System and method for arbitrating interrupts on a daisy-chained architected bus

Abstract

A method and apparatus is provided for assuring balanced servicing of interrupts among devices at the same interrupt level in a daisy-chain architected bus, such as the VME bus, by detecting that a second device on the same level as a first device is having an interrupt serviced, and responsive thereto raising the interrupt level of the first device.

Description

This application is a divisional of U.S. patent application Ser. No. 08/872,590 filed Jun. 10, 1997 now U.S. Pat. No. 6,023,743 by S. L. Kessler for SYSTEM AND METHOD FOR ARBITRATING INTERRUPTS ON A DAISY-CHAINED ARCHITECTED BUS.

BACKGROUND OF THE INVENTION

1. Technical Field of the Invention

This invention pertains to a method and apparatus for servicing interrupts on a daisy-chained bus architecture, such as the VME bus. More particularly, it relates to a method and apparatus for assuring balanced servicing of interrupts from devices on the same interrupt level.

2. Background Art

In a daisy-chained bus, such as the VME bus, no architected method is provided for insuring that interrupts from two different devices which share the same interrupt level will be serviced in a balanced manner. A device that generates interrupts very frequently will be serviced much more often than another device that is plugged into a higher numbered slot on the bus. Bus protocol is such that it is entirely possible that the other device's interrupt will only be serviced after the device in the lower numbered slot has quiesced. Delaying interrupt service cannot be tolerated in many time critical applications.

The daisy-chained interrupt acknowledge architecture of the VME bus assigns interrupt priority primarily by the level of the interrupt and secondarily by the slot location of the interrupting device. When two devices that share the same interrupt level require interrupt service the device in the lower numbered slot will have its interrupt handled first. The other device's interrupt will be left pending. If the lower numbered device's interrupt again becomes active before the higher numbered device's interrupt was serviced the lower numbered device will again have its interrupt serviced by the interrupt handler. The bus architecture has no protocol to insure that higher numbered devices will not be starved for interrupt service. Thus the occurrence of the problem is dependant upon the interrupt service latency in the interrupt handler and the frequency of interrupts from a lower numbered device.

It is, therefore, an object of the invention to assure balanced servicing of interrupts from devices sharing the same interrupt level in a daisy-chain architected bus.

SUMMARY OF THE INVENTION

In accordance with the invention, a method is provided and an apparatus is provided for assuring balanced servicing of interrupts among devices at the same interrupt level in a daisy-chain architected bus by detecting that a second device on the same level as a first device is having an interrupt serviced, and responsive thereto raising the interrupt level of the first device.

Other features and advantages of this invention will become apparent from the following detailed description of the presently preferred embodiment of the invention, taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a high level flow diagram illustrating the system of the invention.

FIG. 2 is a flow diagram illustrating the method steps of the invention.

FIG. 3 is a timing chart illustrating the method of the invention.

FIG. 4 is a logic flow diagram illustrating a preferred embodiment of the invention.

FIG. 5 is a logic flow diagram illustrating in greater detail the interrupt miss logic block 22 of FIG. 4.

FIG. 6 is a timing chart illustrating the operation of the interrupt miss logic 22 and device interrupt logic 24 shown in FIGS. 4 and 5.

BEST MODE FOR CARRYING OUT THE INVENTION

When a VME bus device goes into an interrupt service pending state architected bus protocol only requires that the device look for its interrupt to be acknowledged, that is, serviced. In accordance with the invention, such a device monitors the interrupt acknowledgement activity on the bus. When the device sees that another device, interrupting at the same level, had its interrupt serviced, this device exits from an interrupt service pending state and immediately enters a missed interrupt state.

Entry into the missed interrupt state causes the device to activate an additional, higher priority interrupt level. The higher priority interrupt will now override the lower numbered device whether or not its interrupt becomes active a second time. When the interrupt handler is ready to service another interrupt it will acknowledge this higher priority interrupt. This technique assures that interrupts from two different devices which share the same priority level will be serviced in a balanced manner.

Referring to FIG. 1, device A and device B are attached to bus 40 at slots 10 and 20, respectively, along with interrupt handler 30. Both device A and device B are assigned to the same interrupt level.

Referring to FIG. 2, the method of the invention is presented. In step 100, system reset occurs, resetting all interrupts and states for all devices 10, 20. Consequently, in step 102 there are no interrupts pending for this device 20. In step 104, this device 20 initiates a pending interrupt at level n, and sets its interrupt level n to active. In step 106, an interrupt acknowledge cycle is executed by interrupt handler 30, and is monitored by device 20 to determine if the interrupt acknowledge cycle was at its interrupt level, n. If not, this device 20 continues monitoring in steps 104, 106 for the next interrupt acknowledge cycle. If device 20 determines that the interrupt acknowledge cycle executed by interrupt handler 30 was for level n, in step 108 this device 20 determines if that cycle was acknowledged by this device 20, or by some other device 10. If this device 20 acknowledged the cycle, processing returns to no interrupt pending state 102. If this device 20 was not the one to. acknowledge the cycle, in step 110 this device 20 enters the missed interrupt state and sets interrupt level n+x active. In step 112, this device 20 continues to monitor bus 40 for an interrupt acknowledge cycle executed by interrupt handler 30. Upon detecting that such a cycle occurred at level n+x, and in step 115 that it was acknowledged by some other device 10, in step 110 this device 20 increments its interrupt level to a new n+x (where in step 116 the value of x was increased), and continues monitoring for an interrupt acknowledge cycle. In step 114, upon determining that this device 20 acknowledged an interrupt acknowledge cycle, this device 20 resets its pending interrupt levels and missed interrupt state, and returns to step 102.

Referring to FIG. 3, the various states of devices A at slot 10 and B at slot 20 on VME bus 40 are illustrated with respected to passage of time in unitless integers. Both devices A and B use interrupt level 2. At time 0 device A activates an interrupt at level 2, designated by line 12. At time 1, device B activates an interrupt at level 2, designated by line 22. Thus at time 2, both devices A and B are in the interrupt service pending state, designated by lines 14 and 24, respectively. At time 2, interrupt handler 30 becomes ready to service an interrupt, as is designated by line 32. An interrupt acknowledge cycle starts on VME bus 40 at time 3, as is represented by line 34. Because device A is in the earlier slot 10 of all devices A and B having interrupts pending at the same level 2, its interrupt is serviced at time 4. Device B sees this, enters the missed interrupt state as is represented by line 26, and at time 5 activates an additional interrupt at level 4, as is represented by line 28. Thus, at time 5, device A has no interrupt pending (line 12 is inactive), and device B has two interrupts active, one at level 2 (line 22) and one at level 4 (line 28), and is in the missed interrupt state (line 26 is active.) At time 6 device A enters the interrupt service pending state (line 14 goes active) and activates interrupt level 2 line 12. By time 7 the interrupt handler 30 is ready to service another interrupt. According to VME protocol the highest level interrupt is serviced and an interrupt acknowledge cycle starts at time 8. Device B's interrupt (line 28) is serviced at time 9. By time 10 device B has no interrupt pending (lines 22, 24 and 28 are inactive) and device A has one interrupt active on level 2 (line 12) and is still in the interrupt service pending state (line 14.) Thus, device B, even though in a more remote or higher slot position, has not been blocked out by a pending interrupt at device A, even though devices A and B initially are assigned to the same interrupt level.

Referring to FIG. 4, a logic diagram illustrating the interrupt miss logic of the invention, implemented on a VME bus, will be described. In FIG. 4, two devices 10, 20 are shown in connection with each other and with interrupt handler 30. However, there may be many more devices. Also, for simplicity, the interconnecting signal lines for interrupt miss logic circuit 22 and device interrupt logic with each other and over VME bus 40 with interrupt handler 30 are shown in greater detail only for device 20. Similar interconnections will be required for device 10 logic blocks 12 and 14, and other similarly situated devices (not shown) which implement the interrupt miss logic of this preferred embodiment of the invention.

The VME bus is described in "The VMEbus Specification (conforms to IEEE 1014-1987 and IEC 821 & 297)", published by VITA; 10299 Scottsdale Road, Suite B; Scottsdale, Ariz. 85253-1437; the teachings of which are incorporated herein by reference.

Inputs to interrupt handler 30 on VME bus 40 include VME DTACK line 59 from device interrupt logic 24; and VNE IRQ 4 line 61 and VME IRQ 2 line 52 from interrupt miss logic 22. The outputs from interrupt handler 30 on VME bus 40 include VME DS0 line 57, VME IACK line 54, VME AS line 56, and VME A01, VME A02, VME A03 octal bus 53; and VME IACKIN line 55a to device 10. VME IACKIN line 55 to device 20 is the daisy chained VME IACKOUT line from device 10. Lines 57, 54, 56 and 53 are fed in parallel to all devices 10, 20 on VME bus 40.

Within device 20, the inputs to device interrupt logic 24 include VME IACKIN 55, MISSED INTR STATE line 60, DECODE LVL 2 line 58, and VME DS0 line 57. The outputs of device interrupt logic 24 include VME DTACK 59 to logic 22 and handler 30, daisy chained VME IACKIN line 55b to handler 30, and INTR SERV PENDING line 51 to logic 22. The operation of logic devices 22 and 24 and will be explained hereafter in connection with FIGS. 5 and 6.

Referring to FIG. 5, the interrupt miss logic circuit 22 for implementing a preferred embodiment of the invention on the VME bus includes AND gate 42 feeding the clock input of flip flop 43.

Referring to Table 1, the operation of flip flop 43 is illustrated by a truth table, in which:

D is the data input.

> is the clock input and indicates that the input is sensitive to changes from a logic 0 to a logic 1.

R is the reset input.

Q(T+1) is the flip-flop output at time T+1.

Q(T-1) is the flip-flop output at time T-1.

X is a don't care value: the value can be either a logic 0 or logic 1.

0->1 is a rising edge: the input changing from a logic 0 to a logic 1 at time T.

1->0 is a falling edge: the input changing from a logic 1 to a logic 0 at time T.

TABLE 1
D FLIP FLOP 43 TRUTH TABLE
INPUTS                    OUTPUT
D           >             R           Q(T+1)
X           X             1           0
X           0             0           Q(T-1)
X           1             0           Q(T-1)
X           1→0    0           Q(T-1)
0           0→1    0           0
1           0→1    0           1

In the embodiment of FIG. 5, the data input of flip flop 43 is tied to a logical "1".

The inputs to AND gate 42 are VME IACKIN line 55 inverted by inverter 41, VME AS line 56, VME DS0 line 57, VME IACK line 54, VME DTACK line 59 and DECODE LVL 2 line 58. Inverters 44 and 45 are on the inputs to AND gate 46, which has as inputs inverted VME A01, VME A02 and inverted VME A03 lines 53. The three one bit lines VME A01, VME A02 and VME A03 are used by interrupt handler 30 to signal one of seven (octal: October 1 through October 7) interrupt levels it desires to service. The output of AND gate 46 is DECODE LVL 2 line 58. INTR SERV PENDING line 51 is fed to AND gate 49 and to inverter 47, the output of which is fed to the reset pin of flip flop 43 and inverter 48, the output of which is VME IRQ 2 line 52. INTR SERV PENDING line 51 is also fed to AND gate 49 along with MISSED INTR STATE line 60. The output of AND gate 49 is VME IRQ 4 line 61, which in this example represents the next higher level interrupt (level 4) activated by device 20 when it enters a missed interrupt state (from interrupt level 2.)

Referring now to FIG. 6 in connection with FIGS. 4 and 5, the VME protocol embodiment of the invention will be described, showing the operation of interrupt miss logic 22 and device interrupt logic 24 insofar as these relate to the handling of interrupt misses at devices 10 and 20. The interrupt monitor for device 10 includes AND gates 42 and 46, and flip flop 43. The interrupt generator for device 10 includes AND gate 49 and flip flop 43.

A condition occurs inside device B 20 which causes it to enter an interrupt pending state and activate INTR SERV PENDING line 51 from device interrupt logic block 24 at time 0, and thereafter at time 0.5 issue an interrupt request on its assigned interrupt level 2 by activating VME IRQ 2 line 52. An active interrupt, VME IRQ 2 line 52 from a device 10, 20 causes interrupt handler 30 to initiate an interrupt acknowledge cycle. The start of this cycle is indicated by handler 30 when it places the interrupt level it wishes to acknowledge on VME A03-A01 lines 53 at time 1, by the activation of VME AS line 56 at time 2, and by the activation of VME IACK line 54 at time 2. Handler 30 indicates that it is ready for the interrupting device to respond by activating VME DS0 line 57 at time 2.5. In this example another device, device A 10 intercepts the acknowledge cycle thus preventing device B 20 from having its interrupt acknowledged.

Device B 20 detects that its interrupt level is being acknowledged when DECODE LVL line 58 goes active. The decode of the interrupt level is performed by circuits 44, 45 and 46. DECODE LVL line 58 is raised by device B 20 to indicate that the interrupt level being carried on lines 53 matches VME IRQ 2. Whenever device B 20 has a pending interrupt, that is INTR SERV PENDING line 51 is active, it is able to enter the missed interrupt state because inverter 47 causes the over riding reset input on D flip-flop 43 to be inactive thus allowing MISSED INTR STATE line 60 to go active if and only if device B 20 detects a missed interrupt acknowledge.

A missed interrupt acknowledge is detected by circuits 41 and 42. Device A 10 acknowledges the interrupt cycle by activating interrupt acknowledge signal line VME DTACK 59 at time 3.5, and does not propagate the daisy-chained signal VME IACKIN line 55. The combination of an inactive VME IACKIN line 55, active VME AS line 56, active VME DS0 line 57, active VME IACK line 54, active DECODE LVL 2 line 58, active VME DTACK line 59 causes the output of AND gate 42 to go active. The activation of logic circuit 42 by a 0 to 1 transition on its clock input line from AND gate 42, causes the D flip-flop at logic circuit 43 to activate MISSED INTR STATE line 60 at time 4. Once HISSED INTR STATE line 60 is active device B 20 enters the missed interrupt state and activates the higher priority interrupt VME IRQ 4 at time 4.5. Meanwhile interrupt handler 30 detects an active VNE DTACK line 59 at time 3.5 and thus knows that the interrupt cycle has been acknowledged by a device 10, 20. Interrupt handler 30 then ends the interrupt acknowledge cycle by deactivating VME IACK line 54, VME AS line 56, VME DS0 line 57, and VME A03-A01 lines 53 at time 4.5. Once device A 10 sees an inactive VME DS0 it deactivates VME DTACK line 59 at time 5.

Some time later interrupt handler 30 determines that it can acknowledge the interrupt which is active on VME IRQ 4 line 61. In this example, this new cycle starts at time 7 when interrupt handler 30 places the interrupt level it wishes to acknowledge on VME A03-A01 lines 53. The interrupt handler 30 also activates VME AS line 56, VME IACK line 54 and VME DS0 line 57 at times 7.5 and 8. In this example no other device has an active interrupt on level 4 so device B 20 sees the daisy-chained signal VME IACKIN line 55 go active at time 8. Other logic inside device B 20 responds to the interrupt acknowledge cycle by activating the VME DTACK line 59 at time 9 and by deactivating INTR SER PENDING line 51 at time 9.5. The deactivated INTR SERV PENDING line 51 signal causes VME IRQ 2 line 52 to go inactive by virtue of inverter circuits 47 and 48; cause VME IRQ 4 to go inactive by virtue of AND circuit 49; and causes MISSED INTR STATE line 60 to go inactive by virtue of inverter circuit 47 and flip flop 43. Interrupt handler 30 detects an active VME DTACK line 59 at time 9 and thus knows the interrupt cycle has been acknowledged. Interrupt handler 30 then ends the interrupt acknowledge cycle by deactivating VME IACK line 54, VME AS line 56, VME DS0 line 57, and VME A03-A01 at time 10. Once device B 20 sees an inactive VME DS0 it deactivates VME DTACK line 59 at time 11.

Advantages Over the Prior Art

It is an advantage of the invention that devices operating in earlier slots in a daisy-chain architected interrupt acknowledge bus do not block devices operating in latter slots from having their interrupts acknowledged.

Alternative Embodiments

It will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without departing from the spirit and scope of the invention. In particular, it is within the scope of the invention to provide a memory device, such as a transmission medium, magnetic or optical tape or disc, or the like, for storing signals for controlling the operation of a computer according to the method of the invention and/or to structure its components in accordance with the system of the invention.

Accordingly, the scope of protection of this invention is limited only by the following claims and their equivalents.

Claims

1. A method of preventing blocking out computer devices in a computer system including a central arbitration device for servicing said devices, comprising the steps of:

generating from each of at least two said devices an interrupt pending state at a first priority level;

detecting in a first said device when a second said device has its interrupt serviced; and responsive thereto,

generating from said first device an additional interrupt pending state at a second, higher priority interrupt level; and

operating said central arbitration device responsive to said second, higher priority interrupt level for servicing said first device.

2. A central arbitration unit for servicing devices on a daisy-chained interrupt acknowledge architected bus, comprising:

interrupt cycle acknowledge initiation logic operative in the presence of an first and second interrupt service pending signals from respective first and second devices at a first priority level for signaling readiness to service an interrupt at said first priority level;

interrupt cycle termination logic responsive to acknowledgment from said first for ending said interrupt cycle; and

said interrupt cycle acknowledge initiation logic being further operative in the presence of said second interrupt service pending signal at said first priority level and to a third interrupt service pending signal from said second device at a second, higher priority level for signaling readiness to service an interrupt at said second, higher priority level.

3. An interrupt generator for entering a plurality of interrupt pending states, comprising:

a first interrupt pending state initiator responsive to a device condition for entering a first interrupt pending state at a preassigned priority level; and

a second interrupt pending state initiator responsive to entry into a missed interrupt state for entering a second, concurrent interrupt pending state at a higher priority level.

4. A method for entering a device into two, concurrent interrupt pending states in a daisy-chained system including a central arbiter, comprising the steps of:

responsive to a device condition, signaling to said central arbiter a first interrupt pending state at a preassigned priority level; and

responsive to detecting a missed interrupt, signaling to said central arbiter a second, concurrent interrupt pending state a level higher than said preassigned priority level.

5. A program storage device readable by a machine, tangibly embodying a program of instructions executable by a machine to perform method steps for operating a first device connected to a computer system having a plurality of devices attached to respective slot locations on a daisy-chained interrupt acknowledge architected bus, with each of said plurality of devices assigned one of a plurality of interrupt levels, said computer system including a central arbitration device for servicing said devices first in order of interrupt level and second in order of slot location, said method steps comprising:

upon entering an interrupt pending state at level N, activating an interrupt pending signal line N;

monitoring said bus for an interrupt acknowledge cycle at level N that is acknowledged by a second device and responsive thereto entering a missed interrupt state; and

responsive to entering said missed interrupt state, activating an interrupt pending signal line for an interrupt level of higher priority than N while said interrupt pending signal line N is active.

6. An article of manufacture comprising:

a computer useable medium having computer readable program code means embodied therein for entering a device into two, concurrent interrupt pending states in a daisy-chained system including a central arbiter, the computer readable program means in said article of manufacture comprising:

computer readable program code means for causing a computer to effect responsive to a device condition, signaling to said central arbiter a first interrupt pending state at a preassigned priority level; and

computer readable program code means for causing a computer to effect responsive to detecting a missed interrupt, signaling to said central arbiter a second, concurrent interrupt pending state a level higher than said preassigned priority level.

7. A computer program product or computer program element of preventing blocking out computer devices in a computer system including a central arbitration device for servicing said devices, according to the steps of:

generating from each of at least two said devices an interrupt pending state at a first priority level;

detecting in a first said device when a second said device has its interrupt serviced; and responsive thereto,

generating from said first device an additional interrupt pending state at a second, higher priority interrupt level; and

operating said central arbitration device responsive to said second, higher priority interrupt level for servicing said first device.