A method of reducing electromigration in cu interconnect lines by forming an interim layer of Ca-doped copper seed layer lining a via in a chemical solution and a semi conductor device thereby formed. The method reduces the drift velocity which then decreases the cu migration rate in addition to void formation rate. The method comprises: depositing a cu seed layer in the via; treating the cu seed layer in a chemical solution, selectively forming a cu--Ca--X conformal layer on the cu seed layer, wherein X denotes at least one contaminant; and processing the cu--Ca--X conformal layer, effecting a thin cu--Ca conformal layer on the cu seed layer; annealing the thin cu--Ca conformal layer onto the cu seed layer, removing the at least one contaminant, thereby forming a contaminant-reduced cu--Ca alloy surface on the cu seed layer; electroplating the contaminant-reduced cu--Ca alloy surface with cu, thereby forming a contaminant-reduced cu--Ca/cu interconnect structure; annealing the at least one contaminant-reduced cu--Ca/cu interconnect structure, thereby forming at least one virtually void-less and contaminant-reduced cu--Ca/cu interconnect structure; and chemical mechanical polishing the at least one virtually void-less and contaminant-reduced cu--Ca/cu interconnect structure.

Patent
   6358848
Priority
Nov 30 2000
Filed
Nov 30 2000
Issued
Mar 19 2002
Expiry
Nov 30 2020
Assg.orig
Entity
Large
12
6
all paid
1. A method of fabricating a semiconductor device having a virtually voidless and contaminant-reduced copper-calcium alloy surface on copper (cu--Ca/cu) interconnect structure for reducing electromigration therein, comprising:
A. providing a semiconductor substrate, the substrate having at least one via formed therein;
B. depositing a copper (cu) seed layer in the at least one via for facilitating subsequent formation of at least one cu interconnect line, the cu seed layer lining the at least one via, the cu seed layer comprising at least one intermediate cu layer selected from a group of intermediate copper layers consisting essentially of:
(1) a blanket cu seed layer, and
(2) a partial thickness cu plated layer;
C. treating the cu seed layer in a chemical solution, thereby selectively forming a copper-calcium-X (cu--Ca--X) conformal layer on the cu seed layer, wherein X denotes at least one contaminant;
D. processing the cu--Ca--X conformal layer by a technique selected from a group of techniques consisting essentially of:
(1) proceeding to step (E),
(2) sputtering under an argon (Ar) atmosphere, and
(3) treating in a plasma ambient;
E. annealing the cu--Ca--X conformal layer,
thereby removing the at least one contaminant,
thereby decreasing thickness of the cu--Ca--X conformal layer,
thereby forming a thin cu--Ca conformal layer on the cu seed layer,
whereby the thin cu--Ca conformal layer is alloyed, and
thereby forming a contaminant-reduced cu--Ca alloy surface on the cu seed layer;
F. electroplating the contaminant-reduced cu--Ca alloy surface with cu for filling the volume of the at least one via,
thereby forming the at least one cu interconnect line, and
thereby forming at least one contaminant-reduced cu--Ca/cu interconnect structure in the via;
G. annealing the at least one containment-reduced cu--Ca/cu interconnect structure,
thereby forming at least one virtually voidless and contaminant-reduced cu--Ca/cu interconnect structure;
H. chemical-mechanical-polishing the at least one virtually voidless and contaminant-reduced cu--Ca/cu interconnect structure for forming a planarized surface; and
I. completing formation of the semiconductor device.
2. A method, as recited in claim 1,
wherein the chemical solution comprises an electroless plating solution, and
wherein the electroless plating solution comprises:
a. at least one solvent,
b. at least one cu salt;
C. at least one Ca salt;
d. at least one complexing agent; and
e. at least one reducing agent, (b) through (e) being dissolved in (a).
3. A method, as recited in claim 2, wherein the electroless plating solution further comprises:
f. at least one pH adjuster; and
g. at least one surfactant, (f) and (g) being dissolved in (a).
4. A method, as recited in claim 1, wherein the at least one contaminant is selected from a group of contaminants consisting essentially of carbon (C), sulphur (S), and oxygen (O).
5. A method, as recited in claim 1, wherein the annealing step (E) is performed in a temperature range of 250°C C. to 450°C C. and in an environment selected from a group of environments consisting essentially of a vacuum, an inert gas, and a reducing ambient.
6. A method, as recited in claim 1, wherein the cu--Ca alloy surface is cu-rich with a Ca-doping level in a concentration range of 0.2 atomic % to 5 atomic %.
7. A method, as recited in claim 2, wherein the cu--Ca alloy surface is cu-rich with a Ca-doping level in a concentration range of 0.2 atomic % to 5 atomic %.
8. A method, as recited in claim 3, wherein the cu--Ca alloy surface is cu-rich with a Ca-doping level in a concentration range of 0.2 atomic % to 5 atomic %.
9. A method, as recited in claim 1, further comprising a barrier layer formed in each at least one via.
10. A method, as recited in claim 9,
wherein the barrier layer comprises tantalum (Ta),
wherein the blanket cu seed layer is deposited by a technique selected from a group of techniques consisting essentially of electroplating, electroless plating, chemical vapor deposition (CVD), plasma vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD), and atomic layer deposition (ALD),
wherein the partial thickness cu plated layer is deposited by a technique comprising electroplating, and
wherein the cu interconnect line is dual inlaid.
11. A method of fabricating a semiconductor device having a virtually void-less and contaminant-reduced copper-calcium alloy surface on copper (cu--Ca/cu) interconnect structure for reducing electromigration therein, as recited in claim 9,
wherein the barrier layer comprises tantalum (Ta),
wherein the blanket cu seed layer is deposited by a technique selected from a group of techniques consisting essentially of electroplating, electroless plating, chemical vapor deposition (CVD), plasma vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD), and atomic layer deposition (ALD),
wherein the partial thickness cu plated layer is deposited by a technique comprising electroplating, and
wherein the cu interconnect line is dual inlaid,
wherein the chemical solution comprises an electroless plating solution,
wherein the electroless plating solution comprises:
a. at least one solvent;
b. at least one cu salt,
C. at least one Ca salt,
d. at least one complexing agent,
e. at least one reducing agent,
f. at least one pH adjuster, and
g. at least one surfactant, (b) through (g) being dissolved in (a),
wherein the at least one contaminant is selected from a group of contaminants consisting essentially of carbon (C), sulphur (S), and oxygen (O),
wherein the annealing step (E) is performed in a temperature range of 250°C C. to 450°C C. in an environment selected from a group of environments consisting essentially of a vacuum, an inert gas, and a reducing ambient, and
wherein the contaminant-reduced cu--Ca alloy surface is cu-rich with a Ca-doping level in a concentration range of 0.2 atomic % to 5 atomic %.

This application is related to concurrently filed and commonly assigned applications (serial numbers to be assigned) entitled:

"Chemical Solution for Cu--Ca--O Thin Film Formations on Cu Surfaces;"

"Method of Forming Cu--Ca--O Thin Films on Cu Surfaces in a Chemical Solution and Semiconductor Device Thereby Formed;"

"Method of Calcium Doping a Cu Surface Using a Chemical Solution and Semiconductor Device Thereby Formed;"

"Method of Reducing Carbon, Sulphur, and Oxygen Impurities in a Calcium-Doped Cu Surface and Semiconductor Device Thereby Formed;" and

"Method of Reducing Electromigration in Copper Lines by Calcium-Doping Copper Surfaces in a Chemical Solution and Semiconductor Device Thereby Formed."

The present invention relates to semiconductor devices and their methods of fabrication. More particularly, the present invention relates to the processing of copper interconnect material and the resultant device utilizing the same. Even more particularly, the present invention relates to reducing electromigration in copper interconnect lines by doping their surfaces with barrier material using wet chemical methods.

Currently, the semiconductor industry is demanding faster and denser devices (e.g., 0.05-μm to 0.25-μm) which implies an ongoing need for low resistance metallization. Such need has sparked research into resistance reduction through the use of barrier metals, stacks, and refractory metals. Despite aluminum's (Al) adequate resistance, other Al properties render it less desirable as a candidate for these higher density devices, especially with respect to its deposition into plug regions having a high aspect ratio cross-sectional area. Thus, research into the use of copper as an interconnect material has been revisited, copper being advantageous as a superior electrical conductor, providing better wettability, providing adequate electromigration resistance, and permitting lower depositional temperatures. The copper (Cu) interconnect material may be deposited by chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), sputtering, electroless plating, and electrolytic plating.

However, some disadvantages of using Cu as an interconnect material include etching problems, corrosion, and diffusion into silicon.1 These problems have instigated further research into the formulation of barrier materials for preventing electromigration in both Al and Cu interconnect lines. In response to electromigration concerns relating to the fabrication of semiconductor devices particularly having aluminum-copper alloy interconnect lines, the industry has been investigating the use of various barrier materials such as titanium-tungsten (Ti--W) and titanium nitride (TiN) layers as well as refractory metals such as titanum (Ti), tungsten (W), tantalum (Ta), and molybdenum (Mo) and their silicides.2 Although the foregoing materials are adequate for Al interconnects and Al--Cu alloy interconnects, they have not been entirely effective with respect to all-Cu interconnects. Further, though CVD has been conventionally used for depositing secondary metal(s) on a primary metal interconnect surface, CVD is not a cost-effective method of doping Cu interconnect surfaces with calcium (Ca) ions.

1 Peter Van Zant, Microchip Fabrication: A Practical Guide to Semiconductor Processing, 3rd Ed., p. 397 (1997).

2Id., at 392. Therefore, a need exists for a method of reducing electromigration in Cu interconnect lines by forming an interim protective layer from a chemical solution and a semiconductor device thereby formed.

Accordingly, the present invention provides a method of reducing electromigration in Cu interconnect lines by forming an interim layer of Ca-doped copper seed layer lining a via in a chemical solution and a semiconductor device thereby formed. The present invention method reduces electromigration in Cu interconnect lines by decreasing the drift velocity therein which decreases the Cu migration rate in addition to void formation rate. More specifically, the present invention provides a method of fabricating a semiconductor device having reduced electromigration in its Cu interconnect lines and a device thereby formed, the method comprising: A) providing a semiconductor substrate, the substrate having at least one via formed therein, each at least one via having a volume being optionally lined with a barrier layer; B) depositing a copper (Cu) seed layer in the at least one via for facilitating subsequent formation of at least one Cu interconnect line, the Cu seed layer lining the at least one via, the Cu seed layer comprising at least one intermediate Cu layer selected from a group of intermediate copper layers consisting essentially of: (1) a blanket Cu seed layer, and (2) a partial thickness Cu plated layer; C) treating the Cu seed layer in a chemical solution, thereby selectively forming a copper-calcium-X (Cu--Ca--X) conformal layer on the Cu seed layer, wherein X denotes at least one contaminant, and D) processing the Cu--Ca--X conformal layer by a technique selected from a group of techniques consisting essentially of: (1) proceeding to step E, (2) sputtering under an argon (Ar) atmosphere, and (3) treating in a plasma ambient, thereby effecting a thin Cu--Ca conformal layer on the Cu seed layer; E) annealing the thin Cu--Ca conformal layer onto the Cu seed layer, thereby removing the at least one contaminant, whereby the thin Cu--Ca conformal layer is alloyed, and thereby forming a contaminant-reduced Cu--Ca alloy surface on the Cu seed layer; F) electroplating the Cu--Ca alloy surface with Cu for filling the volume of the at least one via 11, thereby forming the at least one Cu interconnect line, and thereby forming at least one contaminant-reduced Cu--Ca/Cu interconnect structure, comprising the a contaminant-reduced Cu--Ca alloy surface on the Cu seed layer, in the via; G) annealing the at least one contaminant-reduced Cu--Ca/Cu interconnect structure, thereby forming at least one virtually void-less and contaminant-reduced Cu--Ca/Cu interconnect structure; H) chemical mechanical polishing the at least one virtually void-less and contaminant-reduced Cu--Ca/Cu interconnect structure and the optional barrier layer for forming a planarized surface; and I ) completing formation of the semiconductor device. The annealing step primarily removes O and secondarily removes C and S, especially when performed in an environment such as a vacuum, an inert gas, and a reducing ambient such as an ammonia (NH3) plasma. Further, the present invention improves Cu interconnect reliability by enhancing electromigration resistance through impurity-level control, thereby balancing electromigration performance against low resistivity requirements.

For a better understanding of the present invention, reference is made to the below-referenced accompanying drawings.

FIG. 1 is a cross-sectional view of a semiconductor substrate having formed therein a via, optionally lined with a barrier layer, the optional barrier layer having deposited a blanket Cu seed layer, for subsequent formation of a Cu interconnect line, in accordance with the present invention.

FIG. 2 is a cross-sectional view of a semiconductor substrate having formed therein a via with an optional barrier layer; the optional barrier layer having deposited a blanket Cu seed layer, as shown in FIG. 1; the blanket Cu seed layer having selectively formed thereon a Cu--Ca--X conformal layer by treating the blanket Cu seed layer in a chemical solution; the Cu--Ca--X conformal layer being optionally treated by a process such as Ar sputtering, in accordance with the present invention.

FIG. 3 is a cross-sectional view of a semiconductor substrate having formed therein a via with an optional barrier layer; the optional barrier layer having deposited a blanket Cu seed layer, as shown in FIG. 1; the blanket Cu seed layer having selectively formed thereon a Cu--Ca--X conformal layer by treating the blanket Cu seed layer in a chemical solution; the Cu--Ca--X conformal layer being optionally treated by a process such as Ar sputtering, as shown in FIG. 2, the Cu--Ca--X conformal layer being annealed onto the blanket Cu seed layer, thereby forming a contaminant-reduced Cu--Ca alloy surface on the blanket Cu seed layer, in accordance with the present invention.

FIG. 4 is a cross-sectional view of a semiconductor substrate having formed therein a via with an optional barrier layer; the optional barrier layer having deposited a blanket Cu seed layer, as shown in FIG. 1; the blanket Cu seed layer having selectively formed thereon a Cu--Ca--X conformal layer by treating the blanket Cu seed layer in a chemical solution; the Cu--Ca--X conformal layer being optionally treated by a process such as Ar sputtering, as shown in FIG. 2, the Cu--Ca--X conformal layer being annealed onto the blanket Cu seed layer, thereby forming a contaminant-reduced Cu--Ca alloy surface on the blanket Cu seed layer, as shown in FIG. 3, the contaminant-reduced Cu--Ca alloy surface having been further electroplated with Cu for filling the via, thereby forming a Cu interconnect line; and the Cu interconnect line also being annealed, in accordance with the present invention.

FIG. 5 is a cross-sectional view of a semiconductor substrate having formed therein a via with an optional barrier layer; the optional barrier layer having deposited a blanket Cu seed layer, as shown in FIG. 1; the blanket Cu seed layer having selectively formed thereon a Cu--Ca--X conformal layer by treating the blanket Cu seed layer in a chemical solution; the Cu--Ca--X conformal layer being optionally treated by a process such as Ar sputtering, as shown in FIG. 2, the Cu--Ca--X conformal layer being annealed onto the blanket Cu seed layer, thereby forming a contaminant-reduced Cu--Ca alloy surface on the blanket Cu seed layer, as shown in FIG. 3, the contaminant-reduced Cu--Ca alloy surface having been further electroplated with Cu for filling the via, thereby forming a contaminant-reduced Cu--Ca/Cu interconnect structure, comprising the contaminant-reduced Cu--Ca alloy surface, the contaminant-reduced Cu--Ca/Cu interconnect structure also being annealed, as shown in FIG. 4, further chemical mechanical polishing the Cu interconnect line, the Cu--Ca alloy surface, the blanket Cu seed layer, and the optional barrier layer for forming a planarized surface, thereby forming a virtually void-less and contaminant-reduced Cu--Ca/Cu interconnect structure in accordance with the present invention.

FIG. 6 is a cross-sectional view of a semiconductor substrate having formed therein a via having an optional barrier layer, the optional barrier layer having deposited a blanket Cu seed layer, as shown in FIG. 1, the blanket Cu seed layer being partially electroplated with Cu, thereby forming a partial thickness Cu plated layer, in accordance with the present invention.

FIG. 7 is a cross-sectional view of a semiconductor substrate having formed therein a via having an optional barrier layer, the optional barrier layer having deposited a blanket Cu seed layer, as shown in FIG. 1, the blanket Cu seed layer being partially electroplated with Cu, thereby forming a partial thickness Cu plated layer, as shown in FIG. 6, the partial thickness Cu plated layer having selectively formed thereon a Cu--Ca--X conformal layer by treating the partial thickness Cu plated layer in a chemical solution, thereby forming a Cu--Ca conformal layer; the Cu--Ca conformal layer being optionally treated by a process such as Ar sputtering; the Cu--Ca--X conformal layer being annealed onto the partial thickness Cu plated layer, thereby decreasing its thickness to form a thin Cu--Ca conformal layer, and thereby forming a contaminant-reduced Cu--Ca alloy surface on the partial thickness Cu plated layer, in accordance with the present invention.

FIG. 8 is a cross-sectional view of a semiconductor substrate having formed therein a via having an optional barrier layer, the optional barrier layer having deposited a blanket Cu seed layer, as shown in FIG. 1, the blanket Cu seed layer being partially electroplated with Cu, thereby forming a partial thickness Cu plated layer, as shown in FIG. 6, the partial thickness Cu plated layer having selectively formed thereon a Cu--Ca--X conformal layer by treating the partial thickness Cu plated layer in a chemical solution, thereby forming a Cu--Ca conformal layer; the Cu--Ca conformal layer being optionally treated by a process such as Ar sputtering; the Cu--Ca--X conformal layer being annealed onto the partial thickness Cu plated layer, thereby decreasing its thickness to form a thin Cu--Ca conformal layer, and thereby forming a Cu--Ca alloy surface on the partial thickness Cu plated layer, as shown in FIG. 7, the Cu--Ca alloy surface having been further electroplated with Cu for filling the via, and thereby forming a Cu interconnect line, the Cu interconnect line also being annealed; further chemical mechanical polishing the Cu interconnect line, the Cu--Ca alloy surface, the partial thickness Cu plated layer, the blanket Cu seed layer, and the optional barrier layer for forming a planarized surface, in accordance with the present invention.

FIG. 9 is a flowchart of a method for fabricating a semiconductor device having a virtually void-less contaminant-reduced Ca--Cu/Cu interconnect line structure for reducing electromigration therein, in accordance with the present invention.

Reference numbers refer to the same or equivalent parts of the present invention throughout the several figures of the drawings.

FIG. 1 is a cross-sectional view of a semiconductor substrate 10 having formed therein a via 11, optionally lined with a barrier layer 12 such as Ta, the optional barrier layer 12 having deposited a blanket Cu seed layer 13, for subsequent formation of a Cu interconnect line, in accordance with the present invention.

FIG. 2 is a cross-sectional view of a semiconductor substrate 10 having formed therein a via 11, optionally lined with a barrier layer 12, the optional barrier layer 12 having deposited a blanket Cu seed layer 13, for subsequent formation of a Cu interconnect line, as shown in FIG. 1, the blanket Cu seed layer 13 having selectively formed thereon a Cu--Ca--X conformal layer 30 by treating the blanket Cu seed layer 13 in a chemical solution, where contaminant X=C, S, or O; the Cu--Ca--X conformal layer 30 being optionally treated by a process such as Ar sputtering, thereby contributing to decreasing its thickness to form a thin Cu--Ca conformal layer 30a, in accordance with the present invention.

FIG. 3 is a cross-sectional view of a semiconductor substrate 10 having formed therein a via 11, optionally lined with a barrier layer 12, the optional barrier layer 12 having deposited a blanket Cu seed layer 13, for subsequent formation of a Cu interconnect line, as shown in FIG. 1, the blanket Cu seed layer 13 having selectively formed thereon a Cu--Ca--X conformal layer 30 by treating the blanket Cu seed layer 13 in a chemical solution; the Cu--Ca conformal layer 30 being optionally treated by a process such as Ar sputtering, thereby contributing to decreasing its thickness to form a thin Cu--Ca conformal layer 30a, as shown in FIG. 2, the Cu--Ca--X conformal layer 30 being annealed onto the blanket Cu seed layer 13, thereby decreasing its thickness to form the thin Cu--Ca conformal layer 30a, the thin Cu--Ca conformal layer 30a being alloyed, and thereby forming a Cu--Ca alloy surface 30b on the blanket Cu seed layer 13, in accordance with the present invention.

FIG. 4 is a cross-sectional view of a semiconductor substrate 10 having formed therein a via, optionally lined with a barrier layer 12, the optional barrier layer 12 having deposited a blanket Cu seed layer 13, for subsequent formation of a Cu interconnect line 20, as shown in FIG. 1; the blanket Cu seed layer 13 having selectively formed thereon a Cu--Ca--X conformal layer 30 by treating the blanket Cu seed layer 13 in a chemical solution; the Cu--Ca--X conformal layer 30 being optionally treated by a process such as Ar sputtering, thereby contributing to decreasing its thickness to form a thin Cu--Ca conformal layer 30a, as shown in FIG. 2; the Cu--Ca--X conformal layer 30 being annealed onto the blanket Cu seed layer 13, thereby decreasing its thickness to form the thin Cu--Ca conformal layer 30a; the thin Cu--Ca conformal layer 30a being alloyed, and thereby forming a Cu--Ca alloy surface 30b on the blanket Cu seed layer 13, as shown in FIG. 3; the Cu--Ca alloy surface 30b having been further electroplated with Cu for filling the via 11, and thereby forming a Cu interconnect line 20; and the Cu interconnect line 20 also being annealed, in accordance with the present invention.

FIG. 5 is a cross-sectional view of a semiconductor substrate 10 having formed therein a via, optionally lined with a barrier layer 12, the optional barrier layer 12 having deposited a blanket Cu seed layer 13, for subsequent formation of a Cu interconnect line 20, as shown in FIG. 1; the blanket Cu seed layer 13 having selectively formed thereon a Cu--Ca--X conformal layer 30 by treating the blanket Cu seed layer 13 in a chemical solution; the Cu--Ca--X conformal layer 30 being optionally treated by a process such as Ar sputtering, thereby contributing to decreasing its thickness to form a thin Cu--Ca conformal layer 30a, as shown in FIG. 2; the Cu--Ca--X conformal layer 30 being annealed onto the blanket Cu seed layer 13, thereby decreasing its thickness to form the thin Cu--Ca conformal layer 30a; the thin Cu--Ca conformal layer 30a being alloyed, and thereby forming a Cu--Ca alloy surface 30b on the blanket Cu seed layer 13, as shown in FIG. 3; the Cu--Ca alloy surface 30b having been further electroplated with Cu for filling the via 11, and thereby forming a Cu interconnect line 20; the Cu interconnect line 20 also being annealed, thereby forming a composite interconnect structure comprising the Cu interconnect line 20, the Cu--Ca alloy surface 30b, and the blanket Cu seed layer 13, as shown in FIG. 4; and further chemical-mechanical-polishing (CMP) the Cu interconnect line 20, the Cu--Ca alloy surface 30b, the blanket Cu seed layer 13, and the optional barrier layer 12 for forming a planarized surface 40, in accordance with the present invention.

FIG. 6 is a cross-sectional view of a semiconductor substrate 10 having formed therein a via 11, optionally lined with a barrier layer 12; the optional barrier layer 12 having deposited a blanket Cu seed layer 13, for subsequent formation of a Cu interconnect line 20, as shown in FIG. 1; the blanket Cu seed layer 13 being partially electroplated with Cu, thereby forming a partial thickness Cu plated layer 14, in accordance with the present invention.

FIG. 7 is a cross-sectional view of a semiconductor substrate 10 having formed therein a via 11, optionally lined with a barrier layer 12; the optional barrier layer 12 having deposited a blanket Cu seed layer 13, for subsequent formation of a Cu interconnect line 20; the blanket Cu seed layer 13 being partially electroplated with Cu, thereby forming a partial thickness Cu plated layer 14, as shown in FIG. 6; the partial thickness Cu plated layer 14 having selectively formed thereon a Cu--Ca--X conformal layer 30 by treating the partial thickness Cu plated layer 14 in a chemical solution; the Cu--Ca conformal layer 30 being optionally treated by a process such as Ar sputtering, thereby contributing to decreasing its thickness to form a thin Cu--Ca conformal layer 30a; the Cu--Ca--X conformal layer 30 being annealed onto the partial thickness Cu plated layer 14, thereby decreasing its thickness to form the thin Cu--Ca conformal layer 30a; the thin Cu--Ca conformal layer 30a being alloyed, and thereby forming a Cu--Ca alloy surface 30b on the partial thickness Cu layer plated 14, in accordance with the present invention.

FIG. 8 is a cross-sectional view of a semiconductor substrate 10 having formed therein a via, optionally lined with a barrier layer 12; the optional barrier layer 12 having deposited a blanket Cu seed layer 13 for subsequent formation of a Cu interconnect line 20; the blanket Cu seed layer 13 being partially electroplated with Cu, thereby forming a partial thickness Cu plated layer 14, as shown in FIG. 6; the partial thickness plated Cu layer 14 having selectively formed thereon a Cu--Ca--X conformal layer 30 by treating the partial thickness plated Cu layer 14 in a chemical solution; the Cu--Ca conformal layer 30 being optionally treated by a process such as Ar sputtering, thereby contributing to decreasing its thickness to form a thin Cu--Ca conformal layer 30a; the Cu--Ca--X conformal layer 30 being annealed onto the partial thickness Cu plated layer 14, thereby forming the thin Cu--Ca conformal layer 30a, the thin Cu--Ca conformal layer 30a being alloyed, and thereby forming a contaminant-reduced Cu--Ca alloy surface 30b on the partial thickness Cu plated layer 14, as shown in FIG. 7; the contaminant-reduced Cu--Ca alloy surface 30b having been further electroplated with Cu for filling the via, and thereby forming the Cu interconnect line 20, the Cu interconnect line 20 also being annealed, thereby forming a virtually void-less contaminant-reduced Cu--Ca/Cu interconnect structure 21, the virtually void-less contaminant-reduced Cu--Ca/Cu interconnect structure 21 comprising a composite structure, the composite structure comprising the Cu interconnect line 20, the Cu--Ca alloy surface 30b, the blanket Cu seed layer 13, the partial thickness plated Cu layer 14; and further chemical-mechanical-polishing (CMP) the virtually void-less contaminant-reduced Cu--Ca/Cu interconnect structure 21 and the optional barrier layer 12 for forming a planarized surface 40, in accordance with the present invention.

FIG. 9 is flowchart of a method M for fabricating a semiconductor device, having a virtually void-less and contaminant-reduced Cu--Ca/Cu interconnect line structure 21 for reducing electromigration therein, comprising: A) providing a semiconductor substrate 10, the substrate 10 having at least one via 11 formed therein, each at least one via 11 having a volume being optionally and partially lined with a barrier layer 12, as indicated by block 901; B) depositing a copper (Cu) seed layer in the at least one via for facilitating subsequent formation of at least one Cu interconnect line 20, the Cu seed layer lining the at least one via 11, the Cu seed layer comprising at least one intermediate Cu layer selected from a group of intermediate copper layers consisting essentially of: (1) a blanket Cu seed layer 13, and (2) a partial thickness Cu plated layer 14, as indicated by block 902; C) treating the Cu seed layer in a chemical solution, thereby selectively forming a copper-calcium-X (Cu--Ca--X) conformal layer 30 on the Cu seed layer, wherein X denotes at least one contaminant, as indicated by block 903; and D) processing the Cu--Ca--X conformal layer 30 by a technique selected from a group of techniques consisting essentially of (1) proceeding to step E, as indicated by arrow A and block 906, (2) sputtering under an Ar atmosphere, as indicated by block 904, and (3) treating in a plasma ambient, thereby removing the at least one contaminant, as indicated by block 905, contributing to forming a thin Cu--Ca conformal layer 30a on the Cu seed layer; E) annealing the thin Cu--Ca conformal layer 30a onto the Cu seed layer, thereby forming the thin Cu--Ca conformal layer 30a, whereby the thin Cu--Ca conformal layer is alloyed, and thereby forming a contaminant-reduced Cu--Ca alloy surface 30b on the Cu seed layer, as indicated by block 906; F) electroplating the contaminant-reduced Cu--Ca alloy surface 30b with Cu for filling the volume of the at least one via 11, thereby forming the at least one Cu interconnect line 20, and thereby forming, at least one contaminant-reduced Cu--Ca/Cu interconnect structure, comprising the contaminant-reduced Cu--Ca alloy surface 30b, in the via, as indicated by block 907; G) annealing the at least one virtually contaminant-reduced Cu--Ca/Cu interconnect structure, thereby forming at least one virtually void-less and contaminant-reduced Cu--Ca/Cu interconnect structure 21, as indicated by block 908; H) chemical mechanical polishing the at least one virtually void-less and contaminant-reduced Cu--Ca/Cu interconnect structure 21 and the optional barrier layer 12 for forming a planarized surface 40, as indicated by block 909; and I ) completing formation of the semiconductor device, as indicated by block 910, in accordance with the present invention.

The method M and devices thereby formed may also comprise additional features wherein the optional barrier layer 12 comprises tantalum (Ta); wherein the blanket Cu seed layer 13 is deposited by a technique selected from a group of techniques consisting essentially of electroplating, electroless plating, chemical vapor deposition (CVD), plasma vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD), and atomic layer deposition (ALD); wherein the partial thickness Cu plated layer 14 is deposited by a technique comprising electroplating; wherein the Cu interconnect line 20 is dual inlaid; wherein the chemical solution comprises an electroless plating solution; wherein the electroless plating solution comprises at least one Cu salt, at least one Ca salt, at least one complexing agent, at least one reducing agent, at least one pH adjuster, and at least one surfactant; wherein the at least one contaminant is selected from a group of contaminants consisting essentially of carbon (C), sulphur (S), and oxygen (0); wherein the annealing step (E) is performed in a temperature range of 250°C C. to 450°C C. and under vacuum; and wherein the Cu--Ca alloy surface is Cu-rich with a Ca-doping level in a concentration range of 0.2 atomic % to 5 atomic %. The annealing step primarily removes O and secondarily removes C and S, especially when performed in an environment such as a vacuum, an inert gas, and a reducing ambient such as an ammonia (NH3) plasma.

Alternatively, a device having a greater tolerance of impurities may also be formed (e.g., more impurity-tolerant applications): (1) where high levels of C and S impurities are tolerable in the Cu--Ca--X film, neither the Ar-sputtering step nor the annealing step need be performed; (2) where low levels of C and S impurities are tolerable in the Cu--Ca--X film, the annealing step need be performed; (3) where high levels of C, S, and O impurities are tolerable in the Cu--Ca film, the Ar-sputtering step need not be performed; however, (4) where low to zero levels of C, S, and O impurities are tolerable in the Cu--Ca film, the full process (i.e., method M) must be performed.

Information as herein shown and described in detail is fully capable of attaining the above-described object of the invention, the presently preferred embodiment of the invention, and is, thus, representative of the subject matter which is broadly contemplated by the present invention. The scope of the present invention fully encompasses other embodiments which may become obvious to those skilled in the art, and is to be limited, accordingly, by nothing other than the appended claims, wherein reference to an element in the singular is not intended to mean "one and only one" unless explicitly so stated, but rather "one or more." All structural and functional equivalents to the elements of the above-described preferred embodiment and additional embodiments that are known to those of ordinary skill in the art are hereby expressly incorporated by reference and are intended to be encompassed by the present claims. Moreover, no requirement exists for a device or method to address each and every problem sought to be resolved by the present invention, for such to be encompassed by the present claims. Furthermore, no element, component, or method step in the present disclosure is intended to be dedicated to the public regardless of whether the element, component, or method step is explicitly recited in the claims. However, it should be readily apparent to those of ordinary skill in the art that various changes and modifications in form, semiconductor material, and fabrication material detail may be made without departing from the spirit and scope of the inventions as set forth in the appended claims. No claim herein is to be construed under the provisions of 35 U.S. C. 112, sixth paragraph, unless the element is expressly recited using the phrase "means for."

Lopatin, Sergey

Patent Priority Assignee Title
11075146, Aug 31 2005 Micron Technology, Inc. Microfeature workpieces having alloyed conductive structures, and associated methods
6482656, Jun 04 2001 GLOBALFOUNDRIES U S INC Method of electrochemical formation of high Tc superconducting damascene interconnect for integrated circuit
6646353, Nov 30 2000 Advanced Micro Devices, Inc. Semiconductor device having reduced electromigration in copper lines with calcium-doped copper surfaces formed by using a chemical solution
6740221, Mar 15 2001 Applied Materials Inc. Method of forming copper interconnects
6825129, Jun 12 2001 Hynix Semiconductor Inc. Method for manufacturing memory device
6872657, Aug 08 2003 Agency for Science, Technology and Research Method to form copper seed layer for copper interconnect
6943111, Feb 10 2003 Taiwan Semiconductor Manufacturing Company, Ltd. Barrier free copper interconnect by multi-layer copper seed
7215024, Jan 24 2003 Taiwan Semiconductor Manufacturing Company, Ltd. Barrier-less integration with copper alloy
7239747, Jan 24 2002 CHATTERBOX SYSTEMS, INC Method and system for locating position in printed texts and delivering multimedia information
7400043, Mar 29 2002 Micron Technology, Inc. Semiconductor constructions
7423345, Mar 29 2002 Micron Technology, Inc. Semiconductor constructions comprising a layer of metal over a substrate
7923806, Mar 28 2003 Fujitsu Semiconductor Limited Embedded wiring in copper damascene with void suppressing structure
Patent Priority Assignee Title
5143867, Feb 13 1991 International Business Machines Corporation Method for depositing interconnection metallurgy using low temperature alloy processes
5893752, Dec 22 1997 SHENZHEN XINGUODU TECHNOLOGY CO , LTD Process for forming a semiconductor device
5969422, May 15 1997 AMD TECHNOLOGIES HOLDINGS, INC ; GLOBALFOUNDRIES Inc Plated copper interconnect structure
6090710, Jun 27 1995 GLOBALFOUNDRIES Inc Method of making copper alloys for chip and package interconnections
6181012, Apr 27 1998 GLOBALFOUNDRIES Inc Copper interconnection structure incorporating a metal seed layer
6258717, Jul 30 1999 International Business Machines Corporation Method to produce high quality metal fill in deep submicron vias and lines
//
Executed onAssignorAssigneeConveyanceFrameReelDoc
Nov 29 2000LOPATIN, SERGEYAdvanced Micro Devices, INCASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS 0113640778 pdf
Nov 30 2000Advanced Micro Devices, Inc.(assignment on the face of the patent)
Date Maintenance Fee Events
Aug 26 2005M1551: Payment of Maintenance Fee, 4th Year, Large Entity.
Aug 21 2009M1552: Payment of Maintenance Fee, 8th Year, Large Entity.
Aug 21 2013M1553: Payment of Maintenance Fee, 12th Year, Large Entity.


Date Maintenance Schedule
Mar 19 20054 years fee payment window open
Sep 19 20056 months grace period start (w surcharge)
Mar 19 2006patent expiry (for year 4)
Mar 19 20082 years to revive unintentionally abandoned end. (for year 4)
Mar 19 20098 years fee payment window open
Sep 19 20096 months grace period start (w surcharge)
Mar 19 2010patent expiry (for year 8)
Mar 19 20122 years to revive unintentionally abandoned end. (for year 8)
Mar 19 201312 years fee payment window open
Sep 19 20136 months grace period start (w surcharge)
Mar 19 2014patent expiry (for year 12)
Mar 19 20162 years to revive unintentionally abandoned end. (for year 12)