A method for forming a multi-level metal interconnection, comprising the step of forming a first metal interconnection over an underlying layer; forming an insulating layer having a selected thickness over the underlying layer including the first metal interconnection; etching the insulating layer to form a contact hole, thereby exposing the first metal interconnection; forming a metal plug in the contact hole to contact with the first metal interconnection; etching the insulating layer by a portion of the selected thickness; forming a pair of metal spacers in sidewalls of the metal plug over the insulating layer; and forming a second metal interconnection over the insulating layer to contact with the first metal interconnection through one of the metal spacers.
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1. A method for forming a multi-level metal interconnection, comprising the steps of:
forming a first metal interconnection over an underlying layer; forming an insulating layer having a selected thickness over the underlying layer including the first metal interconnection; etching the insulating layer to form a contact hole, thereby exposing the first metal interconnection; forming a metal plug in the contact hole to contact with the first metal interconnection; etching the insulating layer by a portion of the selected thickness; forming a pair of metal spacers in sidewalls of the metal plug over the insulating layer; and forming a second metal interconnection over the insulating layer to contact with the first metal interconnection through one of the metal spacers.
6. A method for forming a multi-level metal interconnection, comprising the steps of:
forming a first metal interconnection over an underlying layer; forming a first insulating layer having a selected thickness over the underlying layer including the first metal interconnection; etching the first insulating layer to a portion of the selected thickness so that a height of the first insulating layer is lower than that of the first metal interconnection; forming metal spacers in sidewalls of the first metal interconnection over the first insulating layer; forming a planarization layer over the first insulating layer including the metal spacers and the first metal interconnection; etching the first insulating layer and the planarization layer to form a contact hole, thereby exposing the first metal interconnection; and forming a second metal interconnection to contact with the metal interconnection through the contact hole.
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1. Field of the Invention
This invention relates to a method for fabricating a semiconductor device, and more particularly to a method for forming a multi-level interconnection in a semiconductor device.
2. Description of the Related Art
When a fine pattern is formed as high integration of semiconductor devices, assurance of overlap margin due to reduction of linewidth is demanded.
As shown in
However, the prior method using the metal plug has a draw back as follows. After etching the metal film for second metal interconnection, a tip is formed in the metal stringer within the contact hole, thereby degrading the device property and acting as the defect factor to reduce yield. Furthermore, the pattern overlap margin between the second metal interconnection formed over the insulating layer and the first metal interconnection formed below the insulating layer is reduced and the production yield and property are degraded with reduction of process margin, as the pattern size is diminished more and more.
As shown in
The prior method has drawbacks as follows. As high integration of semiconductor memory devices, a line and a space of the metal interconnection are smaller so that a void is generated in forming the insulation layer for metal interconnection as shown in FIG. 3A. The void brings about lifting phenomenon of the insulating layer in the following heat treatment so that the critical damage of the device is occurred.
Besides, if misalignment is occurred in the photoetching process for forming the contact hole, when the second metal interconnection is formed following the contact hole formation process using the photosensitive, the overlap margin becomes smaller as shown in FIG. 3B. Accordingly, the electrical property of the device is degraded and mass production is very difficult with lack of the photoetching process margin.
It is an object of the present invention to provide a method for forming a multi-level metal interconnection of a semiconductor device with a metal plug, capable of improving the overlap margin between patterns and metal interconnection property using a metal spacer.
It is another object of the present invention to provide a method for forming a multi-level metal interconnection of a semiconductor device, capable of improving the planarization degree of the metal intermediate insulating layer, preventing occurrence of a void and assuring the sufficient process margin using a metal spacer.
According to an aspect of the present invention, there is provided to a method for forming a multi-level metal interconnection of a semiconductor device, comprising the steps of: forming a first metal interconnection on an underlying layer; forming an insulating layer over the underlying layer including the first metal interconnection; etching the insulating layer to form a contact hole, thereby exposing the first metal interconnection; forming a metal plug in the contact hole; further etching the insulating layer by a thickness; forming metal spacers in sidewalls of the metal plug over the insulating layer; and forming a second metal interconnection over the insulating layer to contact with the first metal interconnection through the metal spacer.
In the formation step of the metal plug, a tungsten plug is deposited over the insulating layer including the contact hole and then etched with a CMP process to form the metal plug. In the etching step of the insulating layer, the insulating layer is etched using an oxide target to have a height lower than the metal plug. Following the formation step of the second metal interconnection, the method of this invention further includes the step of removing the metal spacer which is not contacted with the metal plug.
There is also provided to a method for forming a multi-level metal interconnection of a semiconductor device, comprising the steps of: forming a first metal interconnection on an underlying layer; forming a first insulating layer over the underlying layer including the first metal interconnection; etching the first insulating layer to have a height lower than the first metal interconnection, thereby forming a height difference; forming metal spacers in sidewalls of the first metal interconnection over the first insulating layer; forming a planarization film over the whole surface of the underlying layer including the metal spacers; etching the planarization film to form a contact hole, thereby exposing the first metal interconnection; and forming a second metal interconnection over the planarization film to contact with the first metal interconnection through the contact hole.
The first insulating layer is etched by a wet or dry etching process. In etching the first insulating layer, a freon gas or a diluted gas of CO, O2, Ar and He is used to increase the etching selectivity to the first metal interconnection.
The planarization film formation step includes the step of forming a second insulating layer having good planarization property over the underlying layer and the step of forming a third insulating layer over the second insulating layer.
The objects and features of the invention may be understood with reference to the following detailed description of an illustrative embodiment of the invention, taken together with the accompanying drawings in which:
FIG. 3A and
Referring to
Referring to
Referring to
According to the one embodiment of this invention mentioned above, the contact area between the metal plug 34' and the second metal interconnection 37 is increased by forming the metal spacers. The contact resistance is reduced and the overlap margin between the metal plug and the second metal interconnection can be improved. Therefore, it can solve the problem of the remaining of the metal stringer after the formation of the second metal interconnection in the prior art so that the device property can be improved.
Referring to
A metal film for spacers 44 is deposited over the substrate as shown in
As shown in
According to another embodiment of this invention, the first insulating layer is etched to have a step difference from the first metal interconnection 42 so that the following planarization process is carried out with ease and occurrence of void is prevented. Besides, the metal spacers are formed in sidewalls of the first metal interconnection so that the mutual contact between the first and second metal interconnections through the metal spacers is accomplished, although the misalignment between the first and second metal interconnections is occurred in forming the contact hole. Therefore, the process margin is sufficiently assured in forming the photosensitive film for contact hole.
As above described, the method for forming a multi-level metal interconnection forms a second metal interconnection following metal spacers to assure the sufficient overlap margin between first and second metal interconnections and then to improve interconnection property of the device, thereby improve the yield and fabricating the high degree device with ease. Besides, the planarization process is carried out with ease, following the formation of the metal spacers, thereby preventing void from generating and improving the yield.
While the invention has been particularly shown and described with respect to preferred embodiment thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and the scope of the invention as defined by the following claims.
Kim, Wan Soo, Han, Min Sub, Lee, Tae Gook, Kang, Byoung Ju
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