A low-power high-frequency bipolar transistor is formed to have a small self-aligned intrinsic base region, and small self-aligned extrinsic base and emitter regions that contact the intrinsic base region. The small regions reduce the base resistance, the base-to-collector capacitance, and the base-to-emitter capacitance.
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19. A bipolar transistor formed on a wafer, the wafer having a buried layer and a first epitaxial layer of a first conductivity type, the first epitaxial layer being formed over the buried layer and having a surface and a smaller dopant concentration than the buried layer, the transistor comprising:
an intrinsic base region of a second conductivity type formed on the surface of the first epitaxial layer in the opening; a layer of isolation material formed on the surface of the first epitaxial layer to adjoin the intrinsic base region; a first spacer formed on the layer of isolation material and the intrinsic base region; a second spacer formed on the layer of isolation material and the intrinsic base region, the second spacer being spaced apart from the first spacer; an extrinsic base formed on the layer of isolation material; an intrinsic emitter region formed in the intrinsic base region; and an extrinsic emitter formed on the layer of isolation material; a first conductive spacer formed on the first isolating spacer to contact the extrinsic base and the intrinsic base region; and a second conductive spacer formed on the second isolating spacer to contact the extrinsic emitter and the intrinsic emitter region of the intrinsic base region, the second conductive spacer being spaced apart from the first conductive spacer.
1. A method for forming a bipolar transistor on a wafer, the wafer having a buried layer and a first epitaxial layer of a first conductivity type, the first epitaxial layer being formed over the buried layer and having a smaller dopant concentration than the buried layer, the method comprising the steps of:
forming a layer of isolation material on the first epitaxial layer; forming an extrinsic base and an extrinsic emitter on the layer of isolation material, the extrinsic base having a second conductivity type and being spaced apart from the extrinsic emitter, the extrinsic emitter having the first conductivity type; etching the layer of isolation material to form a first opening in the layer of isolation material, the first opening being between the extrinsic base and the extrinsic emitter, and exposing a surface of the first epitaxial layer; forming an intrinsic base region on the surface of the first epitaxial layer in the first opening; forming a first insulating spacer, a second insulating spacer, and an insulating plug on the intrinsic base region in the first opening, the first insulating spacer contacting the extrinsic base, the second insulating spacer being spaced apart from the first insulating spacer and contacting the extrinsic emitter, the insulating plug being spaced apart from the first and second insulating spacers, and formed between the first and second insulating spacers; forming a base spacer that contacts the extrinsic base and the intrinsic base between the first insulating spacer and the insulating plug, and an emitter spacer that contacts the extrinsic emitter and the intrinsic base between the second insulating spacer and the insulating plug.
2. The method of
forming a first layer of polysilicon on the layer of isolation material, the first layer of polysilicon having a base region and an emitter region; doping the base region to have the second conductivity type, and the emitter region to have the first conductivity type; and etching the first layer of polysilicon to form the extrinsic base and the extrinsic emitter.
3. The method of
4. The method of
5. The method of
6. The method of
7. The method of
forming a first layer of insulation material on the extrinsic base, the extrinsic emitter, the intrinsic base, and the layer of isolation material; forming a first insulating region and a second insulating region on the first layer of insulation material over the intrinsic base region in the first opening, the first insulating region being adjacent to the extrinsic base, the second insulating region being spaced apart from the first insulating region, and adjacent to the extrinsic emitter, the first and second insulating regions defining a gap therebetween; forming a second layer of insulation material on the first layer of insulation material and the first and second insulating regions to fill up the gap; planarizing to remove the first layer of insulation material from over the extrinsic base and the extrinsic emitter, expose the first and second insulating regions, and define an insulation plug between the first and second insulating regions; and removing portions of the first layer of insulation material and the insulating plug, and the first and second insulating regions to expose a first area and a second area on the instrinsic base, the first and second areas being spaced apart.
8. The method of
etching away a portion of the first and second insulating regions to leave remaining portions; etching away a portion of the first isolation material to expose a portion of the extrinsic base and the extrinsic emitter; removing the remaining portions of the first and second insulating regions; and removing a portion of the first isolation material to expose the first area and the second area on the instrinsic base.
9. The method of
10. The method of
11. The method of
forming a first layer of polysilicon on the layer of isolation material, the first layer of polysilicon having a base region and an emitter region; doping the base region to have the second conductivity type, and the emitter region to have the first conductivity type; and etching the first layer of polysilicon to form the extrinsic base and the extrinsic emitter.
12. The method of
13. The method of
14. The method of
15. The method of
16. The method of
forming a first layer of insulation material on the extrinsic base, the extrinsic emitter, the intrinsic base, and the layer of isolation material; forming a first insulating region and a second insulating region on the first layer of insulation material over the intrinsic base region in the first opening, the first insulating region being adjacent to the extrinsic base, the second insulating region being spaced apart from the first insulating region, and adjacent to the extrinsic emitter, the first and second insulating regions defining a gap therebetween; forming a second layer of insulation material on the first layer of insulation material and the first and second insulating regions to fill up the gap; planarizing to remove the first layer of insulation material from over the extrinsic base and the extrinsic emitter, expose the first and second insulating regions, and define an insulation plug between the first and second insulating regions; and removing portions of the first layer of insulation material and the insulating plug, and the first and second insulating regions to expose a first area and a second area on the instrinsic base, the first and second areas being spaced apart.
17. The method of
etching away a portion of the first and second insulating regions to leave remaining portions; etching away a portion of the first isolation material to expose a portion of the extrinsic base and the extrinsic emitter; removing the remaining portions of the first and second insulating regions; and removing a portion of the first isolation material to expose the first area and the second area on the instrinsic base.
18. The method of
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1. Field of the Invention
The present invention relates to a bipolar transistor and, more particularly, to a polysilicon-edge, base-emitter super self-aligned, low-power, high-frequency bipolar transistor and a method of forming the transistor.
2. Description of the Related Art
A high-frequency bipolar transistor is a device that can turn off and on again fast enough to respond to a high-frequency signal without distorting the wave shape of the signal. A low-power high-frequency bipolar transistor is a device that consumes very little power in responding to the high-frequency signal. Low-power high-frequency bipolar transistors are used in wireless applications, and are finding uses in emerging optical networking applications.
As further shown in
Transistor 100 additionally includes a silicided base contact 122 that is formed on base layer 112, and a silicided emitter contact 124 that is formed on extrinsic emitter 116. In addition, an oxide spacer 126 is formed on base layer 112 between poly ridge 120 and base contact 122.
During fabrication, emitter region 118 is formed from dopants diffusing from poly ridge 120 into base layer 112. As a result, a very small base-to-emitter junction results. A small base-to-emitter junction reduces the base-to-emitter capacitance. Reduced capacitance, in turn, provides low-power high-frequency operation.
One drawback of transistor 100, however, is that transistor 100 has a large base-to-collector capacitance which, in turn, limits the operation of the transistor. Thus, there is a need for a low-power high-frequency bipolar transistor with a reduced base-to-emitter capacitance and base-to-collector capacitance.
The present invention provides a low-power high-frequency bipolar transistor that reduces the base resistance, the base-to-emitter capacitance, and the base-to-collector capacitance. The bipolar transistor of the present invention is formed on a wafer that has a buried layer and a first epitaxial layer of a first conductivity type. The first epitaxial layer is formed over the buried layer, and has a smaller dopant concentration than the buried layer.
The bipolar transistor has an intrinsic base region of a second conductivity type that is formed on the surface of the first epitaxial layer in the opening. The bipolar transistor also has a layer of isolation material that is formed on the surface of the first epitaxial layer to adjoin the intrinsic base region.
In addition, the bipolar transistor has a first spacer that is formed on the layer of isolation material and the intrinsic base region, and a second spacer that is formed on the layer of isolation material and the intrinsic base region. The second spacer is spaced apart from the first spacer. The transistor further includes an extrinsic base that is formed on the layer of isolation material, an intrinsic emitter region that is formed in the intrinsic base region, and an extrinsic emitter that is formed on the layer of isolation material.
The bipolar transistor also includes a first conductive spacer that is formed on the first isolating spacer to contact the extrinsic base and the intrinsic base region, and a second conductive spacer that is formed on the second isolating spacer to contact the extrinsic emitter and the intrinsic emitter region of the intrinsic base region. The second conductive spacer is spaced apart from the first conductive spacer.
The present invention also includes a method for forming a low-power high-frequency bipolar transistor. The bipolar transistor is formed on a wafer that has a buried layer and a first epitaxial layer of a first conductivity type. The first epitaxial layer is formed over the buried layer and has a smaller dopant concentration than the buried layer.
The bipolar transistor additionally has an intrinsic base region of a second conductivity type that is formed on only a portion of the first epitaxial layer, and a layer of isolation material that contacts the first epitaxial layer and the intrinsic base region. The bipolar transistor further has an extrinsic base that is formed on the layer of isolation material, and an extrinsic emitter spaced apart from the extrinsic base that is formed on the layer of isolation material. The bipolar transistor additionally has a base spacer that is connected to the intrinsic base and the extrinsic base, and an emitter spacer that is connected to the intrinsic base and the extrinsic emitter.
The present invention also includes a method for forming a low-power high-frequency bipolar transistor. The bipolar transistor is formed on a wafer that has a buried layer and a first epitaxial layer of a first conductivity type. The first epitaxial layer is formed over the buried layer and has a smaller dopant concentration than the buried layer.
The method of the present invention begins by forming a layer of isolation material on the first epitaxial layer, and forming an extrinsic base and an extrinsic emitter on the layer of isolation material. The extrinsic base, which is spaced apart from the extrinsic emitter, has a second conductivity type while the extrinsic emitter has the first conductivity type.
The method also includes the step of etching the layer of isolation material to form a first opening in the layer of isolation material. The first opening is between the extrinsic base and the extrinsic emitter, and exposes a surface of the first epitaxial layer. The method further includes the step of forming an intrinsic base region on the first epitaxial layer in the first opening.
The method additionally includes the step of forming a first insulating spacer, a second insulating spacer, and an insulating plug on the intrinsic base region in the first opening. The first insulating spacer contacts the extrinsic base, the second insulating spacer is spaced apart from the first insulating spacer and contacts the extrinsic emitter. The insulating plug is spaced apart from the first and second insulating spacers, and formed between the first and second insulating spacers.
Further, the method includes the step of forming a base spacer that contacts the extrinsic base and the intrinsic base between the first insulating spacer and the insulating plug, and an emitter spacer that contacts the extrinsic emitter and the intrinsic base between the second insulating spacer and the insulating plug.
A better understanding of the features and advantages of the present invention will be obtained by reference to the following detailed description and accompanying drawings that set forth an illustrative embodiment in which the principles of the invention are utilized.
As further shown in
In addition, transistor 200 includes an n+ intrinsic emitter region 220 that is formed in p- intrinsic base 216, and a layer of isolation material 222 that is formed on n- epitaxial layer 212 to adjoin intrinsic base 216. In addition, an isolation spacer 222S is also formed on isolation layer 222 and intrinsic base 216.
Transistor 200 further includes an extrinsic base 224 that is formed on isolation layer 222, isolation spacer 222S, and an extrinsic emitter 226 that is spaced-apart from base 224 and formed on isolation layer 222. Transistor 200 additionally has a base spacer 230 that is connected to intrinsic base 216 and extrinsic base 224, and a spaced-apart emitter spacer 232 that is connected to intrinsic emitter region 220 and extrinsic emitter 226.
As described in greater detail below, the method of the present invention forms spacers 230 and 232 in a self-aligned process that produces sublithographic feature sizes. This allows emitter region 220 to be very small which, in turn, reduces the base-to-emitter capacitance. Further, the close spacing between the base and emitter spacers 230 and 232 reduces the base resistance. As further described in greater detail below, the method of the present invention also utilizes isolation spacers 222S to position emitter region 220 away from the junction between intrinsic base 216 and isolation layer 222.
Wafer 310 further has a deep trench isolation region 322 that isolates epitaxial layer 320 from laterally adjacent regions. A shallow trench isolation region 324 is also formed in epitaxial layer 320. The shallow trench isolation region 324 separates a collector surface area 326 from a base/emitter surface area 328 of the to-be-formed bipolar transistor.
In addition, wafer 310 can optionally include an n+ diffused contact region 330 that extends down from collector surface area 326 in epitaxial layer 320 to contact n+ buried layer 316. Contact region 330 is utilized to reduce the series resistance to buried layer 316. N+ buried layer 316, n- epitaxial layer 320, and optional n+ diffused contact region 330 define the collector of the to-be-formed bipolar transistor.
As shown in
Mask 344 is patterned to expose an extrinsic emitter region of poly layer 342, and protect an extrinsic base region of poly layer 342. Once mask 344 has been patterned, the exposed regions of poly layer 342 are implanted with a dopant, such as phosphorous or arsenic, to dope the extrinsic emitter region of poly layer 342. For example, phosphorous can be implanted into poly layer 342 at a dose of 1.0×1016 atoms/cm3 at an implant energy of 30 KeV. Mask 344 is then stripped.
Following this, a second poly-doping mask (not shown) is formed and patterned on poly layer 342. The second poly-doping mask is patterned to protect the extrinsic emitter region of poly layer 342, and expose the extrinsic base region of poly layer 342. Once the second poly-doping mask has been patterned, the exposed regions of poly layer 342 are implanted with boron to dope the extrinsic base region of poly layer 342. For example, boron can be implanted at a dose of 1.0×1016 atoms/cm3 at an implant energy of 15 KeV. The second poly-doping mask is then stripped.
Next, as shown in
Following this, as shown in
Once mask 356 has been patterned, the exposed region of nitride layer 354 and the underlying oxide layer 340 are dry etched and removed. The etch forms an opening 360 that exposes a surface region 362 of n- epitaxial layer 320. Opening 360 can be, for example, approximately 0.3 um square. The etch also removes nitride layer 354 from a portion of the top surface of base 350 and all of the top surface of extrinsic emitter 352. Mask 356 is then stripped.
As shown in
Alternately, rather than forming intrinsic base 364 by growing a p- epitaxial layer, intrinsic base 364 can be formed by implanting n- epitaxial layer 320 with boron. Thus, in accordance with the present invention, the size of opening 360 defines the size of intrinsic base 364. By forming intrinsic base 364 to have a small size, the base-to-collector capacitance is reduced.
After p- intrinsic base 364 has been formed, nitride layer 354 is wet (isotropically) etched to expose the side walls of extrinsic base 350 and extrinsic emitter 352. In addition to removing nitride layer 354 from the side walls of extrinsic base 350 and extrinsic emitter 352, the etch also removes nitride layer 354 from the top surface of extrinsic base 350 and collector surface area 326. Further, the etch removes the exposed regions of nitride layer 346 from extrinsic base 350, and all of nitride layer 346 from extrinsic base 350. The etch leaves a portion of nitride layer 346 on the surface of extrinsic base 350.
Following this, as shown in
The layer of silicon nitride is then anisotropically etched to form nitride side wall spacers 370 and a nitride stringer 370A. (The thickness of the silicon nitride layer defines the width of spacers 370 which, in turn, define the width of the to-be-formed emitter.) Next, a layer of plug oxide 372 approximately 1500Å thick is formed on seal oxide layer 366, nitride side wall spacers 370, and nitride stringer 370A.
Plug oxide 372 can be implemented, for example, with HDP or TEOS (depo/etch/depo/etch). Filling the gap between spacers 370 over intrinsic base 364 with plug oxide layer 372 is critical. The thickness of plug oxide layer 372 defines the amount of to-be-performed planarizing that must be done.
As shown in
Following this, as shown in
As shown in
In accordance with the present invention, oxide spacers 366 on the side walls of base 350 and emitter 352 are utilized to position the to-be-formed intrinsic emitter region away from the junction between oxide layer 340 and base region 364. When base region 364 is formed by epitaxial growth, the quality of the epitaxial layer that adjoins oxide layer 340 is typically poor. By positioning the to-be-formed intrinsic emitter region away from the base-to-oxide junction, the influence of the poor quality material is reduced.
Following this, an undoped layer of poly is deposited on oxide layer 340, extrinsic base 350, extrinsic emitter 352, oxide (side wall) layer 366, and oxide plug 376. The undoped layer of poly is then anisotropically etched to form a base poly spacer 380 that is connected to extrinsic base 350 and intrinsic base 364, and an emitter poly spacer 382 that is connected to extrinsic emitter 352 and intrinsic base 364. Thus, in accordance with the present invention, base and emitter spacers 380 and 382 are self-aligned and formed to have sublithographic feature sizes.
Following the formation of base and emitter spacers 380 and 382, wafer 310 is subject to rapid thermal annealing (RTA). During the RTA process, dopants from extrinsic base 350 diffuse into base poly spacer 380 and into p- intrinsic base 364 to form a contact region in layer 364. At the same time, dopants from extrinsic emitter 352 diffuse into emitter poly spacer 382 and into p- intrinsic base 364 to form an n+ intrinsic emitter region 384 in intrinsic base 364. (Although very little diffusion takes place in single-crystal silicon during an RTA process, significant diffusion takes place in polysilicon.)
As shown in
Thus, a method for forming a bipolar transistor in accordance with the present invention has been described. The present method forms a small base region, an extrinsic base and emitter that are formed over an oxide, and small, self-aligned base and emitter contacts.
It should be understood that various alternatives to the method of the invention described herein may be employed in practicing the invention. For example, although the method is described with respect to npn transistors, the method applies equally well to pnp transistors where the conductivity types are reversed.
In addition, the present method can be incorporated into a BiCMOS process. Thus, it is intended that the following claims define the scope of the invention and that methods and structures within the scope of these claims and their equivalents be covered thereby.
Sadovnikov, Alexei, Darwish, Mohamed N., Razouk, Reda
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