A method and structure for an integrated circuit chip includes storage devices, isolation regions adjacent the storage devices and surface straps connected to the storage devices, wherein the isolation regions have a border coincident with the surface straps.
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1. An integrated circuit chip comprising:
storage devices; isolation regions adjacent said storage devices; and surface straps connected to said storage devices, wherein said isolation regions have an offset step-shape, when viewed from a top-view of said integrated circuit chip, and wherein said step-shape increases a contact area between said surface straps and said storage devices. 9. A dynamic random access memory array comprising:
storage devices; isolation regions adjacent said storage devices; and surface straps connected to said storage devices, wherein said isolation regions have an offset step-shape, when viewed from a top-view of said integrated circuit chip, and wherein said step-shape increases a contact area between said surface straps ad said storage devices. 2. The integrated circuit chip in
3. The integrated circuit chip in
4. The integrated circuit chip in
5. The integrated circuit chip in
6. The integrated circuit chip in
7. The integrated circuit chip in
8. The integrated circuit chip in
10. The dynamic random access memory array in
11. The dynamic random access memory array in
12. The dynamic random access memory array in
13. The dynamic random access memory array in
14. The dynamic random access memory array in
15. The dynamic random access memory array in
16. The dynamic random access memory array in
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1. Field of the Invention
The present invention generally relates to integrated circuit manufacturing techniques and more particularly to an improved method and structure to improve the conductive strap electrical connection between a storage device and a pass gate device.
2. Description of the Related Art
Integrated circuit devices such as dynamic random access memories (DRAM) are being continually reduced in size to decrease manufacturing costs and to increase speed. However, as the devices are scaled (e.g., reduced in size), the manufacturing tolerances including size control and positional overlay must be reduced. Therefore, as integrated circuits are scaled, defects resulting from improperly shaped or positioned items often result in circuits which do not perform as intended, reducing manufacturing yield.
In order to avoid such defects, open-bitline or hierarchical architectures are used to help chip area scaling. An open bitline cell may require a bitline that has a direction off-orthogonal to the wordline direction. A discontinuity of the array is required to change the direction of an off-orthogonal bitline. Such a discontinuity of the array will inflict an undesirable area penalty in the chip.
Other similar scaling processes may place the buried strap in direct proximity to the array device channel. If the buried strap is in direct proximity to the device channel, the buried strap outdiffusion region will interact with the array device source drain diffusion, and impact device performance such as off-current and threshold voltage.
Therefore, there is a need to reduce the size of integrated circuit devices and allow more devices to be placed on a chip, without comprising the functionality of the devices.
It is, therefore, an object of the present invention to provide a structure and method for an integrated circuit chip that includes storage devices, isolation regions adjacent the storage devices and surface straps connected to the storage devices, wherein the isolation regions have a border coincident with a border of the surface straps.
The isolation regions have a step-shape for accommodating the surface straps and have a comer which matches a comer of the surface straps. Thus, the isolation regions are free from interfering with a connection between the surface straps and the storage devices.
The storage devices and the isolation regions are formed on a substrate and the storage devices and the isolation regions define active areas in the substrate. The integrated circuit chip includes bitline contacts in the active areas. The integrated circuit chip includes serpentine gate conductors positioned between the surface straps and the storage devices. The storage devices can be deep trench storage devices and the surface strap connects the deep trench storage devices to transistors.
An inventive method for forming an integrated circuit chip includes forming storage devices, forming isolation regions adjacent the storage devices and forming surface straps connected to the storage devices, wherein the isolation regions are formed to have a border coincident with a border of the surface straps. The isolation regions are formed to have a step-shape for accommodating the surface straps and to have a comer which matches a comer of the surface straps. The isolation regions are formed to be free from interfering with a connection between the surface straps and the storage devices.
The invention increases the overlap area between the surface strap and the deep trench storage device which provides greater reliability of the connection, reduces the number of defects and increases manufacturing yields.
The foregoing and other objects, aspects and advantages will be better understood from the following detailed description of preferred embodiments of the invention with reference to the drawings, in which:
Referring now to the drawings, and more particularly to
Serpentine pattern gate conductors or wordlines (GC/WL) 12, represented by the dotted line in
Transistors 18 are formed in the silicon islands 17. Each transistor has a channel region which lies under but is insulated from the GC/WL 12, a source region which lies under and is connected to the surface strap 13 and a drain region which lies under and is connected to the contact 14. Voltage in the GC/WL 12 selectively connects the deep trench 10 to the contact 14 by making the transistor conductive (allowing a circuit to be formed between the source (surface strap 13) and the drain (contact 14)).
However, the conventional structure illustrated in
Therefore, the inventive structure shown in
Serpentine patterned gate conductors or wordlines (GC/WL) 22, represented by the dotted line in
The structure shown in
A second embodiment of the invention is shown in
One embodiment of the invention is shown in flowchart form in FIG. 6. More specifically, in item 60 the gate oxide and conductors are formed. Then the isolation regions 21 are formed, as shown in item 61. In item 62, gate conductors 22 are formed and, in item 63, surface straps 23 are formed. Finally, bitline contacts 24 are formed in item 64.
Thus, as discussed above, the invention increases the overlap area 25, 50 between the surface strap 23, 40 and the deep trench storage device 20 which provides greater reliability of the connection, reduces the number of defects and increases manufacturing yields.
While the invention has been described in terms of preferred embodiments, those skilled in the art will recognize that the invention can be practiced with modification within the spirit and scope of the appended claims.
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