A semiconductor device having a solid device, and a semiconductor chip bonded to the solid device with a back face thereof being opposed to a front face of the solid device. The semiconductor chip has a back electrode provided on the back face thereof and electrically connected to an electrode provided on a front face thereof through a through-hole. The solid device may be a wiring board or another semiconductor chip. Further another semiconductor chip may be stacked and bonded onto the front face of the semiconductor chip.
|
8. A semiconductor chip, comprising:
a semiconductor substrate having a through-hole formed therein; a front electrode provided on a front face of the semiconductor substrate which is a device formation surface of the semiconductor substrate; and a back electrode provided on a back face of the semiconductor substrate and electrically connected to the front electrode through the through-hole, wherein the front electrode includes an electrode ad which is a portion of an internal interconnection exposed from an insulating film provided on the front face of the semiconductor substrate. 1. A semiconductor chip, comprising:
a semiconductor substrate having a through-hole formed therein; a front electrode provided on a front face of the semiconductor substrate which is a device formation surface of the semiconductor substrate; and a back electrode provided on a back face of the semiconductor substrate and electrically connected to the front electrode via a through-interconnection provided in the through-hole, wherein the front electrode includes a bump projecting from the front face of the semiconductor substrate, and wherein the back electrode and the through-interconnection are composed of the same material as the bump. 5. A semiconductor chip, comprising:
a semiconductor substrate having a through-hole formed therein; a front electrode provided on a front face of the semiconductor substrate which is a device formation surface of the semiconductor substrate; and a back electrode provided on a back face of the semiconductor substrate and electrically connected to the front electrode via a through-interconnection provided in the through-hole, wherein an insulating film is provided on an interior of the through-hole and on portions of the front and back faces of the semiconductor substrate adjacent to the through-hole, and wherein the through-interconnection and the front electrode are provided on the insulating film. 7. A semiconductor chip, comprising:
a semiconductor substrate having a through-hole formed therein; a front electrode provided on a front face of the semiconductor substrate which is a device formation surface of the semiconductor substrate; a back electrode provided on a back face of the semiconductor substrate and electrically connected to the front electrode via a through-interconnection provided in the through-hole; and a back-interconnection provided on the back face of the semiconductor substrate for connection between the through-interconnection and the back electrode, wherein an insulating film is provided on an interior of the through-hole and on the back face of the semiconductor substrate, and wherein the through-interconnection and the back interconnection are provided on the insulating film. 6. A semiconductor chip, comprising:
a semiconductor substrate having a through-hole formed therein; a front electrode provided on a front face of the semiconductor substrate which is a device formation surface of the semiconductor substrate; a back electrode provided on a back face of the semiconductor substrate and electrically connected to the front electrode via a through-interconnection provided in the through-hole; and a front interconnection provided on the front face of the semiconductor substrate for connection between the through-interconnection and the front electrode, wherein an insulating film is provided on an interior of the through-hole and on the front face of the semiconductor substrate, and wherein the through-interconnection and the front interconnection are provided on the insulating film. 4. A semiconductor chip, comprising:
a semiconductor substrate having a through-hole formed therein; a front electrode provided on a front face of the semiconductor substrate which is a device formation surface of the semiconductor substrate; a back electrode provided or a back face of the semiconductor substrate and electrically connected to the front electrode via a through-interconnection provided in the through-hole; and a back interconnection provided on the back face of the semiconductor substrate for connection between the through-interconnection and the back electrode, wherein the front electrode includes a bump protecting from the front face of the semiconductor chip, and wherein the back electrode, the through-interconnect on and the back interconnection are composed of the same material as the bump. 2. A semiconductor chip as set forth in
3. A semiconductor chip as set forth in
9. A semiconductor chip as set forth in
10. A semiconductor chip as set forth in
11. A semiconductor chip as set forth in
|
1. Field of the Invention
The present invention relates to a semiconductor device having a solid device (a semiconductor chip or a wiring board) and a semiconductor chip bonded thereto. The invention further relates to a semiconductor chip to be bonded to a solid device.
2. Description of Related Art
For substantial increase in integration level, attention has been directed to semiconductor devices of chip-on-chip structure in which a plurality of semiconductor chips are arranged in a double-stacked relation.
In this case, electrode projections called "bumps" are provided on a device formation surface (active surface) of the semiconductor chips to be stacked, and the semiconductor chips are stacked in a so-called face-to-face relation.
However, the face-to-face bonding merely realizes a double-stacked structure but not a multi-level structure comprising semiconductor chips stacked at three or more levels, thereby posing limitations to higher density integration.
Where a semiconductor chip is mounted by a so-called face-up bonding method to form the chip-on-chip structure, wire interconnection is required for connecting electrodes on a device formation surface of the semiconductor chip to electrodes on an underlying substrate.
More specifically, the TAB (tape automated bonding) technique is employed, by which the electrodes on the device formation surface of the base semiconductor chip are connected to the electrodes of the underlying substrate (e.g., wiring board) via inner leads and the electrodes on the underlying substrate are connected to a printed board or a ceramic board.
The underlying substrate is indispensable for such wire interconnection, so that the underlying substrate cannot be obviated. Further, higher density integration is impossible with a need for an underlying substrate having a larger plan area.
It is an object of the present invention to provide a semiconductor chip which can be bonded to a solid device (another semiconductor chip or a wiring substrate) with an increased flexibility, thereby realizing higher integration and higher density packaging.
It is another object of the invention to provide a semiconductor device which features an increased flexibility in bonding between a semiconductor chip and a solid device (another semiconductor chip or a wiring board), thereby realizing higher integration and higher density packaging.
A more specific object of the invention is to arrange semiconductor chips in any stacked relation to form a chip-on-chip structure, thereby easily realizing a semiconductor device of multi-level structure comprising semiconductor chips stacked at three or more levels.
Another specific object of the invention is to provide a semiconductor device including a semiconductor chip which can be connected directly to a printed board or the like without the use of an underlying substrate when the semiconductor chip is packaged with its device formation surface facing upward (in a face-up manner).
The semiconductor device according to the present invention comprises a solid device, and a semiconductor chip bonded to the solid device with a back face thereof being opposed to a front face of the solid device, the semiconductor chip having a back electrode provided on the back face thereof and electrically connected to an electrode provided on a front face thereof through a through-hole. The back electrode is bonded, for example, to a connecting portion provided on the front face of the solid device.
The solid device may be another semiconductor chip.
Further another semiconductor chip may be stacked and bonded onto the front face of the semiconductor chip.
The solid device may be a wiring board. In this case, the back electrode is preferably bonded to a lead of the wiring board.
The semiconductor chip according to the present invention comprises a semiconductor substrate formed with a through-hole, a front electrode provided on a front face of the semiconductor substrate as a device formation surface thereof, and a back electrode provided on a back face of the semiconductor substrate and electrically connected to the front electrode through the through-hole.
In accordance with the invention, the back electrode is connected to the front electrode through the through-hole, so that a plurality of semiconductor chips can be connected to each other in any stacked relation such as a face-to-back, face-to-face or back-to-back relation. Thus, a semiconductor device can be realized which has a chip-on-chip structure comprising semiconductor chips stacked at any number of levels, i.e., two levels and three or more levels.
Even where the semiconductor chip is packaged with the device formation surface thereof facing upward (in a face-up manner), electrode connection can be established with the use of the back electrode provided on the back face of the chip, so that the semiconductor chip can be connected directly to a printed board or the like. Further, higher density packaging can be achieved because provision of an underlying substrate is obviated.
The back electrode is preferably connected to the front electrode via a through-interconnection provided in the through-hole.
A front interconnection may be provided on the front face of the semiconductor substrate for connection between the through-interconnection and the front electrode.
A back interconnection may be provided on the back face of the semiconductor substrate for connection between the through-interconnection and the back electrode.
The front electrode may comprise a bump projecting from the front face of the semiconductor substrate. In this case, the back electrode, the through-interconnection, the front interconnection or the back interconnection is preferably composed of the same material as the bump.
Thus, the through-interconnection extending through the through-hole can easily be formed by plating or the like for bump formation. Further, electrical connection between vertically stacked semiconductor chips can be established by bump bonding. In addition, stresses exerted on the semiconductor chips can be absorbed by the bumps.
The bump material generally has properties suitable for the electrodes, i.e., a lower electrical resistance and a higher heat conductivity.
In addition, the back electrode, the through-interconnection, the front interconnection or the back interconnection can be formed simultaneously with the formation of the bump. In this case, the formation of any of these elements can be achieved without employing any other steps for element formation.
Of course, the back electrode, the through-interconnection, the front interconnection or the back interconnection may be formed in a later step after the formation of the bump on a pad electrode.
Where the front interconnection is composed of the same material as the bump, the bump can be used in place of a part of chip internal interconnection, so that further integration can be achieved.
The bump preferably has a greater height than the front interconnection.
The front or back face of the semiconductor substrate or the interior of the through-hole is preferably covered with an insulating film. The back electrode, the through-interconnection, the front electrode, the front interconnection or the back interconnection is preferably provided on the insulating film. Thus, a plurality of electrodes can electrically be isolated from each other. Particularly, where a semiconductor substrate such as of Ge or Si having a high electrical conductivity is employed, the insulation is required.
The front electrode may comprise an electrode pad which is a portion of an internal interconnection exposed from the insulating film provided on the front face of the semiconductor substrate.
The through-hole is preferably provided adjacent the electrode pad.
The bump is preferably provided on the electrode pad as covering the electrode pad.
The through-hole is provided just below the electrode pad. With this arrangement, the amount of the material (bump material) for the through-interconnection disposed in the through-hole can be minimized because the electrode pad and the through-hole are located in the same position as viewed in plan. This allows for resource saving and minimization of electrical resistance.
The foregoing and other objects, features and effects of the present invention will become more apparent from the following description of the preferred embodiments with reference to the attached drawings.
Although description will hereinafter be made on the premise that semiconductor chips are Si-based, any other semiconductors such as GaAs and Ge may be employed.
As shown in
In turn, a photoresist 5 is applied on the front and back faces of the semiconductor substrate 1 except portions thereof which are to be subjected to plating for bump formation (FIG. 2C).
A metal bump material 6 is thickly deposited, by an electroplating method, on portions of the front and back faces of the semiconductor substrate 1 and the interior of the through-hole 7 which are not covered with the photoresist (FIG. 2D). Examples of the metal bump material include oxidation-resistant metals such as Au, Pd, Pt, Ag and Ir (iridium).
Subsequently, the photoresist 5 is removed, and the seed layer 4 and the barrier metal layer on the resulting surface are removed. Then, the resulting substrate is subjected to an annealing process. Thus, a semiconductor chip having the bump 6 formed in the through-hole 7 is provided (FIG. 2E).
Thus, the semiconductor chip is formed with the bump 6 which includes the front electrode 61 provided on the Al electrode 2, the front interconnection 62 provided between the front electrode 61 and the through-interconnection 63 on the front face of the semiconductor substrate 1, and the back electrode 64 and the back interconnection 65 provided on the back face of the semiconductor substrate 1 and connected to the through-interconnection 63. It is noted that the Al electrode 2 and the front electrode 61 constitute a front connecting portion for electrical connection to a solid device from the front face of the semiconductor substrate 1.
With this state, a through-hole 7 is formed in the substrate 1 (see FIG. 3B), and a passivation film 3a is formed on the interior of the through-hole 7 and the back face of the substrate 1 for isolation thereof (see FIG. 3C).
Thereafter, a TiW alloy layer (barrier metal layer not shown) for improving adhesion to the underlying layer and a seed film 4 such as of Au or Pt for power supply for plating are successively formed on the entire surfaces of the resulting substrate 1 by electroless plating or the like. Then, a photoresist 5 is applied on the front and back faces of the semiconductor substrate 1 except portions thereof which are to be subjected to plating for forming a bump around the through-hole 7 (see FIG. 3D).
Then, a metal bump material 6 is thickly deposited, by electroplating or electroless plating, on portions of the front and back faces of the semiconductor substrate 1 and the interior of the through-hole 7 which are not covered with the photoresist. Subsequently, the photoresist 5 is removed, and the seed layer 4 and the barrier metal layer on the resulting surface are removed. Then, the resulting substrate is subjected to an annealing process. Thus, a semiconductor chip having the bump 6 formed in the through-hole 7 is provided (FIG. 3E).
Although the bump 6 thus formed in the aforesaid process has a uniform height, a bump (as indicated by a reference numeral 8 in
The semiconductor chip 11 formed through the production process shown in
Exemplary implementation of the semiconductor chip thus formed with the electrode 6 is shown in FIG. 4.
The semiconductor chips 11a and 11b are connected to each other via the bump electrodes 6 extending through the through-holes 7, thereby realizing a so-called back-to-back bonding structure.
With this structure, semiconductor chips can be stacked at a plurality of levels to a great height for size reduction of the semiconductor device. Theoretically, there is no limit to the number of levels at which the semiconductor chips are stacked.
Although a bump portion formed in the through-hole 7 has a center opening in the aforesaid embodiment, the through-hole 7 may completely be filled with the bump material, as shown in
A plurality of bump electrodes 36, 50 are provided in a device formation region of an Si semiconductor chip 31, and another semiconductor chip 51 is rested on the bump electrodes 50. The bump electrodes 36 are each connected to an interconnection 37 provided on the front face of the chip 31. The interconnection 37 is connected to a metal bump portion 38 provided in a through-hole formed in the chip 31. The metal bump portion 38 is electrically connected to a lead 41 on a substrate 40 on the back side of the chip 31.
An explanation will next be given to a production process for the Si semiconductor chip 31 shown in FIG. 8.
As shown in
Then, a photoresist 35 is applied on the resulting surface except portions thereof which are to be subjected to plating for bump formation (FIG. 9C).
A metal bump material is thickly deposited on the resulting surface by an electroplating method (FIG. 9D). Examples of the metal bump material include Au, Pd, Pt, Ag, Ir (iridium) and Cu. Of the bump thus formed, a bump portion (front electrode) formed on the Al electrode 32 is denoted by a reference numeral 36, and bump portions (back electrode and through-interconnection) formed in and around the through-hole 31a are denoted by a reference numeral 38. A bump portion (front interconnection) for connection between the bump portions 36 and 38 is denoted by a reference numeral 37. Instead of the electroplating method, an electroless plating method may be employed which is a metal film formation method utilizing a reducing action by a chemical reaction.
After the photoresist 35 is removed and the seed film 34 and the barrier metal layer on the resulting surface are removed, the resulting substrate is subjected to an annealing process. Thus, the semiconductor chip having the bump formed in the through-hole is provided (FIG. 9E).
With this state, the interior of the through-hole 31a and the back face of the substrate 31 are entirely covered with a passivation film 33a for isolation thereof. After the passivation film 33a except a bump formation portion thereof is covered with a resist film (not shown), only the bump formation portion of the passivation film is etched. Thereafter, the resist film is removed (see FIG. 11B). Since an oxide film is already formed on the surfaces of the substrate (31), the passivation film 33a may selectively be formed only on the back face of the substrate (31) and the interior of the through-hole 31a.
Then, a metal bump material 38 is thickly deposited in and around the through-hole 31a by electroplating or electroless plating (see FIG. 11C).
A sectional view of the through-hole 31a thus formed in the semiconductor chip is shown in FIG. 12. The bump 38 connected to the interconnection 37 extends through the through-hole 31a. The bump 38 functions as the back electrode.
The semiconductor chip produced by the process shown in
As shown in
As shown in
While the present invention has been described in detail by way of the embodiments thereof, it should be understood that the foregoing disclosure is merely illustrative of the technical principles of the present invention but not limitative of the same. The spirit and scope of the present invention are to be limited only by the appended claims.
This application claims priority benefits under 35 USC Section 119 on the basis of Japanese Patent Applications No. 11-51208 and No. 11-51209 filed to the Japanese Patent Office on Feb. 26, 1999, and Japanese Patent Application No. 11-245855 filed to the Japanese Patent Office on Aug. 31, 1999, respectively, the disclosure thereof being incorporated herein by reference.
Hikita, Junichi, Kumamoto, Nobuhisa, Nishimura, Isamu, Morishima, Yoshiyasu
Patent | Priority | Assignee | Title |
10256117, | May 01 2015 | Sony Corporation | Manufacturing method and wiring substrate with through electrode |
6501663, | Feb 28 2000 | SAMSUNG ELECTRONICS CO , LTD | Three-dimensional interconnect system |
6703689, | Jul 11 2000 | ADVANCED INTERCONNECT SYSTEMS LIMITED | Miniature optical element for wireless bonding in an electronic instrument |
6720661, | Jun 02 2000 | ADVANCED INTERCONNECT SYSTEMS LIMITED | Semiconductor device, method of fabricating the same, stack-type semiconductor device, circuit board and electronic instrument |
6737740, | Feb 08 2001 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | High performance silicon contact for flip chip |
6812137, | Feb 08 2001 | Micron Technology, Inc. | Method of forming coaxial integrated circuitry interconnect lines |
6828656, | Feb 08 2001 | Micron Technology, Inc. | High performance silicon contact for flip chip and a system using same |
6850084, | Aug 31 2000 | Micron Technology, Inc. | Assembly for testing silicon wafers which have a through-via |
6962865, | Jun 02 2000 | ADVANCED INTERCONNECT SYSTEMS LIMITED | Semiconductor device, method of fabricating the same, stack-type semiconductor device, circuit board and electronic instrument |
7074632, | Jul 11 2000 | ADVANCED INTERCONNECT SYSTEMS LIMITED | Miniature optical element for wireless bonding in an electronic instrument |
7102219, | Jun 02 2000 | ADVANCED INTERCONNECT SYSTEMS LIMITED | Semiconductor device, method of fabricating the same, stack-type semiconductor device, circuit board and electronic instrument |
7276738, | Jul 11 2000 | ADVANCED INTERCONNECT SYSTEMS LIMITED | Miniature optical element for wireless bonding in an electronic instrument |
7317256, | Jun 01 2005 | TAHOE RESEARCH, LTD | Electronic packaging including die with through silicon via |
7535093, | Mar 08 2002 | Invensas Corporation | Method and apparatus for packaging circuit devices |
7544973, | Jul 11 2000 | ADVANCED INTERCONNECT SYSTEMS LIMITED | Miniature optical element for wireless bonding in an electronic instrument |
7867874, | Mar 08 2002 | Invensas Corporation | Method and apparatus for packaging circuit devices |
7879633, | Jul 11 2000 | ADVANCED INTERCONNECT SYSTEMS LIMITED | Miniature optical element for wireless bonding in an electronic instrument |
7977208, | Mar 08 2002 | Invensas Corporation | Method and apparatus for packaging circuit devices |
Patent | Priority | Assignee | Title |
5239198, | Sep 06 1989 | Freescale Semiconductor, Inc | Overmolded semiconductor device having solder ball and edge lead connective structure |
6011312, | Jul 30 1996 | Kabushiki Kaisha Toshiba | Flip-chip semiconductor package |
6087719, | Apr 25 1997 | TOSHIBA MEMORY CORPORATION | Chip for multi-chip semiconductor device and method of manufacturing the same |
6107679, | Dec 22 1997 | LAPIS SEMICONDUCTOR CO , LTD | Semiconductor device |
JP4370958, |
Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
Feb 24 2000 | Rohm Co., Ltd. | (assignment on the face of the patent) | / | |||
May 16 2000 | NISHIMURA, ISAMU | ROHM CO , LTD | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 010866 | /0301 | |
May 25 2000 | KUMAMOTO, NOBUHISA | ROHM CO , LTD | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 010866 | /0301 | |
May 25 2000 | MORISHIMA, YOSHIYASU | ROHM CO , LTD | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 010866 | /0301 | |
May 30 2000 | HIKITA, JUNICHI | ROHM CO , LTD | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 010866 | /0301 | |
Sep 27 2019 | ROHM CO , LTD | ACHLYS TECHNOLOGIES INC | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 052273 | /0877 |
Date | Maintenance Fee Events |
May 12 2005 | ASPN: Payor Number Assigned. |
Nov 18 2005 | M1551: Payment of Maintenance Fee, 4th Year, Large Entity. |
Nov 12 2009 | M1552: Payment of Maintenance Fee, 8th Year, Large Entity. |
Nov 13 2013 | M1553: Payment of Maintenance Fee, 12th Year, Large Entity. |
Date | Maintenance Schedule |
Jun 11 2005 | 4 years fee payment window open |
Dec 11 2005 | 6 months grace period start (w surcharge) |
Jun 11 2006 | patent expiry (for year 4) |
Jun 11 2008 | 2 years to revive unintentionally abandoned end. (for year 4) |
Jun 11 2009 | 8 years fee payment window open |
Dec 11 2009 | 6 months grace period start (w surcharge) |
Jun 11 2010 | patent expiry (for year 8) |
Jun 11 2012 | 2 years to revive unintentionally abandoned end. (for year 8) |
Jun 11 2013 | 12 years fee payment window open |
Dec 11 2013 | 6 months grace period start (w surcharge) |
Jun 11 2014 | patent expiry (for year 12) |
Jun 11 2016 | 2 years to revive unintentionally abandoned end. (for year 12) |