Device and method for transposing a matrix of video signals, is disclosed, the device including a memory part, a write control circuit for shifting and writing rows of the matrix of video signals on the memory part by any one unit either of a row unit or column unit, and a read control circuit for shifting and reading the matrix of video signals stored in the memory part by one unit different from the unit in the writing either of the row unit or the column unit, with rows of a matrix of video signal received at the next time written on a portion of the memory part emptied due to the shift in the reading.
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1. A video decoder, comprising:
a variable length decoder(VLD) for decoding a received video bit stream in a form of a matrix to provide a matrix of discrete cosine transformation(dct) coefficients and motion vectors; an inverse scanner for inverse scanning the matrix of dct coefficients provided from the VLD; an inverse quantizer for inverse quantizing a signal from the inverse scanner; a transposter for transposing a matrix of signals from the inverse quantizer, the transposer including, a memory part, a mode signal detector for determining a matrix form of a signal from the inverse quantizer and providing a relevant mode signal, a write control circuit for writing the signals from the inverse quantizer on the memory part by any one unit either of a row unit or a column unit while shifting rows of the signals by the any one unit in sequence appropriately in response to the mode signal, a read control circuit for reading a matrix of signals written on the memory part by one unit different from the one unit in the writing either of the row unit or the column unit while shifting the matrix of signals by the one unit different from the one unit in the writing either of the row unit or the column unit in sequence, wherein the write control circuit writes the next signals from the inverse quantizer on a portion of the memory part emptied due to the shift in the reading by one unit identical to the one unit in the reading while shifting rows of the next signals by the one unit identical to the one unit in the reading in sequence; an inverse discrete cosine transformer(IDCT) for subjecting the transposed signals to inverse cosine transformation to provide spatial pixel values; a frame memory for storing a reference frame; a motion compensator for compensating the reference frame using the motion vector from the VLD; and, an adder for adding the signal from the motion compensator and the signal from the IDCT.
12. A television receiver, comprising:
a tuner for receiving a matrix of compressed video bitstream; a demodulator for demodulating the received matrix of video bitstream; a video decoder for decoding the matrix of video bitstream from the demodulator, the video decoder including, a VLD for decoding the demodulated video bitstream to provide a matrix of dct coefficients and motion vectors, an inverse scanner for subjecting the matrix of dct coefficients from the VLD to inverse scanning, an inverse quantizer for subjecting the inverse scanned matrix of dct coefficients to inverse quantizing, a transposer for transposing the inverse quantized matrix of signals, an IDCT for subjecting the transposed matrix of signals to inverse cosine transformation to converting the transposed matrix of signals into, and providing spatial pixel values, a frame memory for storing a reference frame, a motion compensator for compensating the reference frame stored in the frame memory using the motion vectors from the VLD, and an adder for adding the signals from the motion compensator and the signals from the IDCT; the transposer including, a memory part for storing the matrix of signals, a write control circuit for writing rows of the IDCT signals on the memory part by any one unit either of a row unit or a column unit while shifting the rows of the IDCT signals by the any one unit in sequence, and a read control circuit for shifting and writing the signals stored in the memory part by any one unit opposite to the one unit in the writing either of the row unit and the column unit in sequence, wherein rows of a next matrix of signals from the inverse quantizer are shifted and written on portions of the memory emptied due to the shift in the reading by one unit identical to the unit in the reading either of the row unit or the column unit; a video display processor(VDP) for storing the signals from the video decoder, processing the signals displayable, and providing the signal in sequence; and, a display part for displaying the signals from the VDP on a screen. 2. A video decoder as claimed in
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This application is a divisional of co-pending application Ser. No. 08/994,543, filed on Dec. 19, 1997, the entire contents of which are hereby incorporated by reference and for which priority is claimed under 35 U.S.C. §120; and this application claims priority of Application No. 68798/1996 filed in Korea on Dec. 20, 1996 under 35 U.S.C. §119.
1. Field of the Invention
The present invention relates to a device and a method for transposing a matrix of video signals, which may be applied to a video decoder for decoding a matrix of compressed video bitstream such as signals of an MPEG(Moving Picture Expert Group) format.
2. Discussion of the Related Art
As is well known, recently high definition television(HDTV) broadcasting systems have been developed, some of which are put into pilot operation in some of countries. In the pilot operation of the HDTV broadcasting systems, signals according to the HDTV broadcasting systems are transmitted, which are capable of being processed in an HDTV receiver (hereinafter called as HDTV). In the meantime, there are two classes of signals in the HDTV system of the ATSC (Advanced Television Systems Committee) of the U.S.A. One class of signal is an HD class signal for producing images of a high definition, and the other class of signal is an SD (Standard Definition) class signal(hereinafter called as SD signal) for producing images of a standard definition. The SD class signal has a data transmission rate lower than the HD class signal. The HD TV is adapted to process the two classes of video data, basically. Therefore, there can be four cases of signal transmission between broadcasting stations and HD TV's; the first case is displaying a HD signal as an HD signal, the second case is displaying an HD signal as an SD signal, the third case is displaying an SD signal as HD class signal, and the fourth is displaying an SD signal as an SD signal. Though the first, third and fourth cases have no particular problems in processing the signals with regard to the system performances, the second case does. That is, the second case has problem in that the images appear broken. Therefore, if an HD signal is to be displayed as an SD class signal, it is necessary to degrade performance of a received HD signal to some extent. For example, an HD signal of 20 MHz MPEG format should be altered to an SD class signal of 6 MHz MPEG format. This degradation of the HD signal performance implies a drop in the resolution. In general, the HD signal performance is degraded by removing a portion of frequency band over a certain frequency from the HD signal. An HD signal of an 8×8 matrix having a portion of frequency band over a certain frequency removed therefrom to suit to the SD class signal is thereby altered into an 8×4 HD signal. This 8×4 HD signal can be displayed as an SD class signal, with a resolution degraded compared to the 8×8 HD signal, but without the problem of broken images. In the meantime, an 8×8 matrix SD signal can be displayed on an HDTV as it is. Because of the aforementioned reason, the HD TV should be adapted to process the 8×8 HD signal as well as the 8×4 HD signal. A general HD TV will be explained with reference to FIGS. 1∼3.
Referring to
Illustrated in
Referring to
Accordingly, the present invention is directed to device and method for transposing a matrix of video signals and a television receiver employing the same that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a method and a device for transposing a matrix of video signals which can reduce a chip area of the inverse discrete cosine transformer and, further, an area of the video decoder.
Another object of the present invention is to provide a method and a device for transposing a matrix of video signals which is operable at fast speed.
Other object of the present invention is to provide a video decoder and a television receiver employing the same method and device.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, there is provided a memory part for writing a matrix of video signals thereon, a write control circuit shift and writes rows of the video signals on the memory part by any one unit either of a row unit or a column unit. The video signals written on the memory are read from the memory by one unit different from the unit in the writing either of the row unit and the column unit by a read control circuit for transposing. Rows of video signals received at the next time are shifted, and written on portions of the memory part emptied in sequence due to the shift in the reading by one unit opposite to the unit in the reading either of the row unit and the column unit in sequence. The memory part may includes either one memory on which the matrix of video signals may be written or two memory of less capacity, resulting to a reduction of an occupied area of the memory part. Because rows of video signals received at the next time is shifted, and written on portions of the memory part emptied in sequence in the reading, a speed of the transposing becomes faster.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention:
In the drawings:
FIGS. 5A∼5H illustrate the steps of a process for transposing a matrix of video signals in accordance with the first preferred embodiment of the present invention;
FIGS. 7A∼7H illustrate the steps of a process for transposing a matrix of video signals in accordance with the second preferred embodiment of the present invention;
Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings.
FIRST EMBODIMENT
First, the write control circuit 200 shifts, and writes all rows of the received matrix of signals on the memory part 100 by any one unit either of a row unit or a column unit to a first direction. The read control circuit shifts, and reads the matrix of signals stored in the memory part 100 by any one unit either of a row unit or a column unit different from the unit in the writing to a second direction. In the meantime, vacant spaces in the memory part 100 caused by the shifting in the reading are filled with an identical matrix of the next video signals received successively, with the video signals shifted by the same unit as the reading to the second direction. In this instance, if the writing is made by a row unit and reading is made by a column unit, the first direction is a top to bottom direction of the memory part 100 and the second direction is a left to right direction of the memory part 100. And, if the writing is made by a column unit and reading is made by a row unit, the first direction is the left to right direction of the memory part 100 and the second direction is the top to bottom direction of the memory part 100. When a sequence of lines connecting the write control circuit 200 and the read control circuit 300 to the memory 100 is changed to an opposite fashion, the first direction is a right to left direction and the second direction is a bottom to top direction.
The matrix of video signals may either be m×m(m=an positive integer) or m×m/2(m=a positive even numeral). In general, a received HD signal and SD signal may be either a matrix of 8×8 signals or a matrix of 8×4 signals. The operation of the transposer shown in
First, referring to
Next, the case when 8 rows of received 8×8 video signals are written on the 8×8 memory 100 by a column unit will be explained. In this case, since what is required is only a simple change of the units in the writing at an initial operation, this operation will be explained without any reference to attached drawings. All the 8 rows in the 8×8 signals are written on the 8×8 memory 100 by a column unit, shifting by a column from the right end column to the left end column in the 8×8 memory 100 in sequence. In this instance, the 8 signals in each of the rows are written from bottom to top of each column of the 8×8 memory 100. The 8×8 video signals written on the 8×8 memory 100 are read by a row unit, shifting by one row, from the bottom end row to the top end row in sequence. In this instance, the 8 signals in each of the rows are read from the right side to the left side. In the meantime, the rows emptied in sequence from the top end of the 8×8 memory are filled with the rows of the 8×8 video signals received at the next time shifted from the top end row to the bottom end row in sequence, with the 8 signals in each of the rows written from the right end to the left end of each emptied row in the 8×8 memory 100.
Though the above explanation is given for the case when the memory 100 is an m×m memory and the received video signal is also m×m as an example, it is applicable to a case when the received video signal is smaller than m×m(for example, m×m/2). In this case, both the write control circuit 200 and the read control circuit 300 are adapted to control only an m×m/2 region of the m×m memory region. In this instance, the rest of the memory is left void. In this first embodiment, the video signals are read or written from the right column to the left column and from the bottom row to the top row. And, the video signals are written or read from the right end to the left end of each row and from the bottom end to the top end of each column. However, this sequence shows an example, and the video signals may be processed in the opposite sequence. That is, the video signals are read or written from the left column to the right column and from the top row to the bottom row. And, the video signals are written or read from the left end to the right end of each row and from the top end to the bottom end of each column.
SECOND EMBODIMENT
A transposing method in accordance with a second embodiment of the present invention will be explained.
First, a case when the rows of the 8×4 signals are written on the memories 500 and 600 by a column unit will be explained with reference to
Next, a case when the received 8×4 video signals are written by a row unit, initially. Since this case represents a case when the unit of the writing is changed from a column unit to row unit, this case will be explained briefly, without reference to any attached drawings.
First, upon reception of 8×4 video signals, the write control circuit 700 classifies the received 8×4 video signal into a first 4×4 video signals of odd numbered columns and a second 4×4 video signals of even numbered columns. Then, the write control circuit 700 writes each of the 4 rows of the first 4×4 video signals and the second 4×4 video signals on the first 4×4 memory 500 and the second 4×4 memory 600 respectively by a row unit shifting from the bottom end row to the top end row in sequence. The four signals in each row are written from the right end to the left end of each row of each of the 4×4 memories 500 and 600. Then, the read control circuit 800 reads the first 4×4 video signals and the second 4×4 video signals on the first 4×4 memory 500 and the second 4×4 memory 600 respectively, shifting from the right end column to the left end column of each of the memories 500 and 600 by a column unit in sequence. The second 4×4 memory 600 and the first 4×4 memory 500 are read alternatively in the order of the second 4×4 memory 600 and the first 4×4 memory 500, with the 4 signals in each column of each of the memories 500 and 600 read from the bottom end to the top end. And, the columns in the first 4×4 memory 500 and the second 4×4 memory 600 emptied from the left end column to the right end column due to the shift of the video signals during the reading are filled with rows of the first 4×4 video signals and the second 4×4 video signals of the received 8×4 video signals, shifted from the top end row signals to the bottom row in sequence. In this instance, the 4 signals in each row of the 4×4 video signals are written from the bottom end to the top end of the emptied columns of each of the memories 500 and 600.
Though the case when two 4×4 memories are used as the m/2×m/2 memories, is taken as an example in the case of reception of m×m/2 video signals in this second embodiment, other sizes of m/2×m/2(m is an even numeral) memories may be used for transposing m×m/2 video signals(m is a positive even numeral) of other size matrices. And, identical to the first embodiment, each of the 4×4 memories may includes any one of multiplexed flipflops, an SRAM or register files. And, as explained in the first embodiment, the video signals may be processed in a sequence opposite to the sequence explained above.
The video bitstream may be an MPEG signal for a HDTV broadcasting. And, as explained, the matrix of video bitstream may be m×m(m is a positive integer) signals, and the memory part may be a memory which can store the m×m signals. Particularly, the m×m signal may be 8×8 signals. Or, the received video bitstream may be m×m/2(m is a positive even numeral), and the memory part may includes two memories each of which can store m/2×m/2 signals. Particularly, the m×m/2 signals may be 8×4 signals, and the m/2×m/2 signals may be 4×4 signals.
As has been explained, because reading of a matrix of video signals and writing of the next matrix of video signals can be carried out on the same time, the device and method for transposing a matrix of video signals of the present invention can make IDCT in a video decoder faster. For example, an IDCT transpose block of 400 M sample/sec can be made available by the method of the present invention, where an IDCT transpose block of 100 M sample/sec can be made available by the background art method. Further, because what is required is only one memory of a 16 bits×64 bits size for realization of such a four time faster transpose block, the size of the memory block can be reduced significantly.
Even though the present invention has been explained taking an HDTV as an example in the aforementioned embodiments, the present invention can be applicable to a DVD and any devices involving the MPEG.
It will be apparent to those skilled in the art that various modifications and variations can be made in the device and method for transposing a matrix of video signals and a HDTV receiver employing the same of the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.
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