A method of constructing a conductive via spacer within a dielectric layer located between a first metal layer and a second metal layer includes the steps of depositing a conductive spacer layer within the opening and over the first metal layer. A portion of the conductive spacer layer is removed to leave a conductive spacer within the opening. The second metal layer is deposited over the spacer to complete the connection between the first and second metal layers. The spacer preferably comprises a material selected from the group comprising refractory metal silicides and nitrides. The spacer is preferably tapered and the via may include a glue layer to improve the adherence of the spacer to the dielectric layer.
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1. A via carried in an opening having a top and a bottom in a dielectric layer of an integrated circuit and located between a first metal conductor defining the bottom of the opening and a second metal conductor at the top of the opening, comprising:
a conductive spacer in contact with both the first and second metal conductors, said conductive spacer having a lateral portion having a thickness formed on an inner wall of the opening and a bottom portion having a thickness in contact with the first metal conductor, wherein the thickness of the bottom portion is less than the thickness of the lateral portion adjacent the bottom portion, and wherein the thickness of the lateral portion of said spacer is greater near the bottom of the opening than near the top of the opening.
6. The via of
13. The via of
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1. Field of the Invention
The present invention is directed generally to a via containing a spacer and a method of making the via, and, more particularly, to a via containing a conductive spacer.
2. Description of the Background
It is well known in the semiconductor art to use interconnect structures, known as vias and contacts, to connect an upper conductor of current, such as metal or polysilicon, through a dielectric layer to a lower conductor of current. A via is an electrical connection between two metal layers, and a contact, in contrast, is an electrical connection between anything other than two metal layers, such as between metal and silicon. Vias and contacts are used extensively in very large scale integrated ("VLSI") circuits, and an average VLSI circuit may contain 16 million vias and contacts.
Vias and contacts are formed by an opening in a dielectric layer and a conductor within the opening. Directional deposition methods, such as evaporation and sputtering, are often used to deposit the conductor within the opening. Such methods, however, often provide poor step coverage and only a thin conductive layer on the vertical wall of the opening. Thin layers are often not sufficient to provide good electrical contact between the upper and lower conductors, and result in a high resistance and a propensity for electromigration failures.
Although non-directional deposition methods, such as chemical vapor deposition, provide good coverage of vertical walls, those methods do not provide satisfactory results with conductors which are preferably used in vias and contacts, such as aluminum.
It is well known that step coverage can be greatly improved in directional deposition methods by tapering the wall of a via or contact, so that the wall is not substantially vertical and the diameter at the top is greater than the diameter at the bottom.
One approach to taper a wall is by sputtering or etching the walls of the opening, as disclosed, for example, in U.S. Pat. NO. 5,269,880, issued to Jolly et al. That approach, however, often requires additional process steps to provide the bottom of the opening with a protective layer prior to sputtering or etching, and then removing the protective layer following sputtering or etching, as disclosed in the Jolly et al patent.
An alternative approach is to taper the walls by providing a spacer within the via or contact, without disturbing the dielectric layer and without the need for a protective layer to protect the bottom of the opening. An example of such a method is disclosed in U.S. Pat. No. 4,489,481, issued to Jones. Spacers are typically used in critical geometries where dimensions, such as the size of the opening, must be precisely controlled.
Dielectric materials have traditionally been used as spacers, as disclosed in the Jones patent. Oxides, for example, have a smooth surface which allows more precise control of their dimensions. Metals, in contrast, have a "grainy" structure which results in a rough surface. The rough surface, in turn, makes it difficult to precisely control the dimensions of a metal structure. As a result, it was believed that metals were not suited for use in critical geometries, such as spacers, and so the use of metal as a spacer has generally been ignored.
In addition, vias and contacts are typically formed in oxide layers, and while oxide spacers adhere very well to the oxide layer, many metals do not, and thus require an intermediate "glue" layer, such as polysilicon, which adheres well to both oxide and the metal.
Spacers made of a dielectric, however, have the undesirable property of being an insulator. As a result, the use of a dielectric spacer narrows the contact area between the conductor in a via or contact and the upper or lower conductor, resulting in increased resistance. Furthermore, when a dielectric spacer is etched, it leaves dielectric material in the bottom of the opening, which further increases the resistance of the via or contact, or alternatively, requires additional process steps to remove the dielectric material.
Those problems are exaggerated as the density of integrated circuits increases and the size of openings decreases. As the diameter of an opening approaches one micron, the aspect ratio approaches 1 to 1, and directional deposition methods, even when used in conjunction with tapered sidewalls or dielectric spacers, do not provide a reliable electric contact. In those situations, to reliably obtain good electrical contact the opening is usually completely filled with a conductor, known as a "plug". Plugs, however, are time consuming to produce, and they require several additional process steps. Furthermore, shadowing effects during the formation of plugs often limit their effectiveness as a good electrical connection. As a result, the use of plugs is not always a desirable option.
U.S. Pat. No. 4,507,853, issued to McDavid, discloses the use of metal spacers in a contact between a metal layer and a silicon substrate. There is no disclosure in the McDavid patent, however, of a method of forming a metal spacer in a via. The method disclosed in the McDavid patent does not address the problems present in forming a metal spacer in a via. For example, one problem with forming a metal spacer in a via, which is not addressed in the McDavid patent, is determining when to stop the etch process used to form a spacer from a metal layer deposited in an opening. In the process disclosed in the McDavid patent, a silicon substrate acts as an etchstop. When forming a metal spacer in a via, however, a process that etches the metal layer used to form the spacer will also etch an underlying metal layer. The etch process, therefore, must be stopped before it reaches the underlying metal layer. In an extreme case, the etch process can destroy the underlying metal layer. In a less extreme case, the surface of the underlying metal layer will be recessed by the etch process, increasing both the effective depth and the aspect ratio of the opening, making it more difficult for a subsequent metal layer to make contact with the underlying metal layer. In contrast, if the etch process is stopped too soon, the removal of the conductive layer will not be effective, and a thin film of conductor will remain where it is not wanted.
Thus, the need exists for via spacer with improved electromigration properties, with improved metal step coverage, and with reduced resistance, thereby allowing the use of smaller vias and more dense semiconductor devices.
The present invention is directed generally to a via spacer and a method of making the same. The via spacer is formed within an opening in a dielectric layer between a first and a second metal layer. The invention includes the step of depositing a spacer layer within the opening of the via so that the spacer layer is in contact with the first metal layer. The invention also includes the step of removing a portion of the spacer layer to leave a spacer within the opening, with a portion of the spacer covering the first metal layer. The second metal layer is deposited over the spacer to complete the connection between the first and second metal layers.
The spacer preferably comprises a material selected from the group comprising refractory metal silicides or their associated nitrides, such as, for example, titanium silicide, titanium nitride, and cobalt silicide. The spacer is preferably tapered and the via may include a glue layer to improve the adherence of the spacer to the dielectric layer.
The invention solves the above-mentioned shortcomings in the prior art by providing a method of forming a conductive spacer, which provides for good step coverage and which does not decrease the contact area of the via.
For the present invention to be clearly understood and readily practiced, the present invention will be described in conjunction with the following figures, wherein:
It is to be understood that the figures have been simplified to illustrate only those aspects of a via which are relevant, and some of the dimensions have been exaggerated to convey a clear understanding of the present invention, while eliminating, for the purpose of clarity, some elements normally found in a via. Those of ordinary skill in the art will recognize that other elements and process steps are required to produce an operational via. However, because such elements and process steps are well known in the art, and because they do not further aid in the understanding of the present invention, a discussion of such elements is not provided herein.
Alternatively, titanium may be sputtered directly onto the dielectric layer 12 and the opening 10. Because sputtered titanium may result in shadowing, a columniator may be utilized to provide a more uniform distribution of the spacer layer 16, in particular with respect to the walls and the bottom of the opening 10.
Another preferred material for the spacer layer 16 is titanium silicide, TiSix, deposited by a CVD process. Titanium silicide CVD produces a conformal layer of titanium silicide, yielding uniform metal layers along the vertical and horizontal surfaces in and around the opening 10. The titanium silicide CVD process uses titanium tetrachloride, TiCl4, in conjunction with silan, DCS, or some other source of silicon in the gas molecule.
The anisotropic etch removes the spacer layer 16 from horizontal surfaces. The etch also removes material more quickly from the top of the dielectric layer 12 than from the bottom of the opening 10, so that when the spacer layer 16 has been removed from the top of the dielectric layer 12, there is still a thin spacer layer 19 remaining on the bottom of the opening 10 and over the first metal layer 14. As a result, the spacer layer 16 can be removed from the dielectric layer 12, and damage to the first metal layer 14 can be avoided, by using the removal of the spacer layer 16 from the dielectric layer 12 as a limiting factor. For example, the time required to etch the spacer layer 16 from the dielectric layer 12 can be calculated, given the material of the spacer layer 16, the thickness of the spacer layer 16, and the etch chemistry used. Alternatively, a spectrum analyzer may be used to sense the presence of the dielectric material, such as silicon dioxide, which is indicative that the spacer layer 16 has been removed from the top of the dielectric layer 12, and the dielectric layer 12 is being etched. Those processes will have a margin of error created by the spacer layer 19 remaining at the bottom of the opening 10 after the spacer layer 16 has been removed from the dielectric layer 12.
Since the spacer layer 19 in the bottom of the opening 10 is a conductor, its presence is not detrimental to obtaining a good electrical contact. In fact, the titanium spacer layer 19 cleans the first metal layer 14 and decreases the contact resistance by consuming silicon dioxide which may be present at the bottom of the opening 10. As a result, it is preferable to have at least a small titanium layer 19 remaining in the bottom of the opening 10.
As seen in
Those with ordinary skill in the art will recognize that many modifications and variations of the present invention may be implemented. The foregoing description and the following claims are intended to cover all such modifications and variations.
Gonzalez, Fernando, Blalock, Guy
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