A method of manufacturing a metal oxide semiconductor field effect transistor (MOSFET). The method forms an insulator layer over a substrate and a doped layer over the insulator layer. Further, the invention patterns a conductor layer over the doped layer. The conductor layer includes gate conductors. The invention implants a second impurity through the conductor layer and into the doped layer. The second impurity is of an opposite type than that of the first type of impurity. Also, the second impurity decreases the effective concentration of the first impurity in the doped layer. The amount of the second type of impurity that penetrates through the conductor layer into the doped layer changes depending upon the length of the gate conductors within the conductor layer.
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13. A method of manufacturing a metal oxide semiconductor field effect transistor (MOSFET), said method comprising:
forming an insulator layer over a substrate; forming a doped layer over said insulator layer, wherein said doped layer includes a first type of impurity; patterning a conductor layer over said doped layer, wherein said conductor layer includes gate conductors; and decreasing an effective concentration of said first type of impurity in said doped layer by implanting a second type of impurity through said conductor layer and into said doped layer, wherein said second type of impurity is of an opposite type than that of said first type of impurity.
1. A method of manufacturing a metal oxide semiconductor field effect transistor (MOSFET), said method comprising:
forming an insulator layer over a substrate; forming a doped layer over said insulator layer, wherein said doped layer includes a first type of impurity; patterning a conductor layer over said doped layer, wherein said conductor layer includes gate conductors; and implanting a second type of impurity through said conductor layer and into said doped layer, wherein said second type of impurity is of an opposite type than that of said first type of impurity and said second type of impurity decreases an effective concentration of said first type of impurity in said doped layer.
7. A method of manufacturing a metal oxide semiconductor field effect transistor (MOSFET), said method comprising:
forming an insulator layer over a substrate; forming a doped layer over said insulator layer, wherein said doped layer includes a first type of impurity; patterning a conductor layer over said doped layer, wherein said conductor layer includes gate conductors; implanting a second type of impurity through said conductor layer and into said doped layer, wherein said second type of impurity is of an opposite type than that of said first type of impurity and said second type of impurity decreases an effective concentration of said first type of impurity in said doped layer; and performing an angled implant of said first type of impurity to create a halo implant in said doped layer beneath said gate conductors.
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1. Field of the Invention
The present invention generally relates to semiconductor devices and more particularly to a method of manufacturing semiconductor device that reduces undesirable short-channel effects.
2. Description of the Related Art
The threshold voltage of a metal oxide semiconductor field effect transistor (MOSFET) decreases as the gate length or channel length decreases for "short" gate lengths. This is commonly known as the "short channel effect". This short channel effect increases the off current of the minimum length MOSFET and is one of the constraining limitations in a MOSFET technology. Therefore, there is a need to reduce the short channel effect. Conventionally, the average well doping is increased as the gate length decreases to counter the short channel effect.
It is common practice to introduce higher well doping near the edge of the gate by an angled implantation after the gate is patterned. This is referred to as a "halo" implant. The halo implant doping is a larger fraction of the well doping for short gate lengths, thus increasing the average well doping for short gate lengths as compared to long gate lengths. A halo implant has limits in its effectiveness due to its limited spatial extent near the edge of the gate (e.g., the halo implant only exists around the edge of the gate conductor, not in the center region below the gate conductor).
The maximum electrically active dopant concentration achievable by halo implantation is limited by the solid solubility of the implanted dopant. Also, the angle at which the halo implant can be implanted is limited by the height and proximity of an adjacent gate structure which could potentially block the angled halo implant.
The invention includes a method of manufacturing a metal oxide semiconductor field effect transistor (MOSFET). The method forms an insulator layer over a substrate and a doped layer over the insulator layer. Further, the invention patterns a conductor layer over the doped layer. The conductor layer includes gate conductors. The invention implants a second impurity through the conductor layer and into the doped layer. The second impurity is of an opposite type than that of the first type of impurity. Also, the second impurity decreases the concentration of the first impurity in the doped layer. The amount of the second type of impurity that penetrates through the conductor layer into the doped layer changes depending upon the length of the gate conductors within the conductor layer.
The second impurity that penetrates through the conductor layer decreases in concentration as the length of the gate conductors decreases. Also, the decrease in the amount of the second impurity increases the concentration of the first impurity that remains in the doped layer. The invention anneals the MOSFET structure after the implanting process. The doped layer is formed by a deposited doped layer and an undoped layer followed by doping implantation.
The foregoing and other objects, aspects and advantages will be better understood from the following detailed description of a preferred embodiment(s) of the invention with reference to the drawings, in which:
As mentioned above, it is advantageous to reduce the short channel effect. By increasing the well doping as the gate length decreases the short channel effect is countered and reduced. The commonly used halo implant has limits in its effectiveness toward increasing well doping due to its limited spatial extent near the edge of the gate.
The invention increases well doping without having to resort to an angled implantation. More specifically, the invention implants a first type of impurity before the gate conductor is formed and then subsequently implants a second type of impurity after the gate conductor is formed. The implantation of the second impurity penetrates through the gate conductor. The implanted second impurity is too deep in the structure to affect the first impurity except in regions where the gate conductor is present. The gate conductor reduces the vertical penetration depth of the second impurity to coincide with the well region. However, near the edge of the gate conductor, where a vertical step exists, the reduction of penetration depth of the second impurity is less than away from the gate edge. This is explained with reference to
More specifically, as shown in
This is also shown in
The effect shown in
As mentioned above, because of the decreased doping effects below the patterned gate layer 20,21, the compensating dopant under the gate material in the well region is lower in concentration for shorter gate length devices than for longer gate length devices. Since the net doping, i. e. the well dopant minus the compensating dopant (of opposite type) is the relevant doping for short channel behavior, the effective well doping increases as gate length decreases, even if the uncompensated well doping is independent of gate length.
The process of forming a device according to the invention is shown in
As shown in
In
In
As mentioned above a halo 8 may also be formed with the invention by way of an angled well-type impurity implant as shown in FIG. 8. Then, well-known processing steps are used to create a sidewall insulator 6 and a source/drain region 7 for a functional MOSFET device, as shown in FIG. 9.
An important advantage of the invention is that the average concentration of the compensating dopant implanted through the gate 5 into the well region 3 is less for a short gate conductor than for a long gate conductor, as explained. For the purpose of this description this is called the "butte effect". Also, for the purpose of this description the "gate length" is the area (or horizontal length) of contact between the gate conductor 5 and the underlying substrate (e.g., the gate oxide 4). Therefore, in
As explained above, the short channel effect (SCE) is well known in MOSFET devices. That is, as the gate length becomes shorter, the threshold voltage decreases. A halo implant is commonly used to reduce the SCE. The halo dopant is implanted locally under the edge of the gate and is the same type as the well dopant in layer 3. It has the effect of increasing the average doping in layer 3 for shorter gate length devices.
The inventive butte effect used with a compensating dopant further increases the average net doping in short gate devices compared to long gate devices. The combination of the halo and butte effect are illustrated in the plot shown in FIG. 10. The butte effect provides a method for reducing the SCE in addition to the use of a halo implant. In addition vertical profiles of the implanted compensating dopant for a short gate 21 and a long gate 20 are compared in the graph shown in FIG. 10. The effect of the halo implant is shown in
The inventive process is shown in flowchart form in FIG. 11. More specifically, item 110 first forms an insulator layer 2 over a substrate 1. Then, in item 112, a doped layer 3 is formed over the insulator layer 2 using a first impurity. Item 114.shows forming the gate oxide 4. In item 116, the invention patterns of the conductor over the doped layer 3 to form gate conductors. In item 118 a second impurity 7 is implanted through the conductor layer and into the doped layer.
Therefore, with the invention, a larger portion of the first impurity remains uncompensated within the well region for short gate lengths thereby providing the necessary increase in well region doping to avoid the short channel effects. The invention increases well doping as gate length decreases in a broader spatial extent than that produced by a halo implant alone because the implantation energy of the second impurity is higher than the halo implant energy. The lateral spread of an implanted impurity naturally increases as the implantation energy increases.
In addition, the invention can be used in conjunction with a halo implant to give an additional performance benefit over and above that produced by an optimized halo implant alone. Two-dimensional process and device simulations have shown an additional performance benefit of 3% when the invention is used in conjunction with an optimized halo implant.
The penetration of an impurity through a gate conductor varies depending upon the length of the gate conductor. Therefore, the invention automatically allows relative increased doping for smaller channel length gate conductors. This is very important because short channel effects increase as the channel lengths decrease. The invention automatically increases the dopant in the well region for those shorter channel lengths which need an increase in doping to fight the increase in short channel effects that will be associated with such smaller channel lengths.
The present invention enables the device designer of any CMOS technology to increment the device performance by a few percent. This performance improvement can be used to gain competitive advantage or to delay the purchase of costly process tools otherwise needed to improve the device designs.
While the invention has been described in terms of preferred embodiments, those skilled in the art will recognize that the invention can be practiced with modification within the spirit and scope of the appended claims.
Rausch, Werner, Young, Ralph W.
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