circuit techniques provide different trip points for a rising-edge and for a falling-edge input to a logic gate. Adjustment of the gate trip point for a rising-edge input may be independently adjusted to that for the falling-edge input, and vice versa. Different circuit topologies are provided for delay chains on integrated circuits. Each implementation allows flexibility in delay elements through metal options to allow modifying delay chain delays with simple metal-only layout changes. delay chains are used in integrated circuits to produce either a constant delay or to track another circuit delay.
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17. An integrated circuit comprising:
first, second, third, and fourth logic gates formed on a substrate of the integrated circuit, wherein the first logic gate is coupled to the second logic gate; a first resistance coupled between the second logic gate and a first conductor, a second resistance coupled between a second conductor the thrid logic gate, a third resistance coupled between the third logic gate and a third conductor, and a fourth resistance coupled between a fourth conductor and the fourth logic gate; and a first metal option between first and second conductors, and a second metal option between third and fourth conductors.
22. A logic circuit comprising:
a logic gate coupled between a first input and an output of the logic circuit; a first plurality of transistors coupled in series between a frist supply and the output, wherein the first plurality of transistors comprises a first transistor coupled to the first input and a second transistor coupled to a second input; a second plurality of transistors coupled in series between a second supply and the output, wherein the second plurality of transistors comprises a third transistor coupled to the first input and a fourth transistor coupled to the second input; and an inverter having an input coupled to the second input and an output coupled to the first input.
1. A logic circuit comprising:
a logic gate coupled between a first input and an output of the logic circuit; a first plurality of transistors coupled in series between a first supply and the output, wherein a first plurality of transistors comprises a first transistor coupled to the first input and a second transistor coupled to a second input; and a second plurality of transistors coupled in series between a second supply and the output, wherein the second plurality of transistors comprises a third transistor coupled to the first input and a fourth coupled to the second input, wherein the logic circuit has a first trip point for a rising edge at the first input and a second trip point for a falling edge at the first input, and the first trip point is above the second trip point.
38. A logic circuit comprising:
a logic gate coupled between a first input and an output of the logic circuit; a first plurality of transistors coupled in series between a first supply and the output, wherein the first plurality of transistors comprises a first transistor coupled to the first input and a second transistor coupled to a second input; a second plurality of transistors coupled in series between a second supply and the output, wherein the second plurality of transistors comprises a third transistor coupled to the first input and a fourth transistor coupled to the second input; an inverter coupled between the second input and a first node; a resistance coupled between the first node and the first input; and a capacitance coupled between the first input and the second supply.
51. A logic circuit comprising:
a logic gate coupled between a first input and an output of the logic ciruit; a first plurality of transistors coupled in series between a first supply and the output, wherein the first plurality of transistors comprises a first transistor coupled to the first input and a second transistor coupled to a second input; a second plurality of transistors coupled in series between a second supply and the output, wherein the second plurality of transistors comprises a third transistor coupled to the first input and a fourth transistor coupled to the second input; and an inverter having an input coupled to the second input and an output coupled to gates of the first transistor and the third transistor, wherein a signal at the first input is delayed and inverted with respect to a signal at the second input.
53. A logic circuit comprising:
a logic gate coupled between a first input and an output of the logic circuit; a first plurality of transistors coupled in series between a first supply and the output, wherein the first plurality of transistors comprises a first transistor coupled to the first input and a second transistor coupled to a second input; a second plurality of transistors coupled in series between a second supply and the output, wherein the second plurality of transistors comprises a third transistor coupled to the first input and a fourth transistor coupled to the second input; and an inverter having an input coupled to the second input and an output coupled to gates of the first transistor and the third transistor, wherein a falling edge at the second input is followed by a rising edge at the first input with a delay between the falling and rising edges.
52. A logic circuit comprising:
a logic gate coupled between a first input and an output of the logic circuit; a first plurality of transistors coupled in series between a first supply and the output, wherein the first plurality of transistors comprises a first transistor coupled to the first input and a second transistor coupled to a second input; a second plurality of transistors coupled in series between a second supply and the output, wherein the second plurality of transistors comprises a third transistor coupled to the first input and a fourth transistor coupled to the second input; and an inverter having an input coupled to the second input and an output coupled to gates of the first transistor and the third transistor, wherein a rising edge at the second input is followed by a falling edge at the first input with a delay between the rising and falling edges.
50. A logic circuit comprising:
a logic gate coupled between a first input and an output of the logic ciruit; a first plurality of transistors coupled in series between a first supply and the output, wherein the first plurality of transistors comprises a first transistor coupled to the first input and a second transistor coupled to a second input; a second plurality of transistors coupled in series between a second supply and the output, wherein the second plurality of transistors comprises a third transistor coupled to the first input and a fourth transistor coupled to the second input; and an inverter having an input coupled to the second input and an output coupled to gates of the first transistor and the third transistor, wherein a rising edge at the second input is followed by a falling edge at the first input with a delay between the rising and falling edges, and the delay is at least about one gate delay.
2. The logic circuit of
5. The logic circuit of
6. The logic circuit of
an inverter coupled between the second input and a first node; a resistance coupled between the first node and the first input; and a capacitance coupled between the first input and the second supply.
9. The logic circuit of
10. The logic circuit of
12. The logic circuit of
13. The logic circuit of
an inverter having an input coupled to the second input and an output coupled to gates of the second transistor and the fourth transistor.
15. The logic circuit of
16. The logic circuit of
18. The integrated circuit of
19. The integrated circuit of
20. The integrated circuit of
23. The integrated circuit of
26. The logic circuit of
27. The logic circuit of
29. The logic of
30. The logic circuit of
31. The logic circuit of caim 29 wherein the delay is from about 0.1 nanoseconds to about 100 nanoseconds.
33. The logic circuit of
35. The logic circuit of
36. The logic circuit of
37. The logic circuit of
40. The logic circuit of
41. The logic circuit of
43. The logic circuit of
45. The logic circuit of
47. The logic circuit of
48. The logic circuit of
49. The logic circuit of
54. The logic circuit of
56. The logic circuit of
58. The logic circuit of
59. The logic circuit of
60. The logic circuit of
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This application claims the benefit of U.S. provisional application 60/118,389, filed Feb. 1, 1999, which is incorporated by references along with all the other references cited in this application.
The present invention relates to the field of integrated circuit and more specifically to trip-point adjustment and delay circuits.
There are many types of integrated circuit including microprocessors, ASICs, memories, gate arrays, and programmable logic. On an integrated circuit, various circuitry is used to implement different functions. For example, for a digital integrated circuit, logic gates are the basic building blocks. Despite the overwhelming success of integrated circuits in the marketplace, there is a constant demand for integrated circuits that have better performance or have greater functionality. One of the ways to meet the demand for integrated circuits with greater performance is to improve the circuitry of the integrated circuit.
A standard CMOS logic gate has a gate trip point that defines the voltage at the gate input at which the output transitions. For a CMOS gate, this trip point is usually near the middle of the voltage range (i.e., VCC/2). By adjusting the ratio of the PMOS pull-up network W/L versus the NMOS pull-down network W/L in the CMOS gate, this trip point can be adjusted to be higher or lower than VCC/2. For a standard CMOS inverter, the gate trip point as adjusted in the above manner is the same for both rising and falling inputs. In some applications, it is desirable to have an inverter or logic gate with a different trip point for a rising-edge input from the trip point for a falling-edge input.
Another type of circuit that is useful in an integrated circuit is a delay circuit. Delay circuits are used in various places in an integrated circuit and for various purposes. Delay circuits can be used in conjunction with the clocking tree to ensure logic signals do not arrive too early at sequential logic, latches, and flip-flops, relative to the latching clock (i.e., prevent hold time violations). Delay circuits can be used in delay-locked loops and phase-locked loops. It is important to have circuits where the delay can be tuned to have the precise delay desired. Also, the delay circuit should have a delay that is relatively constant given variations in the process, temperature, and supply voltage.
Therefore, there is a need for trip point adjustment circuit and delay chain circuit techniques.
An aspect of the invention is a circuit technique that provides for different trip points for a rising-edge and for a falling-edge input to a logic gate. Adjustment of the gate trip point for a rising-edge input may be independently adjusted to that for the falling-edge input, and vice versa. This circuit may be useful in, for example, delay chain circuits and any logic where it is desirable to control independently the rising and falling delays. Another aspect of the invention is to provide different circuit topologies for delay chains on integrated circuits. Each implementation allows flexibility in delay elements through metal options to allow modifying delay chain delays with simple metal-only layout changes. Delay chains are used in integrated circuits to produce either a constant delay (e.g., to meet a minimum timing specification), or to track another circuit delay (e.g., hold time delays that track the clock network path delay).
In an embodiment, the invention is a logic circuit including a logic gate connected between a first input and an output of the logic circuit. A first group of transistors is connected in series between a first supply and the output, where a first transistor of the first plurality is connected to the first input and a second transistor of the first plurality is connected to a second input. A second group of transistors connected in series between a second supply and the output, where a third transistor of the second plurality is connected to the first input and a fourth transistor of the second plurality is connected to the second input.
In another embodiment, the invention is an integrated circuit including a first logic gate, a second logic gate, and first, second, third, fourth, fifth, sixth, seventh, and eighth resistances. A first conductor connects the first logic gate to the first resistance, a second conductor connects the first resistance to the second resistance, a third conductor connects the second resistance to the third resistance, a fourth conductor connects the third resistance to the fourth resistance, a fifth conductor connects the fourth resistance to the fifth resistance, a sixth conductor connects the fifth resistance to the sixth resistance, a seventh conductor connects the sixth resistance to the seventh resistance, and an eighth conductor connects the seventh resistance to the eighth resistance. A ninth conductor connects the second logic gate to the first conductor through a first metal option, second conductor through a second metal option, third conductor through a third metal option, fourth conductor through a fourth metal option, fifth conductor through a fifth metal option, sixth conductor through a sixth metal option, seventh conductor through a seventh metal option, and eighth conductor through an eighth metal option.
In yet another embodiment, the invention is an integrated circuit including first, second, third, and fourth logic gates. A first resistance is between the second logic gate and a first conductor, a second resistance is between a second conductor and the third logic gate, a third resistance is between the third logic gate and a third conductor, and a fourth resistance is between a fourth conductor and the fourth logic gate. A first metal option is between first and second conductors, and a second metal option between third and fourth conductors.
Other objects, features, and advantages of the present invention will become apparent upon consideration of the following detailed description and the accompanying drawings, in which like reference designations represent like features throughout the figures.
The present invention is a circuit that provides for a different trip point for a rising-edge and for a falling-edge input to a CMOS logic gate. Adjustment of the gate trip point for a rising-edge input may be independently adjusted to that for the falling-edge input, and vice versa. This circuit may be useful in, for example, delay chain circuits and any logic where it is desirable to control independently the rising and falling delays. The present invention is applicable to integrated circuit such as microprocessors, ASICs, memories, and programmable logic. Programmable logic integrated circuits are discussed in greater detail in the 1999 edition of The Altera Data Book, which is incorporated by reference.
In addition to standard CMOS inverter INV1, the circuit in
In
In operation, because DINB transitions at or before the transition of DIN, either transistor T1 or T4 will be cutoff when the INV1 input transitions. This serves to disconnect either the pull-up network or pull-down network, respectively. So, for a rising edge signal at DIN, DINB will already be low and transistor T4 will be cutoff. Therefore, the pull-up network will be active while the pull-down network will not be active. The additional pull-up network to INV1 causes the trip point of the inverter to be higher.
Similarly, for a falling-edge signal at DIN, DINB will already be high and transistor T1 will be cutoff. Therefore, the pull-down network will be active while the pull-up network will not be active. The additional pull-down network to INV1 causes the trip point of the inverter to be lower.
In summary, for the configuration shown in
For an alternative of the invention, a rising edge at DIN will result in a lower trip point and a falling edge at DIN will result in a higher trip point. This alternative embodiment may be obtained by placing an inverter between DINB and the gates of transistors T1 and T4.
This invention is useful in any case where a different trip point is desired for rising and falling edges into a logic gate. Examples of two applications are delay chains and circuits where equalized rising and falling edge delays are desired.
For delay chains, resistor/capacitance networks are often used in delay chains to produce a slow transition in a logic stage. For longer delays, a larger resistor or capacitor is required. By using the trip-point adjustment circuit as shown in
Another application is in circuits where equalized rising and falling delays are desirable. Since rising and falling trip points can be independently adjusted, this invention may be used to equalize rising and falling delays through a given logic path by including the trip-point adjustment circuitry in the path. If faster delays are desired, one can choose to use the alternate embodiment described above by placing an inverter between DINB and the gates of transistors T1 and T4.
Another aspect of the invention is to provide different circuit topologies for delay chains on integrated circuits. Each implementation allows flexibility in delay elements through metal options to allow modifying delay chain delays with simple metal-only layout changes. Delay chains are used in integrated circuits to produce either a constant delay (e.g., to meet a minimum timing specification), or to track another circuit delay (e.g., hold time delays that track the clock network path delay).
This invention describes three delay chain topologies. All these chain topologies may be implemented using unsalicided N+ poly over diffusion, but may be used with any type of resistor structure. In a representative process technology, unsalicided polysilicon has a sheet resistance of about 196 ohms per square. Unsalicided N+ polysilicon also has the characteristic of a negative temperature coefficient. This is a benefit in delay element circuits because this causes the resistance of the resistors to decrease as temperature increases. This counteracts the increase in the delay associated with transistors at higher temperatures. Also, with such a polysilicon resistor, when routed over diffusion, a distributed gate capacitance is built in, which gives a fairly constant RC delay.
Topology 1 (shown in
Topology 3 (shown in
To conserve power, the three topologies incorporate an enable input (DEN) to allow the delay chain to be disabled when the delay chain is not in use. When DEN is a logic low, the delay chain will be disabled.
TABLE 1 | ||
Contact Point | Contact Point Impedance | Shorted Option |
0 | 0X | C0 |
1 | 1X | C1 |
2 | 2X | C2 |
3 | 3X | C3 |
4 | 4X | C4 |
5 | 5X | C5 |
6 | 6X | C6 |
7 | 7X | C7 |
8 | 8X | C8 |
The right bank of four resistors 422 are each of a given size X. In the
TABLE 2 | ||||
Contact | Contact Point | All C1 to C5 | All D0 to D4 | All O0 to O4 |
Point | Impedance | Shorted Except | Open Except | Open Except |
0 | 0X | C1 | D0 | O0 |
1 | 1X | C1 | D0 | O1 |
2 | 2X | C1 | D0 | O2 |
3 | 3X | C1 | D0 | O3 |
4 | 4X | C1 | D0 | O4 |
5 | 5X | C2 | D1 | O0 |
6 | 6X | C2 | D1 | O1 |
7 | 7X | C2 | D1 | O2 |
8 | 8X | C2 | D1 | O3 |
9 | 9X | C2 | D1 | O4 |
10 | 10X | C3 | D2 | O0 |
11 | 11X | C2 | D2 | O1 |
TABLE 3 | ||||
Contact | Contact Point | All C1 to C5 | All D0 to D4 | All O0 to O4 |
Point | Impedance | Shorted Except | Open Except | Open Except |
12 | 12X | C3 | D2 | O2 |
13 | 13X | C3 | D2 | O3 |
14 | 14X | C3 | D2 | O4 |
15 | 15X | C4 | D3 | O0 |
16 | 16X | C4 | D3 | O1 |
17 | 17X | C4 | D3 | O2 |
18 | 18X | C4 | D3 | O3 |
19 | 19X | C4 | D3 | O4 |
20 | 20X | C5 | D4 | O0 |
21 | 21X | C5 | D4 | O1 |
22 | 22X | C5 | D4 | O2 |
23 | 23X | C5 | D4 | O3 |
24 | 24X | C5 | D4 | O4 |
This implementation uses a trip-point adjustment circuit 428 to increase its delay. However, this embodiment of invention may be practiced without using the trip-point adjustment circuit. A standard CMOS inverter may be used instead. By using the trip-point adjustment circuit, this allows independent adjustment of the trip points to achieve larger delays for the same resistance network. In the circuit of
The topology in
To allow this tracking, nonminimum channel length drivers X1 and X2 are used to drive the resistor network, which is composed of resistors T1 to T4. Nonminimum channel length transistors will vary more with condition changes than a clock path using minimum channel length devices; resistances for T1 to T5 will vary much less with conditions than the clock path composed of minimum channel length devices. Therefore, balance of nonminimum channel length sizing versus resistor sizing will produce a corresponding delay that will track with the associated clock network. For example, if the minimum drawn channel length permitted by the process is 0.25 microns, then the drawn channel lengths of the inverters X1 and X2 could be 0.45 microns.
To balance out differences in rising and falling delays, a two-stage delay chain is used. This is used because process skew conditions can produce very different delays for either a rising-edge or falling-edge input in a single-stage delay as in topologies 1 and 2. The right bank of resistors (T5 to T8) is added to allow increasing resistor length through M1 options changes only. Resistors T1 to T4 are each 5× larger than T4 to T8. In
Table 4 shows three different options for configuring the
TABLE 4 | ||
Connected Options | Resistance Value | |
Option | (All Others Unconnected) | for Each of Two Stages |
A | OP1, OP2, OP5, OP7, OP6, OP8 | 2X (6225.8 Ohms) |
B | OP3, OP9, OP7, OP10, OP4, OP8 | 2X + Y (6848.4 Ohms) |
C | OP3, OP5, OP11, OP12, OP6, OP4 | 2X + 2Y (7471 Ohms) |
This detailed description of the invention has been presented for the purpose of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form described. Many modifications and variations are possible in light of this detailed description. The embodiments were chosen and described in order to best explain the principles of the invention and its practical applications. Others skilled in the art will recognize that various modifications can be made in order to best utilize and practice the invention for a particular application. The scope of the invention is defined by the following claims.
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