The present invention provides an electrooptical panel and electronic appliances provided with the electrooptical panel, wherein production yield and a pixel aperture ratio are not decreased even when pixels are made fine in the electrooptical panel using an active matrix addressing method by TFT addressing.
The foregoing problems can be solved by putting a plurality of communication lines into electrical contact with the TFT array substrate via contact holes, wherein a plurality of pixel electrodes addressed using a TFT by the data line and scanning line are provided. A lift-up film is formed under the contact holes formed through an interlayer insulation film to put the drain region of the TFT in electrical contact with the pixel electrode.
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6. A projecting apparatus, comprising:
a light source; the electro-optical device according to 1; and a projection optical system.
7. An electro-optical apparatus, comprising:
a plurality of data lines; a plurality of scanning lines intersecting the plurality of data lines; a plurality of switching elements being disposed in correspondence with intersections of the plurality of data lines and the plurality of scanning lines, one of the plurality of switching elements having a semiconductor layer; a plurality of pixel electrodes being disposed in correspondence with the plurality of switching elements; at least one capacitor line extending along one of the plurality of scanning lines, one of the plurality of capacitor lines defining at least one notch which has a rectangular shape; and a contact hole, at least a part of the contact hole surrounded by the at least one notch of the plurality of capacitor lines that isolate to the at least one notch, and being formed for electrically connecting the semiconductor layer of the one of the plurality of switching elements and one of the plurality of pixel electrodes.
1. An electro-optical apparatus, comprising:
a plurality of data lines; a plurality of scanning lines intersecting the plurality of data lines; a plurality of switching elements being disposed in correspondence with intersections of the plurality of data lines and the plurality of scanning lines, one of the plurality of switching elements having a semiconductor layer; a plurality of pixel electrodes being disposed in correspondence with the plurality of switching elements; at least one capacitor line extending along one of the plurality of scanning lines, the at least one capacitor line defining at least one first notch, the scanning lines having at least one second notch opposing the at least one first notch; a contact hole disposed at the at least one first notch and at least one second notch and formed for electrically connecting the semiconductor layer of the one of the plurality of switching elements and one of the plurality of pixel electrodes, the width of the capacitor line being narrower in the notch than the other portion of the capacitor line opposing another capacitor electrode.
2. The electro-optical apparatus according to
3. The electro-optical apparatus according to
4. The electro-optical apparatus according to
5. The electro-optical apparatus according to
8. The electro-optical apparatus according to
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This is a Continuation application Ser. No. 09/691,138 filed Oct. 19, 2000, which in turn is a Continuation of application Ser. No. 09/245,287 filed Feb. 5, 1999 now U.S. Pat. No 6,172,721. The entire disclosure of the prior application(s) is hereby incorporated by reference herein in its
1. Field of Invention
The present invention relates to an active matrix electrooptical panel such as a liquid crystal panel having a thin film transistor (referred to TFT hereinafter) addressing-type panel, and to electronic appliances using the electrooptical panel.
2. Description of Related Art
To obtain a high resolution liquid crystal panel, pixels in the display must be made smaller (i.e., finer) and very precisely. However, narrowing the pixel pitch L as shown in
When increasing the aperture ratio of a pixel, it is important that, not only the wiring width of the data lines 6a and scanning lines 3a is narrowed, but also the TFT 30' as a switching element is made fine. For that purpose, the size of the contact hole 5 between the source region of the semiconductor layer la and data line 6a, and the size of the contact hole 8 between the drain region and pixel electrode 9a of the semiconductor layer 1a should be made fine.
A high quality display image and low power consumption are frequently required in liquid crystal panels. Thus, micro-lenses may be used for enhancing the efficiency of light incident on the liquid crystal panels. In the conventional art shown in
The invention provides an electrooptical panel and electronic appliances that include the electrooptical panel that avoid decreases in process yield and pixel aperture ratio even when pixels are made fine.
The invention provides an electrooptical panel having a plurality of data lines and scanning lines intersecting with the data lines, thin film transistors connected to corresponding data lines and pixel electrodes electrically connected to a corresponding thin film transistor. The thin film transistors each have a semiconductor layer separated from a gate electrode by a gate insulation film. At least one interlayer insulation film is formed over the semiconductor layer and gate electrode, and the drain regions of the thin film transistors are electronically connected to the pixel electrodes via contact holes formed through the interlayer insulation film. The contact holes are disposed in close proximity to at least one of the scanning lines and data lines, and a lift-up film is formed under the contact holes.
In one aspect of the invention, the lift-up film is formed under the contact hole so as to reduce the step height between at least one of the scanning lines and data lines and flattening the surface of the interlayer insulation. Therefore, preventing disclination of the liquid crystal due to step formation is possible. While a resist mask can be formed on the interlayer insulation film for allowing a desired region of the interlayer insulation film to be removed, reflection of light on the film surface can be suppressed to prevent retreat of the resist when the resist mask is exposed during a photolithographic process. Thus, the contact holes are formed with approximately the same size as that of the pattern on the mask. Accordingly, the dimension of the opening for the contact hole is not enlarged thereby increasing production yield with respect to pixel defects. Making the dimension of the contact holes accurately also allows the pixels to be made fine, thus providing a fine, precise and compact electrooptical panel.
In one aspect of the invention, at least one of the scanning line and data line, and the lift-up film have approximately the same film thickness.
The invention also provides an electrooptical panel having a plurality of data lines and scanning lines intersecting with the data lines, thin film transistors connected to corresponding data lines and pixel electrodes electrically connected to a corresponding thin film transistor. The thin film transistors each have a semiconductor layer separated from a gate electrode by a gate insulation film. At least one interlayer insulation film is formed over the semiconductor layer and gate electrode, and the drain regions of the thin film transistors are electrically connected to the pixel electrodes via contact holes formed through the interlayer insulation film. A capacitor line serves as one electrode of a capacitor and is aligned approximately parallel with the scanning lines. The contact holes are disposed between each scanning line and each capacitor line, and a lift-up film is formed under each contact hole.
In one aspect of the invention, the contact holes are provided between the scanning lines and capacitor lines and the lift-up film is formed under the contact hole making it possible to reduce the step height between the scanning line and capacitor line, thereby flattening the surface of the interlayer insulation film. Forming the contact hole between the scanning line and capacitor line allows the contact hole to be provided in the region where light is shielded by fitting the scanning line and capacitor line in the same region as the disclination region formed by the transverse electric field generated between the two adjoining pixel electrodes in the conventional art. Accordingly, disclination of the liquid crystal can be prevented along with suppressing the dimension of the opening of the contact hole from being broadened when the resist mask is exposed in the photolithographic process.
In one aspect of the invention, the scanning lines and capacitor lines are simultaneously formed using the same material, the gate insulation film and the dielectric film of the capacitor are simultaneously formed using the same material, and the semiconductor layer and the other electrode of the capacitor are simultaneously formed using the same material.
In one aspect of the invention, the scanning line and the capacitor line are nearly leveled with each other to reduce the step height between them. Since the lift-up film can be tailored to match to this step height, the step height between the scanning line, capacitor line and contact hole can be easily adjusted along with leveling their upper surfaces with respect to each other, thus making the contact holes fine and decreasing disclination.
In one aspect of the invention, at least a part of the lift-up film is formed so as to surround the contact hole, and at least one of the scanning lines is formed to be hollow along the lift-up film.
In one aspect of the invention, at least a part of the lift-up film is formed along the contact hole forming region and at least one of the scanning line and capacitor line is aligned along the lift-up film. Therefore, the aperture ratio is not decreased for the pixels even when the scanning line is disposed in close proximity to the capacitor line, thereby enabling the formation of a contact hole with a large opening area between the scanning line and capacitor line.
In one aspect of the invention, the lift-up film is formed so that the film does not overlap with the scanning lines and capacitor lines.
Accordingly, a step owing to overlap of the scanning line or capacitor line and the lift-up film is not generated so that their upper surfaces are more level with respect to each other, thereby further preventing disclination of the liquid crystal from being formed by the step or broadening the opening of the contact hole.
In one aspect of the invention, the lift-up film has the same film thickness as at least one of the scanning line and capacitor line.
In one aspect of the invention, adjusting the film thickness of the lift-up film to be approximately equal to that of at least the scanning line and capacitor line allows the step height between the lift-up film, and at least one of the scanning line and capacitor line, to be smaller.
In one aspect of the invention, the lift-up film is a conductive film in electrical contact with the drain region.
Accordingly, the lift-up film serves as an etching stopper in forming the contact hole provided that the lift-up film is formed on the drain region. On the other hand, when the lift-up film is formed under the drain region, pixel defects can be avoided even if the contact hole has penetrated through the drain region since the lift-up film is in electrical contact with the conductive film
In one aspect of the invention, the lift-up film is a conductive film simultaneously formed on the drain region using the same material as used in the data line.
In one aspect of the invention, the lift-up film can be formed without increasing the processing steps since the lift-up film is simultaneously formed on the drain region using the same material as used in the data line.
In one aspect of the invention, the lift-up film is a conductive film formed under the drain region.
In one aspect of the invention, pixel defects can be avoided even if the contact hole has penetrated through the drain region since the lift-up film is in electrical contact with the conductive film. Accordingly, the semiconductor layer can be made thin to enable a high speed writing, thus providing an electrooptical panel with a high contrast ratio.
The invention also provides electronic appliances provided with an electrooptical panel.
In one aspect of the invention, a bright and high quality image display is made possible by using an electrooptical panel having a wide irradiation area to the opening region by which the luminous energy efficiency is improved.
In one aspect of the invention, the invention provides an electrooptical panel comprising a plurality of data lines, a plurality of scanning lines crossing with the plurality of data lines, a switching element connected to each data line and scanning line, and a plurality of pixel electrode disposed in a matrix while being connected to the plurality of switching elements on the first substrate, the pixel electrodes being connected to a switching element via a contact hole, the contact hole being allowed to open at nearly a center position between the data line for supplying image signals to the pixel electrode and the data line adjoining the foregoing data line. Accordingly, the contact hole being allowed to open on the interlayer insulation film for connecting the TFT drain region as a switching element to the pixel electrode is formed at a nearly center position between the data line for supplying image signals to the corresponding pixel electrode and the data line adjoining to the foregoing data line to prevent the data line and pixel electrode from forming a short circuit between them, thereby not causing any decrease in the production yield and pixel aperture ratio even if the pixels become minute.
In one aspect of the invention, capacitor lines for endowing the respective pixel electrodes with a prescribed capacitance are provided on the first substrate in parallel relation to the scanning lines, wherein the contact hole is allowed to open between the capacitor line and scanning line in adjoining relation with each other.
Accordingly, the TFT as a switching element and the contact hole for putting the pixel electrode in electrical continuity cause disclination of the liquid crystal due to step configuration between them. However, providing the contact hole between the scanning line and capacitor line makes it possible to fit the TFT into the region where disclination of the liquid crystal due to transverse electric field among the pixels is generated The configuration described above allows non-opening regions, forced to be light-shielded to suppress generation of the liquid crystal disclination, to be adjusted to a minimum proportion. Providing the data lines for endowing the pixel electrode with capacitance in order to retain writing charges of the pixels in the disclination generating region allows to provide an electrooptical panel with a high image quality without decreasing the pixel aperture ratio. Since the contact hole is allowed to open by taking advantage of the space between the adjoining capacitor line and scanning line without sandwiching the contact hole between them, the opening region whose width along the data line direction is prescribed by the capacitor line and data line can be broadened within each pixel disposed in a matrix. Accordingly, the luminous energy efficiency is improved as compared with the case when the contact holes are formed at the corner of each pixel.
In one aspect of the invention, least a lift-up film is provided under the switching element and just under the contact hole. Accordingly, a lift-up film is placed under the semiconductor layer of the TFT at a prescribed position for allowing the contact hole, provided for connecting the TFT as a switching element to the pixel electrode, to open, so that pixel defects can be prevented from occurring even when the contact hole opened by the etching process has penetrated through the semiconductor layer. This configuration makes it possible to thin the semiconductor layer, providing an electrooptical panel having a high contrast ratio since a high speed writing characteristics can be obtained.
In one aspect of the invention, the switching element comprises a thin film transistor, the source region of the thin film transistor being in electrical continuity with a data line, the drain region of the thin film transistor being connected to the pixel electrode, and the lift-up film as a conductive film being in electrical continuity with the drain region. Accordingly, the lift-up film is put into electrical continuity with the drain region of the TFT semiconductor region as a switching element. The lift-up film is formed of a conductive film of a poly-silicon film, a high melting point metal film such as a W (tungsten), Ti (titanium), Cr (chromium), Mo (molybdenum) or Ta (tantalum) film, or an alloy film thereof Therefore, any pixel defects are not caused even when the contact hole penetrates through the semiconductor layer in opening it by an etching process, because the lift-up film is put into electrical continuity.
In one aspect of the invention, the lift-up film is provided so that the film is not overlapped with the scanning line and capacitor line. Accordingly, the lift-up film provided under the TFT drain region of the TFT semiconductor layer is placed not to overlap with the scanning line and capacitor line provided on the semiconductor layer via the gate insulation film. This means that the surface of the interlayer insulation film on the drain region of the semiconductor layer can be approximately flattened. A resist mask is formed at the region where the interlayer insulation film is not removed for opening the contact hole at a prescribed region of the interlayer insulation film. However, when the surface of the interlayer insulation film is flattened in exposing the resist mask by the photolithographic process, reflection of light on the film surface can be suppressed to prevent the resist from being retreated, thereby making it possible to form the contact hole with the same dimension as that of the mask. Accordingly, no decrease of the production yield due to pixel defects is caused since the diameter of the opening of the contact. hole is never broadened. Making the contact hole fine also allows the pixel to be fine, thus providing a highly precise and compact electrooptical panel.
In one aspect of the invention, the film thickness of the lift-up film is nearly equal to the film thickness of the scanning line and capacitor line. Accordingly, more flattening of the surface of the, interlayer insulation film on the TFT drain region is made possible by adjusting the film thickness of the lift-up film to nearly equal to the film thickness of the capacitor line and scanning line, further preventing the resist mask from being retreated, making the dimension of the contact hole finer and enabling the pixel to be fine, which is advantageous for making the electrooptical panel precise, fine and compact.
In one aspect of the invention, the opening region has a plane configuration being in a line symmetry relation to the contact hole. Accordingly, the contact hole for putting the TFT drain region into electrical continuity to the pixel region is allowed to open at the position in line symmetry relation to the center line of the opening region. Therefore, the opening region with a line symmetry, disposed in a matrix and situated at near the center within the respective pixel having a square shape, can be broadened, wherein the steps of the pixel electrode around the contact hole are distributed in line symmetry relation to the opening region Accordingly, possibility of orientation faults such as reverse tilt becomes almost equal even when a levorotatory liquid crystal or a dextrorotatory liquid crystal is used. In other word, the case when distinct orientation faults occur when either the levorotatory or the dextorotatory liquid crystal is used can be obviated, being advantageous since either type of the liquid crystal can be equally used. Moreover, luminous energy efficiency can be improved as compared with the case when a circular light irradiation region having no line symmetry is formed in the opening region as a result of forming the contact holes at the comer of each pixel as in the conventional art shown in FIG. 16.
In one aspect of the invention, a micro-lens is provided at a position confronting each pixel electrode so that the center of the lens is situated at the center point of the opening region. Accordingly, since the center point of the circular light irradiation region by the micro-lens is focused on the center point of the opening region of the pixel, the proportion occupied by the light irradiation region to the opening region is increased to improve luminous energy efficiency, thereby enabling to provide a luminous electrooptical panel even when the pixels are made fine.
The foregoing and other objects, features and advantages of the present invention will be apparent from the following more particular description of a preferred embodiment of the invention as illustrated in the accompanying drawings.
The embodiments of the present invention will be described referring to the drawings. The embodiments are explained using a liquid crystal panel as a example of an electrooptical panel.
A first embodiment of the invention is explained referring to FIG. 1 through FIG. 3.
A plurality of pixels formed into a matrix constituting the image display region of the liquid crystal panel comprises more than one TFT 30 for controlling the pixel electrodes 9a as shown in FIG. 1. Data lines 6a supply image signals to the source of the TFTs 30. The image signals to be written in the data lines 6a may be successively supplied in the order of lines S1, S2 through Sn or may be simultaneously supplied to adjoining data lines 6a for each group. A scanning line 3a contacts the gate of each TFT 30, to provide scanning pulse signals on the scanning lines 3a in the order of lines G1, G2 through Gm according to a given timing. The pixel electrodes 9a electrically contacts the drain of a corresponding TFT 30 and image signals transferred from the corresponding data line 6a are stored in a given timing by closing the TFT 30 for a given time interval. The image signals with a desired level are stored in the liquid crystal between the pixel electrode 9a and opposing electrodes (described below) formed on an opposing substrate for a given time interval Change of orientation of the liquid crystal between the pixel electrode 9a and opposing electrodes in response to the voltage level modulates the light transmitted and/or reflected by the liquid crystal panel A capacitor 70 is added in parallel with the liquid crystal capacitor formed between the pixel electrode 9a and the opposing electrode in order to prevent leakage of the retained image signals, thereby further improving the retention characteristic to provide a liquid crystal panel with a high contrast ratio. The capacitor 70 may be formed by providing a capacitor line 3b as a wiring line for forming the capacitor or the capacitor may be formed between an adjacent scanning line 3a.
According to the first embodiment, the plan layout of the pixels constituting the image display region of the liquid crystal panel has a construction as shown in
A contact hole 8 for electrically contacting the drain region of the semiconductor layer a with the pixel electrode 9a is provided between the scanning line 3a and capacitor line 3b. The area where the disclination of the liquid crystal is generated by the step formation of the contact hole 8 is integrated with the same area as the disclination by the horizontal direction electric field that is generated between the adjacent pixel electrodes 9a.
Therefore, a contact hole 8 can be effectively provided in the area where the light had to be shielded conventionally. A conductive lift-up film 13a made of a polysilicon film or a high melting point metal film made of W (tungsten), Ti (titanium), Cr (chromium), Mo (molybdenum) and Ta (tantalum) or an alloy film thereof may be provided as an etching stopper at the portion defined by a bold line in
Forming at least the channel region 1a' of the TFT 30 and junctions between the channel region 1a' and the source-drain region beneath the data line 6a in the liquid crystal panel according to the first embodiment allows the channel region 1a' and junctions between the channel region 1a' and the source-drain region not to be directly irradiated with incident light. A first light shielding film 11a (indicated by hatch lines from the bottom to the top-left in
While the TFT 30 has preferably an LDD structure as described above, an offset structure may be made in which no impurity ions are implanted into the low concentration source region 1b and low concentration drain region 1c, or the TFT may be a self-aligning type TFT in which a high concentration of impurity ions are implanted using the gate electrode formed as a part of the scanning line 3a as a mask followed by forming high concentration source and drain regions.
Two gate electrodes formed as a part of the scanning line 3a, receiving two identical signals and serving as resistors aligned in series, may be provided between the high concentration source region 1d and high concentration drain region 1e in the construction of the TFT 30 shown in
Although the polysilicon layers such as the channel region 1a', low concentration source region 1b and low concentration drain region 1c of the semiconductor layer a usually generate electric current by the photoelectric transfer effect and cause degradation of transistor characteristics, incident light (the light from the top in
A capacitor 70 is provided for each pixel electrode 9a as shown in FIG. 1. This capacitor 70 is, in more detail composed of a first capacitor electrode 1f extending from the high concentration drain region 1e of the semiconductor layer 1a, a dielectric film formed by the same step as forming the thin insulation film 2, the second capacitor electrode formed as a part of a capacitor line 3b formed by the same step as forming the scanning line 3a (gate electrode), and a part of the pixel electrode 9a opposite the capacitor line 3b and separated by the second interlayer insulation film 4 and the third interlayer insulation film 7. Providing this capacitor 70 enables a highly precise display even when the duty ratio is small. The capacitor line 3b is provided on the surface of the TFT array substrate 10 approximately in parallel relation to the scanning line 3a as shown in FIG. 2. Providing the first light shielding film 11a under the first capacitor electrode 1f via the first interlayer insulation film 12 as shown in the present embodiment allows the first interlayer insulation film 12 to serve as a dielectric film to increase capacitance, thereby providing a liquid crystal panel with a high image quality.
The production process of the liquid crystal panel having the construction as hitherto described will be explained hereinafter referring to FIG. 4 through FIG. 7. FIG. 4 through
The production process of the portions including the TFT 30 corresponding to the cross section along A-A' in
As shown in step (a) in
A light-shielding film 11a metal film such Ti (titanium), Cr (chromium), W (tungsten), Ta (tantalum), Mo (molybdenum) and Pb (lead) or a metallic alloy film such as silicide--is deposited by sputtering to a film thickness of 1000 to 5000 Å, preferably 2000 Å, on the whole surface of the TFT array substrate 10 that has been treated as described above. However, deposition of the light-shielding film 11 is not needed when a light having a luminous energy at a level that does not cause cross-talk is used
Then, a mask corresponding to the pattern of the light-shielding film 11a is formed by photolithography on the deposited light-shielding film 11 as shown in step (b). The first light-shielding film 11a is formed by applying an etching treatment to the light-shielding film 11 through the mask The first light-shielding film 11a may be formed as islands or in stripes extending along the scanning lines or data lines. Resistance of the first light-shielding film 11a can be reduced when it is formed into a grid pattern.
In the next step as shown in step (c), a first interlayer insulation film 12 comprising a silicate glass film such as NSG (a silicate glass film not containing boron and phosphorous), PSG (a silicate glass film containing phosphorous), BSG (a silicate glass containing boron) and MPSG (a silicate glass film containing phosphorous and boron), a silicon nitride film, or a silicon oxide film is formed on the first light-shielding film 11a by, for example, a reduced pressure or atmospheric pressure CVD method using TEOS (tetraethyl orthosilicate) gas, TEB (tetraethyl borate) gas, or TMPO (tetramethyl oxyphosphate) gas. The film thickness of this first interlayer insulation film is, for example, 8000 to 15000 Å.
Then, as shown in step (d), a conductive film 13 is deposited by a reduced pressure CVD or sputtering. The conductive film 13 comprises a polysilicon film, a film of a high melting point metal such as W (tungsten), Ti (titanium), Cr (chromium), Mo (molybdenum) and Ta (tantalum), or an alloy film thereof. Film thickness of the conductive film 13 may be adjusted to be the same film thickness as the scanning line and capacitor line to be deposited in the following steps, the advantage of which will be described hereinafter.
Then, as shown in step (e), a photolithographic step and etching step are applied so that a lift-up film 13a is left behind at just under the pixel electrode 9a and semiconductor layer 1a in the following steps. The lift-up film 13a is provided for the purpose of preventing any defects caused by penetration of contact holes, provided for putting the pixel electrode 9a into electrical contact with the drain region of the semiconductor layer 1a, through the semiconductor layer by etching. However, there will be no problem if the lift-up film 13a is provided under the contact hole 8 for putting the pixel electrode into electrical contact with the drain region of the semiconductor layer 1a.
Then, as shown in step (f), an amorphous silicon film is deposited on the lift-up film 13a in a relatively low temperature atmosphere of about 450 to 550 (C, preferably at 500 (C, by a reduced pressure CVD (for example, CVD with a pressure of about 20 to 40 Pa) using monosilan gas or disilan gas with a flow rate of about 400 to 600 cc/min. The polysilicon film 1 is grown in solid phase to a thickness of about 500 to 2000 Å, preferably about 1000 Å, thereafter by applying an annealing treatment in a nitrogen atmosphere at a temperature of about 600 to 700 (C for about 1 to 10 hours, preferably 4 to 6 hours. A small amount of impurity ions of group V elements such as Sb (antimony), As (arsenic) and P (phosphorous) may be doped during the growth step by an ion-implantation method for forming an n-channel type TFT 30. When the TFT 30 is p-channel type, on the other hand, a small amount of the impurity ions of group III elements such as B (boron), Ga (gallium) and In (indium) may be doped by an ion implantation method. The polysilicon film 1 may be directly deposited by the reduced pressure CVD method without forming the amorphous silicon film Otherwise, the polysilicon film 1 may be once turned into an amorphous state by implanting silicon ions into the deposited polysilicon film using the CVD method, followed by recrystallization by an annealing treatment to form the polysilicon film 1. Silicon nuclei may be grown in solid state by an annealing treatment by laser irradiation using, for example, an excimer laser.
A desired pattern of an island-shaped semiconductor layer a is then formed by a photolithographic process or etching process as shown in step (g). Not only the channel region and source-drain region to serve as switching elements, but also a region to serve as one electrode of a capacitor are collectively formed during this step.
As shown in step (h), a heat oxidation film with a relatively thin film thickness of 100 to 500 Å is formed by heat-oxidizing the semiconductor layer 1a at a temperature of about 900 to 1300 (C, preferably at about 1000 (C, followed by depositing a high-temperature oxidized silicon oxide film or a silicon nitride film with a relatively thin film thickness of about 100 to 1000 Å by a reduced pressure CVD method to form a thin insulation film 2 having a multi-layer structure. Consequently, the semiconductor layer 1a' has a thickness of about 200 to 1500 Å, preferably about 350 to 500 Å, while the thin insulation film 2 has a thickness of about 200 to 1500 Å, preferably about 300 to 1000 Å. Shortening the high-temperature oxidation time interval as described above prevents the substrate from being warped especially when a large size substrate of about 8 inches in diameter is used. However, the thin insulation film 2 with a single layer structure may be formed merely by heat-oxidizing the polysilicon film 1, or a silicon nitrate film may be used in order to endow the gate insulation film 2 with high voltage resistance.
As shown in step (i) in
The scanning line 3a may be formed of a high melting point metal film such as W or Mo or a metal silicide film, or a multi-layer structure may be formed by combining these metal films or metal silicide with a polysilicon firm. When the scanning line 3a is disposed as a light shielding. film corresponding to a part or overall region covered with the second light shielding film 22 shown in
When the TFT 30 is constructed as an n-channel type TFT with the LDD structure as shown in step (k), impurity ions 300 of group V elements such as P are doped at a low concentration (for example, P ions with a dosage of 1 to 3 (1013/cm2) using the scanning line 3a as a diffusion mask for forming the low concentration source region 1b and low concentration drain region 1c, thereby turning the semiconductor layer 1a under the scanning line 3a into the channel region 1a'. The semiconductor layer 1a under the capacitor line 3b (the second capacitor electrode) serves as the first capacitor electrode 1f by making use of the thin insulation film 2 as a dielectric substance. P ions may be previously implanted into the portion for forming the first capacitor electrode 1f in order to have a low resistance.
After forming a resist layer 302 on the scanning line 3a using a mask with a wider width than the scanning line 3a in order to deposit the high concentration source region 1d and high concentration drain region 1e as shown in step (l), impurity ions 301 of group V elements such as P are also doped in high concentration (for example, P ions with a dosage of 1 to 3 (1015/cm2). When the TFT 30 serves as a p-channel type, the region of the n-channel type TFT 30 is protected by covering with the resist and steps (k) and (l) are repeated again. The semiconductor layer 1a is doped with group III elements such as B for forming the low concentration source region 1b and low concentration drain region 1c, and high concentration source region 1d and high concentration drain region 1e. The TFT having such LDD structure is advantageous for reducing the short-channel effect. The TFT may be an offset structure TFT without applying a low concentration doping or may be a self-aligning type TFT by an ion implantation of P ions or B ions using the gate electrode as a mask.
Auxiliary addressing circuits having a complementary structure comprising the n-channel type TFT and p-channel type TFT can be formed on the TFT array substrate 10 simultaneously with the steps described above. The present embodiment is advantageous in that the auxiliary addressing circuits such as the data line addressing circuits and scanning line circuits can be formed by the same steps as forming the TFT 30.
The second interlayer insulation film 4 comprising a silicate glass film such as NSG, PSG, BSG and BPSG, a silicon nitride film or a silicon oxide film is formed so as to cover the scanning line 3a and capacitor line 3b as shown in step (m) using, for example, atmospheric pressure or reduced pressure CVD method and TEOS gas. The film thickness of the second interlayer insulation film 4 may be as thick as possible for not endowing the film with a inter-wiring capacity, preferable thickness being from 5,000 through 15,000 Å.
After applying an annealing treatment at about 1,000 (C for 20 minutes for activating the semiconductor layer 1a as shown in step (n), the contact hole 5 for the data line 6a is formed by a dry etching process, such as reactive ion etching or reactive ion-beam etching. It is advantageous that the contact hole 5 is allowed to open by an anisotropic etching process like reactive ion etching or reactive ion-beam etching since the shape of the opening is similar to that of the mask. Forming the opening by a combination of dry etching and wet etching allows the contact hole 5 to have a tapered shape, which is advantageous in that wire breakage during wiring connection can be prevented. Contact holes for putting the scanning line 3a into electrical contact with wiring lines (not shown in the drawing) are allowed to open on the second interlayer insulation film 4 by the same step as forming the contact hole 5.
A metal containing film 6 such as a low-resistance metal film of opaque Al or a metal silicide film is deposited on the second interlayer insulation film 4 as shown in step (o) in
The data line 6a is formed by a photolithography process and an etching process as shown in step (p). Applying dry etching such as reactive etching and reactive ion-beam etching in the etching process is advantageous since overetching is suppressed to allow precise patterning in accordance with the mask dimensions.
The third interlayer insulation film 7 comprising a silicate glass such as NSG, PSG, BSG and BPSG, silicon nitride film or silicon oxide film is deposited as shown in the step (q) so as to cover the data line 6a using an atmospheric pressure or reduced pressure CVD method and TEOS gas. It is recommended that the third interlayer insulation film 7 be relatively thick, preferably about 5,000 to 15,000 Å, so that no capacitance is present between the data line 6a and pixel electrodes 9a to be formed in a post-processing step. Since disclination of the liquid crystal is sometimes generated due to steps on the TFT 30 as a wiring line and switching element, a flat film may be deposited by spin-coating an organic film or SOG (spin-on-glass) instead of, or over, the silicate glass film constituting the third interlayer insulation film 7, or a CMP(Chemical Mechanical Polishing) treatment may be by applied. Such construction allows the disclination generating region of the liquid crystal to be reduced as small as possible, providing a high pixel aperture ratio even when the pixels are made fine.
The contact hole 8 for electrically contacting the pixel electrode 9a with the high concentration drain region 1e is formed by dry etching such as reactive ion etching or reactive ion-beam etching as shown in step (r). Opening the contact hole 8 by anisotropic etching such as reactive ion etching or reactive ion-beam etching is advantageous since the shape of the opening can be adjusted to be approximately the same as that of the mask. However, forming the opening by a combination of dry etching and wet etching is more advantageous for preventing wire breakage during wiring connection since the shape of the contact hole 8 can be tapered. Because not only the high concentration drain region 1e of the semiconductor region but also the lift-up film 13a as a conductive film are placed just under the region where the contact hole 8 is opened, penetration of the contact hole 8 through the semiconductor layer 1a does not cause any defects in the liquid crystal panel. Providing a lift-up film 13a allows the channel region 1a' of the semiconductor layer 1a to be a thin film, making it possible to improve characteristics of the element.
A transparent conductive thin film 9 such as ITO (Indium Tin Oxide) film with a thickness of about 500 to 2,000 Å is deposited on the third interlayer insulation film 7 by a sputtering treatment as shown in step (s), followed by forming the pixel electrode 9a by a photolithographic process or etching process as shown in step (t). When the liquid crystal panel 100 is used as a reflection-type liquid crystal device, the pixel electrode 9a may be formed of an opaque material having a high reflection index, such as Al. However, a flattening treatment such as a CMP treatment should be applied in forming the third interlayer insulation film 7 to provide the pixel electrode 9a with a mirror face.
After coating the surface of the pixel electrode 9a with a polyimide-based orientation film, an orientation film 23 as shown in
A glass substrate is provided for the opposing substrate 20 shown in
An opposing electrode 21 is formed thereafter by depositing the transparent conductive thin film such as ITO at a thickness of about 500 to 2,000 Å over the whole surface of the opposing substrate 20 by a sputtering treatment. After additionally coating the whole surface of the opposing electrode 21 with a coating of a polyimide-based orientation film, the orientation film is formed by applying a rubbing treatment along a prescribed direction so that the film has a prescribed pre-tilt angle.
Finally, the TFT array substrate 10 and opposing substrate 20, on which the foregoing layers are formed, are adhered with each other with a seal member, with which gap materials comprising glass fibers or glass beads having a given particle size (for example 1 to 6 (m) are mixed, so that the orientation film 23 face each other. A liquid crystal prepared by mixing more than one kind of nematic liquid crystal is provided in the space between both substrates by vacuum suction to form a liquid crystal layer having a desired thickness.
The production process for opening the contact hole 8 to be provided at the region between the scanning line 3a and capacitor line 3b will be described hereinafter.
As shown in step (a) in
Then, light is exposed with a stepper apparatus using a photo mask 303 as shown in step (b) in FIG. 7. When the resist 302 is a positive type resist, the portion of the photo mask 303 where there is no light-shielding chromium film 304 (or the portion where the light passes) is removed. The light is not irregularly reflected during exposure since the area where the contact hole 8 is formed is relatively flat. Accordingly, the region on the third interlayer insulation film 7 where there is no light-shielding chromium film 304 on the resist 302 is removed, or a portion of the resist 302 is removed that is the same size as the pattern diameter for forming the contact hole. Therefore, the resist 302 is not over-removed as shown in the conventional example of
Widening of the diameter of the contact hole 8 is suppressed as much as possible by forming the contact hole 8 using an anisotropic process, etching such as reactive etching or reactive ion-beam etching as shown in step (c) in FIG. 7. The diameter of the opening is not widened when a wet etching is used to form the side wall of the contact hole 8 into a tapered shape because the resist 302 is not over removed as in the conventional art, making it possible to open a fine contact hole.
Pixels in the image display region of the TFT array are finally formed by providing the pixel electrode 9a as shown in step (d) in FIG. 7.
The second embodiment of the liquid crystal panel according to the present invention will be described hereinafter referring to FIG. 8 and FIG. 9.
The overall constitution of the liquid crystal panel in the second embodiment is similar to those in the first embodiment shown in FIG. 2 and
Accordingly, there are no projections on the surface of the TFT array substrate 10 when the first light-shielding film 11a is not provided as shown in FIG. 9. Moreover, the need of forming the first interlayer insulation film 12 is excluded when the substrate is thoroughly cleaned, making it possible to eliminate the steps for forming the first light-shielding film 11a and depositing the first interlayer insulation film 12. In other words, it is effective for improving the production yield and saving production cost because production steps from (a) through (c) in
When the third interlayer insulation film 7 itself is formed as a flat structure, or a CMP treatment is applied or a flattened film of an organic film is formed on the third interlayer insulation film as described in the second embodiment, irregular reflection during exposure in the photolithograhy step for forming the contact hole 8 can be prevented, thereby making it possible to provide a fine contact hole 8. The construction as described above makes it unnecessary to allow the film thickness of the lift-up film 13a to be the same as those of the scanning line 3a and capacitor line 3b.
The third embodiment of the liquid crystal panel according to the present invention will be described hereinafter referring to FIG. 10.
The overall construction of the liquid crystal panel in the third embodiment is approximately identical to the first embodiment shown in FIG. 2 and
Narrowing the pixel pitch L along the X-direction makes the distance between the data lines 6a shorter, and the pixel electrodes could possibly form short circuits between the data line 6a and the contact hole 8. The possibility of short circuit is markedly increased when the data line 6a is formed of an Al (aluminum) film, because the third interlayer insulation film 7 can not be formed as a porous structure by a high temperature treatment because of the low melting point of the Al film. Accordingly, the etching rate for forming the contact hole 8 is accelerated. Especially, since the side walls of the contact hole 8 are formed into a tapered shape, the diameter of the opening of the contact hole 8 through the third interlayer insulation film 7 tends to be enlarged. When no lift-up film 13a as an etching stopper is provided as in the conventional art and the contact hole 8 is formed by dry etching, the contact hole 8 possibly penetrates through the insulation film, forcing simultaneous use of a wet etching process thus making it difficult to form an opening with a small diameter.
The graph indicating the relation between the pixel pitch L and percent defective pixels is shown in
When the distance between the contact hole 8 and the data line 6a is extremely short as shown in the third embodiment, the film thickness of the lift-up film 13a may be designed to have approximately the same thickness as that of the data line 6a, or the interlayer insulation film on the data line 6a may form a flat surface with the area where the contact hole 8 is formed. Disclination of the liquid crystal panel can be reduced by the construction as described above since the diameter of the contact hole 8 is suppressed from being enlarged and the step height is lowered.
According to the present embodiment, the contact hole 8 is formed at a position symmetrical with respect to the center line 9c (refer to
According to the present embodiment as hitherto described, the luminous energy efficiency is improved as compared with the conventional example shown in
Since the liquid crystal panel according to the present embodiment includes a TFT 30 as a switching element or a polysilicon (p-Si) type TFT, auxiliary addressing circuits for addressing pixels on the TFT array substrate can be produced by the same production steps as in forming the TFT 30. The structure of a liquid crystal panel 100 having integrated auxiliary addressing circuits will be described herein with reference to FIG. 12 and FIG. 13.
As shown in
The data line addressing circuit 101 and the scanning line addressing circuit 104 are put into electrical contact with the data line 6a and scanning line 3a, respectively, via wiring lines. The data line addressing circuit 101 includes a shift register circuit for successively transferring start signals in response to clock signals, controlling a sampling circuit by the addressing signals successively outputted from the data line addressing circuit 101 and supplying image signals, transformed into a data type that can be instantly displayed, from a display information processing circuit (not shown in the drawing), to the data line 6a via the sampling circuit. The scanning line addressing circuit 104 includes a shift register circuit for successively transferring start signals in response to clock signals, and the data line addressing circuit 101 transfers signal voltages corresponding to the image signals to the data lines 6a in synchronization with sequential transfer of gate voltage pulses to the scanning lines 3a The sampling circuit may be formed within the data line addressing circuit 101 or may be formed in the region of the third light-shielding film 53. Forming the sampling circuit in the region of the third light-shielding film 53 that has not been utilized allows the space to be effectively used, providing a compact and highly functional data line addressing circuit 101.
As shown in
While the liquid crystal layer is composed of a nematic liquid crystal as an example in the liquid crystal panel 100, the orientation film 23, and the polarizing film and polarizing plate as described above are not needed when a polymer dispersion-type liquid crystal in which liquid crystal is dispersed in a polymer as fine droplets is used. This construction allows the liquid crystal panel to be highly luminous or to consume low electricity by enhancing the luminous energy efficiency. The present embodiment is applicable to various kinds of liquid crystals (liquid crystal phases), operation modes, liquid crystal alignments and methods. As hitherto described, the auxiliary addressing circuits for addressing the image display region can be integrated on the TFT array substrate 10 which does not require attaching the auxiliary circuits by packaging tapes and COG, providing a super-compact liquid crystal panel. The number of ICs for addressing the liquid crystal panel can be largely reduced, thus reducing cost
Micro-lenses that are used on some liquid crystal panels can be produced by the method disclosed, for example, in Japanese Unexamined Patent Publication Nd. 6-194502. One example, liquid crystal panel with micro-lenses 200 is shown in
A cover glass 202 is adhered on the whole surface of the micro-lenses 200 with an adhesive 201, a second light-shielding film 22, an opposing electrode 21 and an orientation film 23 being further formed in this order thereon. The light-shielding film 22 forms a matrix along the boundary of the micro-lens 200 so that the center of each pixel opening is overlapped with respective lens centers 200a of each micro-lens 200.
As shown in
The opening region of the pixel electrode 9a especially has a symmetrical shape relative to the center line 9c passing through the nearly central point 9b of the opening region, as shown in
According to the present embodiment, the light incident from the opposing substrate 20 side is condensed on the pixel electrode 9a around the approximate center point 9b of the opening region with the micro-lens 200 (or 200') having a lens center 200a (or 200a) at the position approximately opposite the center point 9b (center of gravity) of the opening region. Therefore, a circular (or approximately circular or ellipsoidal) light irradiation region is formed within the opening region by the light condensed by the micro-lens 200 (or 200'). The contact hole 8 is formed at a position so as to be symmetrical in relation to the central line 9c of the opening region, thereby it is possible to have a wide symmetrical opening region positioned at around the center of each pixel. Since the opening region is symmetrical in relation to the central line 9c passing approximately through the central point 9b, a circular light irradiation region is formed at a symmetrical position in the opening region (or the center of the circle approximately overlaps the center point 9b). Accordingly, the ratio of the light irradiation region relative to the opening region is high, improving the luminous energy efficiency. The light condensation ability of the micro-lens 200 may be sufficient for accommodating the light irradiation region just within the opening region and the light irradiation region is not smaller than required.
Although the present embodiment is constructed so as to address the pixel electrode 9a using a TFT 30, using an active matrix element such as TFD (Thin Film Diode) other than the TFT is possible. The liquid crystal panel can be also constructed as a passive matrix type liquid crystal panel. So long as light is condensed on the pixel electrode with the micro-lens as described above, the structure, in which the lens center is approximately opposite the center point of the opening region improves luminous energy efficiency.
Embodiments of electronic appliances provided with the liquid crystal panel according to the invention will be described hereinafter referring to
The electronic appliance shown in the schematic block diagram of
Examples of the electronic appliance described above will be shown in
The channel region of the TFTs for switching the pixel electrodes can be sufficiently shaded especially in the present embodiment by providing a light-shielding film under the TFT as previously described, even when the reflected light from the projection optical system within the liquid crystal projector based on the projected light from the liquid crystal panel 100, the reflected light from the surface of the TFT array substrate when the projection light goes through, and a part of the projected light (a part of the R and G lights) penetrating through the dichroic prism 1112 after being output from the other liquid crystal panels 100 are incident in as back light from the TFT array substrate side. Accordingly, adhering an AR(Anti Reflection) film for blocking the back light between the TFT array substrate and prism of each liquid crystal panel, or applying an AR coating film treatment on the polarized plate is not required even when a prism suitable for compacting is used for the projection optical system, which is advantageous for compacting and simplifying the construction.
Aligning the direction of distinct vision of the liquid crystal panel constituting the three light valves 100R, 100G and 100B allows occurrence of irregular colors or decrease of contrast to be suppressed. Therefore, only the light valve 100G among the light valves 100R, 100G and 100B should be horizontally rotated in the direction of distinct vision of the liquid crystal when a TN liquid crystal is used as a liquid crystal. However, when the light valve provided with the liquid crystal panel according to the present embodiment is used, the configuration of the opening of the pixels becomes nearly identical to the dextrorotatory or levorotatory liquid crystals irrespective of either type of the TN liquid crystal, thereby enabling to equally recognize the image even when disclination of the liquid crystal is generated. The constitution described above provides a liquid crystal projector that produces high quality images when the lights from the light valves 100G, 100R and 100B are synthesized by the prism, since occurrence of irregular colors or decrease of contrast on the display image is not caused.
A multimedia compatible laptop type personal computer (PC) 1200 as an example electronic appliance shown in
When the addressing circuit 1004 and display information processing circuit 1002 are not mounted on the liquid crystal panel 100 as shown in
Examples of the electronic appliances shown in
As hitherto described, the present embodiment provides a liquid crystal panel that does not result in decrease of production yield and pixel aperture ratio even when the pixels are made fine, and various electronic appliances provided with the same, by using a relatively simple structure.
The liquid crystal panel according to the present invention allows the surface of the interlayer insulation film to be flat because a lift-up film is formed under the contact hole for providing an opening on the interlayer insulation film in order to put the drain region of the TFT as a switching element into electrical contact with the pixel electrode, thereby reducing the step height on the area where contact holes are to be formed. This constitution enables disclination of the liquid crystal to be prevented along with suppressing the size of the opening of the contact hole from being enlarged when the resist is exposed in the photolithographic process.
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