A method of forming fine patterns of semiconductor devices comprises patterning one material layer using at least two sub-photomasks. The material layer is formed on a semiconductor substrate, and the material layer is patterned at least twice using each of the sub-photomasks. The shapes and sizes of the patterns on one sub-photomask are different to those of the other sub-photomask, and the patterns of one sub-photomask may partially overlap those of the other sub-photomask. The profiles of all patterns formed on the one material layer can thereby be optimized.
|
1. A method for forming fine patterns of a semiconductor device, comprising the steps of:
(a) forming a material layer to be patterned on a semiconductor substrate; (b) forming an etch mask layer on the material layer; (c) independently patterning the etch mask layer at least twice by using at least two sub-photomasks, which includes: (c1) forming a first photoresist pattern on the etch mask layer using a first sub-photomask; (c2) first-patterning the etch mask layer using the first photoresist pattern as an etch mask; (c3) removing the first photoresist pattern; (c4) forming a second photoresist pattern on the etch mask layer from which the first photoresist pattern was removed, using the second sub-photomask; (c5) second-patterning the first-patterned etch mask layer using the second photoresist pattern as an etch mask; and (c6) removing the second photoresist pattern, wherein the first sub-photomask has patterns of a first group and the second sub-photomask has patterns of a second group, wherein the shape of the patterns of the first group is different from the shape of the patterns of the second group; and
(d) patterning the material layer using the etch mask layer from step (c) thereby forming a material layer pattern having a plurality of patterns on the semiconductor substrate.
2. The method of
3. The method of
5. The method of
6. The method of
|
1. Field of the Invention
The present invention relates to a method of fabricating semiconductor devices and, more particularly, to a method of forming fine patterns of semiconductor devices.
2. Description of the Related Art
There is currently a great amount of research in methods for forming fine patterns of semiconductor devices and photomasks necessary therefore because semiconductor devices are becoming more highly integrated. Presently, a phase shift mask process is widely used to form fine patterns of semiconductor devices because it is highly effective in forming periodic patterns. However, elaborate techniques are required to form a phase shift mask, and it is expensive to fabricate the phase shift mask, moreover, phase shift mask processes do not effectively form aperiodic patterns. Thus, processes using a phase shift mask are inappropriate for forming fine aperiodic or abnormal patterns at low cost. Since, pattern density increases as integration increases and pattern abnormalities increase as pattern density increases, pattern abnormalities in semiconductor devices increase with the increased integration thereof.
Referring to
Referring to
As described above, light 20 passes through the transparent substrate 22 and through the contact hole patterns 3 of the opaque material pattern 24 when the light 20 radiates the photomask 1. The light which passes through the transparent substrate 22 and the contact hole patterns 3 exposes a predetermined region of the photoresist layer 26 formed on the semiconductor substrate 21. The diffraction or interference effect on the light beams passing through the transparent substrate 22 and contact hole patterns 3 is more severe as the distance d between adjacent holes in the contact hole pattern 3 decreases. The etch mask layer 25 is formed on the interdielectric layer 23 and acts as an antireflection layer, but the diffraction and interference effects cannot be overcome.
Thus, as shown in
In the conventional art, when the sizes or shapes of patterns of the photomask 1 are different, it is difficult to optimize profiles of all patterns formed on the semiconductor substrate. For example, when patterns having various sizes or shapes are mixed in the photomask 1, it is difficult to optimize profiles of all patterns. This is because conditions of the photo process, for example, conditions of exposure and development, must be changed in accordance with the size or the shape of the pattern.
The present invention is directed to overcoming or at least reducing the effects of one or more of the problems set forth above.
In accordance with one aspect of the present invention there is provided a photomask for forming fine patterns capable of optimizing the profiles of all patterns formed in a high pattern density region. More specifically, there is provided a photomask for forming fine patterns by etching one material layer formed on a semiconductor substrate. The photomask for forming fine patterns includes at least two sub-photomasks. Each of the sub-photomasks is composed of one transparent substrate and patterns on one side of the transparent substrate. All of the patterns to be formed can be thought of as an entire set of patterns which are split into subsets of patterns. The union of the subset of patterns is the entire set of patterns. Each sub-photomask is transcribed with a corresponding subset of patterns. The patterns of one sub-photomask correspond to one of the groups obtained by classifying a group of patterns finally formed on the semiconductor substrate. For instance, when the photomask is composed of two sub-photomasks, patterns on a substrate of the first sub-photomask (i.e., patterns of a first group) are patterns obtained by transcribing some of the entire set of patterns. The patterns on a substrate of the second sub-photomask (i.e., patterns of the second group) are patterns obtained by transcribing the entire set of patterns with the exception of the patterns of the first group.
In accordance with another aspect of the present invention, at least one of the patterns on one sub-photomask may overlap with at least one of the patterns on another sub-photomask. The overlapped pattern may correspond to a pattern such as an alignment key, which is difficult to completely pattern with one photo process.
In a further aspect of the present invention, when the sizes of the patterns in the entire set of patterns are the same, the minimum distance between patterns on the substrate of each of the sub-photomasks is wider than the minimum distance among the entire set of patterns. Thus, when the photo process is performed using each of the sub-photomasks, the distance between patterns is increased, so that the interference and/or diffraction effect of light beams can be remarkably suppressed.
In accordance with yet another aspect of the present invention, when there are two different shapes of patterns in the entire set of patterns, patterns of the same shape are transcribed on a substrate of one sub-photomask. For instance, when the entire set of patterns are classified into two kinds of shapes, i.e., rectangular patterns and regular square patterns, the rectangular patterns are transcribed on the substrate of one sub-photomask and regular square patterns are transcribed on the substrate of another sub-photomask. Here, the rectangular pattern may be a pattern for forming an interconnection of a bar type or a pattern for forming an oval contact hole, and the regular square pattern may correspond to a pattern for forming a circular contact hole. Thus, it is easy to optimize the profiles of the regular square patterns and rectangular patterns formed on the semiconductor substrate by changing the process conditions whenever a photo process using each of sub-photomask is performed.
In accordance with another aspect of the present invention there is provided a method of forming fine patterns using the photomask. More specifically, there is provided a method of forming fine patterns capable of optimizing the profiles of all patterns formed on a semiconductor substrate. In this method, one material layer to be patterned such as a dielectric layer or a conductive layer is formed on the semiconductor substrate, and the material layer is patterned using at least two sub-photomasks. Here, the sub-photomasks are the same as those of the sub-photomask for forming fine patterns. As a result, the method of forming fine patterns requires the same number of photo processes as the number of sub-photomasks.
In a further aspect of the present invention, when two sub-photomasks are used (i.e., first and second sub-photomasks) the step of patterning the material layer includes the sub-steps of forming a first photoresist pattern on the material layer using the first sub-photomask; first-patterning the material layer using the first photoresist pattern as an etch mask; removing the first photoresist pattern; forming a second photoresist pattern using the second sub-photomask which is different from the first sub-photomask on the semiconductor substrate where the first photoresist pattern is removed; patterning the first patterned material layer using the second photoresist pattern as an etch mask, thereby forming a plurality of patterns in the material layer.
In accordance with yet another aspect of the present invention, the present invention may further comprise a sub-step of forming an etch mask layer having an etch selectivity with respect to the material layer. At least two of the sub-photomasks are used for patterning the etch mask layer. Also, the material layer is patterned by one etching process using the patterned etch mask layer as an etch mask, thereby forming desired patterns. The etch mask layer is formed of a silicon nitride layer or a silicon oxynitride layer acting as an antireflection layer. When the two sub-photomasks are first and second sub-photomasks, the step of patterning the material layer includes the sub-steps of: forming the first photoresist pattern on the etch mask layer using the first sub-photomask; patterning the etch mask layer using the first photoresist pattern as an etch mask; removing the first photoresist pattern; forming a second photoresist pattern on the semiconductor substrate where the first photoresist pattern is removed; using the second sub-photomask which is different from the first sub-photomask; second-patterning the first-patterned etch mask layer using the second photoresist pattern as an etch mask; removing the second photoresist pattern, and etching the material layer using the second-patterned etch mask layer.
In accordance with still another aspect of the present invention, when the shapes of the patterns of the first sub-photomask are different from that of the second sub-photomask, the photo process using the first sub-photomask is performed under different conditions than that of the photo process using the second sub-photomask, thereby easily optimizing the profiles of all patterns finally formed in the material layer. When all patterns finally formed in the material layer have the same size, the profiles of all patterns formed in the material layer can be optimized by manufacturing first and second sub-photomasks such that a minimum distance of patterns transcribed on the first sub-photomask and a minimum distance of patterns transcribed on the second sub-photomask are wider than the distances of the plurality of patterns. This is because whenever photo processes are performed using each of the sub-photomasks, the minimum distance of the patterns transcribed on the semiconductor substrate is wider than that in the conventional art, so that the interference or diffraction effect of the light beams generated between adjacent patterns is remarkably reduced. Particularly, when an etch mask layer is additionally formed on the material layer, profiles of each of the patterns can be further optimized.
According to the present invention, a plurality of patterns which are formed by using single photo process, are formed by using at least two photo processes, thereby optimizing the profiles of each of the patterns.
The above features and advantages of the present invention will become more apparent upon reference to the following detailed description of specific embodiments and the attached drawings, of which:
Korean application Ser. No. 99-19985 filed Jun. 1, 1999 is hereby incorporated by reference as if fully set forth herein.
Hereinafter, preferred embodiments of the present invention will be described. The preferred embodiments of the present invention are described with respect to a photomask composed of two sub-photomasks (i.e., first and second sub-photomasks) for patterning one material layer. However, it will become readily apparent that the photomask may be composed of three or more sub-photomasks by further dissecting the patterns and repeating the steps used for the exemplary first and second sub-photomask.
Referring to
Meanwhile, adjacent patterns in the low pattern density region 36 are separated by a larger distance than adjacent patterns in the high pattern density region 34. As previously mentioned, the patterns are classified into two groups of patterns, i.e., the first group of patterns 30 and the second group of patterns 32. The first group of patterns 30 include some of the patterns arranged in the high pattern density region 34 and all of the patterns arranged in the low pattern density region 36. The patterns arranged in the low pattern density region 36 may also be the second group of patterns 32. This is because the distance between the patterns arranged in the low pattern density region 36 is larger than those between the patterns arranged in the high pattern density region 34.
Adjacent first group patterns 30 must be separated by a distance longer than the distances dx and dy as shown in FIG. 3. Similarly, adjacent second group patterns 32 must be separated by a distance longer than the distances dx and dy.
As shown in
Meanwhile, an alignment key (not shown in
Referring to
Referring to
Referring to
Referring to
Referring to
Referring to
Also, the second sub-photomask 110 includes the second group of patterns 92 shown in
The method of forming patterns on a semiconductor substrate using the first and the second sub-photomasks 100 and 110 respectively is the same as that described with respect to
According to the present invention, one material layer is patterned using at least is two sub-photomasks having different patterns, to thereby realize patterns having an optimized profile.
It should be understood that the invention is not limited to the illustrated embodiment and many changes and modifications can be made within the scope of the invention by a person skilled in the art.
Thus, a method of forming fine patterns of a semiconductor device has been described according to the present invention. While the invention is susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and described in detail herein. However, it should be understood that the invention is not limited to the particular forms disclosed. Rather, the invention covers all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined in the appended claims.
Patent | Priority | Assignee | Title |
10176289, | Feb 24 2017 | United Microelectronics Corp. | Method for decomposing semiconductor layout pattern |
10312090, | Jul 28 2017 | United Microelectronics Corp.; Fujian Jinhua Integrated Circuit Co., Ltd. | Patterning method |
12106962, | Jun 07 2021 | United Microelectronics Corp. | Patterning method and overlay measurement method |
6803178, | Jun 25 2001 | Advanced Micro Devices, Inc. | Two mask photoresist exposure pattern for dense and isolated regions |
6872509, | Aug 05 2002 | Micron Technology, Inc. | Apparatus and methods for photolithographic processing |
7064078, | Jan 30 2004 | Applied Materials, Inc | Techniques for the use of amorphous carbon (APF) for various etch and litho integration scheme |
7368225, | Jun 25 2001 | Advanced Micro Devices, Inc. | Two mask photoresist exposure pattern for dense and isolated regions |
7375793, | Aug 05 2002 | Micron Technology, Inc. | Apparatus for photolithographic processing |
7718081, | Jan 30 2004 | Applied Materials, Inc. | Techniques for the use of amorphous carbon (APF) for various etch and litho integration schemes |
8435874, | Jan 23 2008 | SHENZHEN XINGUODU TECHNOLOGY CO , LTD | Method of forming openings in a semiconductor device and a semiconductor device fabricated by the method |
9524361, | Apr 20 2015 | United Microelectronics Corp. | Method for decomposing a layout of an integrated circuit |
Patent | Priority | Assignee | Title |
5573634, | Dec 23 1993 | Hyundai Electronics Industries Co. Ltd. | Method for forming contact holes of a semiconductor device |
5882827, | Aug 26 1996 | Mitsubishi Denki Kabushiki Kaisha | Phase shift mask, method of manufacturing phase shift mask and method of forming a pattern using phase shift mask |
6162370, | Aug 28 1998 | VERSUM MATERIALS US, LLC | Composition and method for selectively etching a silicon nitride film |
6204187, | Jan 06 1999 | Infineon Technologies AG | Contact and deep trench patterning |
6281562, | Jul 27 1995 | Godo Kaisha IP Bridge 1 | Semiconductor device which reduces the minimum distance requirements between active areas |
6303514, | Aug 28 1998 | VERSUM MATERIALS US, LLC | Composition and method for selectively etching a silicon nitride film |
JP5243115, | |||
JP907105, |
Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
May 24 2000 | KIM, KI-JOON | SAMSUNG ELECTRONICS CO , LTD | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 010844 | /0194 | |
Jun 01 2000 | Samsung Electronics Co., Ltd. | (assignment on the face of the patent) | / |
Date | Maintenance Fee Events |
Jun 05 2006 | M1551: Payment of Maintenance Fee, 4th Year, Large Entity. |
Jun 01 2010 | M1552: Payment of Maintenance Fee, 8th Year, Large Entity. |
Jun 02 2010 | ASPN: Payor Number Assigned. |
Aug 01 2014 | REM: Maintenance Fee Reminder Mailed. |
Dec 24 2014 | EXP: Patent Expired for Failure to Pay Maintenance Fees. |
Date | Maintenance Schedule |
Dec 24 2005 | 4 years fee payment window open |
Jun 24 2006 | 6 months grace period start (w surcharge) |
Dec 24 2006 | patent expiry (for year 4) |
Dec 24 2008 | 2 years to revive unintentionally abandoned end. (for year 4) |
Dec 24 2009 | 8 years fee payment window open |
Jun 24 2010 | 6 months grace period start (w surcharge) |
Dec 24 2010 | patent expiry (for year 8) |
Dec 24 2012 | 2 years to revive unintentionally abandoned end. (for year 8) |
Dec 24 2013 | 12 years fee payment window open |
Jun 24 2014 | 6 months grace period start (w surcharge) |
Dec 24 2014 | patent expiry (for year 12) |
Dec 24 2016 | 2 years to revive unintentionally abandoned end. (for year 12) |