In one disclosed embodiment, a collector is deposited and a base is grown on the collector, for example, by epitaxially depositing either silicon or silicon-germanium. An emitter is fabricated on the base followed by implant doping an extrinsic base region. For example, the extrinsic base region can be implant doped using boron. The extrinsic base region doping diffuses out during subsequent thermal processing steps in chip fabrication, creating an out diffusion region in the device, which can adversely affect various operating characteristics, such as parasitic capacitance and linearity. The out diffusion is controlled by counter doping the out diffusion region. For example, the counter doped region can be implant doped using arsenic or phosphorous. Also, for example, the counter doped region can be formed using tilt implanting or, alternatively, by implant doping the counter doped region and forming a spacer on the base prior to implanting the extrinsic base region.
|
1. A method comprising steps of:
depositing a collector; growing a base on said collector; fabricating an emitter on said base; implant doping an extrinsic base region in said base with a first dopant so as to create an out diffusion region; and counter doping said out diffusion region with a second dopant.
11. A method comprising steps of:
depositing a collector; growing a base on said collector; fabricating an emitter on said base; counter doping an out diffusion region with a first dopant; forming a spacer on said base; and implant doping an extrinsic base region in said base with a second dopant, said second dopant diffusing into said out diffusion region.
22. A structure comprising:
a collector comprising a single crystal silicon; a base comprising a single crystal material, said base and said collector forming a base-collector junction; an emitter comprising polycrystalline silicon, said emitter and said base forming a base-emitter junction in an intrinsic base region; an out diffusion region below an extrinsic base region; and a counter doped region below said out diffusion region.
2. The method of
3. The method of
4. The method of
5. The method of
6. The method of
7. The method of
8. The method of
9. The method of
10. The method of
12. The method of
13. The method of
14. The method of
15. The method of
16. The method of
17. The method of
18. The method of
depositing a conformal layer of a dielectric on said base; etching back said conformal layer of said dielectric so as to form said spacer on said base.
20. The method of
21. The method of
28. The structure of
30. The structure of
32. The structure of
|
1. Field of the Invention
The present invention relates to the field of fabrication of semiconductor devices. More specifically, the invention relates to the fabrication of silicon-germanium semiconductor devices.
2. Related Art
In a heterojunction bipolar transistor ("HBT"), a thin silicon-germanium layer is grown as the base of a bipolar transistor on a silicon wafer. The silicon-germanium HBT has significant advantages in speed, frequency response, and gain when compared to a conventional silicon bipolar transistor. Speed and frequency response can be compared by the cutoff frequency which, simply stated, is the frequency where the gain of a transistor is drastically reduced. Cutoff frequencies in excess of 100 GHz have been achieved for the HBT, which are comparable to the more expensive GaAs. Previously, silicon-only devices have not been competitive for use where very high speed and frequency response are required.
The higher gain, speeds, and frequency response of the HBT have been achieved as a result of certain advantages of silicon-germanium not available with pure silicon, for example, narrower band gap, and reduced resistivity. In addition, silicon-germanium may be epitaxially grown on silicon wafers using conventional silicon processing and tools, and allows one to engineer device properties such as the band gap, energy band structure, and mobilities. For example, it is known in the art that grading the concentration of germanium in the silicon-germanium base builds into the HBT device an electric field, which accelerates the carriers across the base, thereby increasing the speed of the HBT device compared to a silicon-only device. One method for fabricating silicon and silicon-germanium devices is by chemical vapor deposition ("CVD"). A reduced pressure chemical vapor deposition technique, or RPCVD, used to fabricate the HBT device allows for a controlled grading of germanium concentration across the base layer.
Because the benefits of a high gain and high speed silicon-germanium HBT device can be either partially or completely negated by high base contact resistance, it is important that the resistance of the base contact be kept low. In addition to the contact resistance, the geometry of the base regions may also affect the base resistance. The geometry of the base region may necessitate providing a low resistance electrical pathway through a portion of the base itself between the base contact and the base-emitter junction, referred to as the extrinsic base region. The extrinsic base region is heavily doped by implantation (also called extrinsic doping) in order to provide reduced resistance from the base contact to the base-emitter junction.
During the manufacture of an integrated circuit chip there are many processing steps which involve heating the wafer in which the integrated circuit chip is included. It is normal for dopants to diffuse out from where they have been implanted into surrounding areas of the chip during these heating processes. Typically, the out diffusion of dopants is accounted for in the design of a circuit device such as the HBT. Unwanted out diffusion can have disadvantageous effects, however, especially under certain circumstances. For example, there is drive in current technology to operate the HBT at lower voltages and comparatively higher collector currents for those low voltages. When the HBT is operated in a range of low voltage and high collector current, the effects of an energy barrier at the metallurgical transition from silicon-germanium to silicon near the base-collector junction can become more pronounced. Such an operating range can be characterized, for example, by a collector-emitter voltage in the range of approximately 1.0 to 4.0 volts and a collector current in the range of approximately 0 to 3.0 milliamperes ("mA"). Under these operating conditions, an energy barrier at the metallurgical transition from silicon-germanium to silicon near the base-collector junction has an effect of limiting current flow through the collector.
Out diffusion of dopants from the heavily doped extrinsic base region acts to further restrict collector current flow under these conditions and there are other deleterious effects on the operating characteristics and device parameters of the HBT device. For example, the operating range over which the HBT can operate linearly as class A amplifier is reduced. Briefly stated, a device operates as a class A amplifier if output current flows for all values of the input, as opposed to, for example, class B operation in which output current flows for one-half the cycle of the input waveform. Linear operation, simply stated, is the amplification of an input signal without distortion. A wider operating range for linear class A operation, i.e. one in which the maximum and minimum voltages and currents of the device are spaced further apart, is desirable because design flexibility and reliability are increased. As another example, power output in class A operation can be reduced because the reduced collector current directly reduces power which, simply stated is the product of current times voltage.
As a further example, out diffusion of dopants from the heavily doped extrinsic base region may increase a parasitic capacitance between the base and collector. Briefly, capacitance in an electric circuit relates to an effective flow of current due to the storage of electric charge between two otherwise electrically separated conductors. Parasitic capacitance between the base and collector effectively represents a near-short circuit in the HBT for a high frequency signal being amplified and is, thus, undesirable.
Also, for example, out diffusion of dopants from the heavily doped extrinsic base region can reduce a breakdown voltage of the HBT device. Briefly, the presence of a voltage, greater than the breakdown voltage, between the base region and a conductive region below the collector can cause the intervening material, which physically and electrically separates the two, to start to conduct electricity, known as "breakdown" of the intervening material. When breakdown occurs the HBT device no longer functions as intended, and can be permanently damaged. Thus, it is undesirable for breakdown voltage to be reduced.
Moreover, the effects of out diffusion on a device can limit the scalability of the device. Scalability, simply stated, refers to preserving the relative proportions of the various features of a device in such a way that the device still functions when the overall size of the entire device is reduced. As feature sizes of bipolar devices are reduced, it is important to achieve accurate control over the size of the various features in order to keep feature sizes in proportion. So for example, if out diffusion is not properly controlled the relative size of the out diffusion regions increases as the size of the entire bipolar device is reduced. An increase in the relative size of the out diffusion regions exacerbates the problems and disadvantages described above. Thus, the effects of out diffusion on the device can limit the scalability of the bipolar device. Furthermore, as feature size of CMOS devices is reduced it is important to achieve a concomitant reduction of feature size in bipolar devices on the same chip as CMOS devices.
One approach to the problem has been to use carbon in conjunction with the implant doping of the extrinsic base regions as a "suppressant" to control the amount of subsequent out diffusion of dopants from the extrinsic base regions. In general, the use of carbon for control of diffusion is complicated to implement from a technological viewpoint, is not generally available in the industry, and can require expensive tooling or retooling of the fabrication facility.
Thus, there is a need in the art to control out diffusion of dopants in bipolar devices. There is also need in the art for technologically simple, relatively low cost, readily available control of out diffusion of dopants in bipolar devices. There is a further need in the art for fabrication of bipolar devices which is scalable as the size of MOS and CMOS devices decreases.
The present invention is directed to a high performance bipolar transistor. The invention is used to control out diffusion of dopants in bipolar devices. The invention overcomes the need in the art for technologically simple, relatively low cost, readily available control of out diffusion of dopants in bipolar devices. The invention also provides fabrication of bipolar devices which is scalable to the size of MOS and CMOS devices as the size of MOS and CMOS devices decreases.
In one aspect of the invention a collector is deposited and a base is grown on the collector. For example, the base can be grown by epitaxially depositing either silicon or silicon-germanium on the collector. An emitter is then fabricated on the base followed by implant doping an extrinsic base region outside the emitter. For example, the extrinsic base region can be implant doped using boron with an implant dose of approximately 1015 atoms per square centimeter. The extrinsic base region doping diffuses out during subsequent thermal processing steps in chip fabrication, creating an out diffusion region in the device. The out diffusion region can adversely affect various operating characteristics of the device, such as parasitic capacitance and linearity. The out diffusion is controlled by counter doping the out diffusion region. For example, the counter doped region can be implant doped using arsenic or phosphorous with an implant dose of approximately 1013 atoms per square centimeter. Also, for example, the counter doped region can be formed using tilt implanting or, alternatively, by implant doping the counter doped region and then forming a spacer on the base prior to implanting the extrinsic base region.
The present invention is directed to a high performance bipolar transistor. The following description contains specific information pertaining to the implementation of the present invention. One skilled in the art will recognize that the present invention may be implemented in a manner different from that specifically discussed in the present application. Moreover, some of the specific details of the invention are not discussed in order to not obscure the invention. The specific details not described in the present application are within the knowledge of a person of ordinary skill in the art.
The drawings in the present application and their accompanying detailed description are directed to merely example embodiments of the invention. To maintain brevity, other embodiments of the invention which use the principles of the present invention are not specifically described in the present application and are not specifically illustrated by the present drawings.
By way of background,
As seen in
Also as seen in
Base 120 includes intrinsic base region 122. Single crystal N+ out-diffusion region 132 is situated above single crystal intrinsic base region 122. The base-emitter junction is formed within the single crystal layer at the boundary of N+ out-diffusion region 132 and intrinsic base region 122. Intrinsic base region 122 and base contacts 121 are electrically connected with each other through extrinsic base regions 124. Extrinsic base regions 124 and intrinsic base region 122 comprise base 120.
Continuing with
As seen in
In addition, silicon substrate 101, buried layer 102, epitaxial silicon 105, collector sinker 106, deep trench 108 and field oxide 110 isolation structures, base contacts 121, intrinsic base region 122, extrinsic base regions 124, out diffusion regions 126, out-diffusion region 132, dielectric segments 140, and distance WCx 155 are shown, respectively, as silicon substrate 201, buried layer 202, epitaxial silicon 205, collector sinker 206, deep trench 208 and field oxide 210 isolation structures, base contacts 221, intrinsic base region 222, extrinsic base regions 224, out diffusion regions 226, out-diffusion region 232, dielectric segments 240, and distance WCx 255. Thus, collector 204, base 220, and emitter 230 form NPN HBT 250 which is analogous to NPN HBT 150 in FIG. 1. The region enclosed by dashed line 260 corresponds to structures 360 of FIG. 3 and 460 of
Structure 200 includes collector 204, base 220, and emitter 230. Collector 204 is N type single crystal silicon which can be deposited epitaxially using an RPCVD process in a manner known in the art. Base 220 is P- type silicon-germanium single crystal which can be deposited epitaxially in a "nonselective" RPCVD process according to one embodiment. As seen in
As seen in
Continuing with
As seen in
The process of counter doping is known as applied in the fabrication of metal oxide semiconductor ("MOS") and complementary metal oxide semiconductor ("CMOS") devices such as field effect transistors ("FET"). For example, an application of counter doping to FET devices using tilt implant doping is described in "A 0.1-μm CMOS Technology with Tilt Implanted Punchthrough Stopper (TIPS)" by Takahashi HORI, in IEDM 94, pp 75-78, copy right 1994 by the Institute for Electrical and Electronics Engineers ("IEEE"). As another example, an application of counter doping to FET devices is described in "Source-to-Drain Nonuniformly Doped Channel (NUDC) MOSFET Structures for High Current Drivability and Threshold Voltage Controllability" by Yoshinori Okumura, et al., IEEE Transactions on Electron Devices, vol. 39, no. 11, pp 2541-52, November 1992. Counter doping in FET devices, as described in the two examples cited, is used for entirely different reasons compared to the reasons for its application in the present invention as described herein. Moreover, the results of counter doping in FET devices, such as described in the two cited examples, are entirely different from the results achieved by the invention as described in the present application.
Continuing with
As
Thus,
As
Implant doping 446 is followed by the formation of spacers 441. Spacers 441 can be formed, for example, by depositing a conformal layer of dielectric, such as silicon oxide, over emitter 430 and then etching back the conformal layer. Formation of spacers 441 is followed by P type doping 448 of extrinsic base regions 424 using conventional, i.e. non-angled, implanting. In one embodiment, extrinsic base regions 424 can be conventionally implant doped using P type doping 448, represented by non-angled arrows in FIG. 4. For example, extrinsic base regions 424 can be implant doped using non-angled implanting with boron, using an implant dose of approximately 1015 atoms per square centimeter, to produce P+ doped extrinsic base regions 424 with a dopant concentration of approximately 1020 atoms per cubic centimeter, as noted above in connection with FIG. 2.
Thus,
It is appreciated by the above detailed description that the invention provides a method for controlling out diffusion of dopants in the fabrication of bipolar transistors. The method eliminates problems associated with out diffusion of dopants from the heavily doped extrinsic base regions near the base-collector junction of a bipolar transistor. Using the invention, out diffusion of dopants can be controlled to improve the linearity, power output, base-collector parasitic capacitance and breakdown voltage of an HBT or conventional bipolar transistor. Further, using the invention, the scalability of the HBT can be improved where reduced feature size is needed. Although the invention is described as applied to the construction of a heterojunction bipolar transistor, it will be readily apparent to a person of ordinary skill in the art how to apply the invention in similar situations where control of dopant out diffusion for improved operating characteristics of a bipolar device is needed.
From the above description of the invention it is manifest that various techniques can be used for implementing the concepts of the present invention without departing from its scope. For example, although the particular embodiment of the present invention described here is applied to silicon-germanium bipolar HBT device, the invention is also applicable, for example, to silicon or silicon-germanium bipolar or BiCMOS devices. Moreover, while the invention has been described with specific reference to certain embodiments, a person of ordinary skill in the art would recognize that changes can be made in form and detail without departing from the spirit and the scope of the invention. The described embodiments are to be considered in all respects as illustrative and not restrictive. It should also be understood that the invention is not limited to the particular embodiments described herein, but is capable of many rearrangements, modifications, and substitutions without departing from the scope of the invention.
Thus, a high performance bipolar transistor has been described.
Kempf, Paul, Schuegraf, Klaus F., Zampardi, Peter J., Asbeck, Peter
Patent | Priority | Assignee | Title |
10211090, | Oct 12 2016 | GLOBALFOUNDRIES U S INC | Transistor with an airgap for reduced base-emitter capacitance and method of forming the transistor |
6764918, | Dec 02 2002 | DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT | Structure and method of making a high performance semiconductor device having a narrow doping profile |
6847061, | Apr 03 2003 | TAIWAN SEMICONDUCTOR MANUFACTURING CO , LTD | Elimination of implant damage during manufacture of HBT |
8232156, | Nov 04 2010 | GLOBALFOUNDRIES U S INC | Vertical heterojunction bipolar transistors with reduced base-collector junction capacitance |
8338863, | Nov 04 2010 | GLOBALFOUNDRIES U S INC | Vertical heterojunction bipolar transistors with reduced base-collector junction capacitance |
Patent | Priority | Assignee | Title |
5117271, | Dec 07 1990 | GLOBALFOUNDRIES Inc | Low capacitance bipolar junction transistor and fabrication process therfor |
6177325, | May 18 1998 | Winbond Electronics Corp | Self-aligned emitter and base BJT process and structure |
6262472, | May 17 1999 | National Semiconductor Corporation | Bipolar transistor compatible with CMOS utilizing tilted ion implanted base |
Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
Mar 13 2001 | ZAMPARDI, PETER J | Conexant Systems, Inc | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 011636 | /0394 | |
Mar 13 2001 | SCHUEGRAF, KLAUS F | Conexant Systems, Inc | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 011636 | /0394 | |
Mar 13 2001 | KEMPF, PAUL | Conexant Systems, Inc | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 011636 | /0394 | |
Mar 13 2001 | ASBECT, PETER | Conexant Systems, Inc | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 011636 | /0394 | |
Mar 17 2001 | Newport Fab, LLC | (assignment on the face of the patent) | / | |||
Mar 12 2002 | Conexant Systems, Inc | Newport Fab, LLC | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 012754 | /0852 | |
Jan 06 2006 | Newport Fab, LLC | WACHOVIA CAPITAL FINANCE CORPORATION WESTERN | SECURITY AGREEMENT | 017223 | /0083 | |
Sep 29 2023 | WELLS FARGO CAPITAL FINANCE, LLC, AS SUCCESSOR BY MERGER TO WACHOVIA CAPITAL FINANCE CORPORATION WESTERN | NEWPORT FAB, LLC DBA JAZZ SEMICONDUCTOR OPERATING COMPANY | RELEASE BY SECURED PARTY SEE DOCUMENT FOR DETAILS | 065284 | /0123 |
Date | Maintenance Fee Events |
Jul 03 2006 | M1551: Payment of Maintenance Fee, 4th Year, Large Entity. |
Jun 01 2010 | M1552: Payment of Maintenance Fee, 8th Year, Large Entity. |
Jul 07 2014 | M1553: Payment of Maintenance Fee, 12th Year, Large Entity. |
Jun 08 2016 | ASPN: Payor Number Assigned. |
Jun 08 2016 | RMPN: Payer Number De-assigned. |
Date | Maintenance Schedule |
Jan 14 2006 | 4 years fee payment window open |
Jul 14 2006 | 6 months grace period start (w surcharge) |
Jan 14 2007 | patent expiry (for year 4) |
Jan 14 2009 | 2 years to revive unintentionally abandoned end. (for year 4) |
Jan 14 2010 | 8 years fee payment window open |
Jul 14 2010 | 6 months grace period start (w surcharge) |
Jan 14 2011 | patent expiry (for year 8) |
Jan 14 2013 | 2 years to revive unintentionally abandoned end. (for year 8) |
Jan 14 2014 | 12 years fee payment window open |
Jul 14 2014 | 6 months grace period start (w surcharge) |
Jan 14 2015 | patent expiry (for year 12) |
Jan 14 2017 | 2 years to revive unintentionally abandoned end. (for year 12) |