A method of forming a flash eeprom device with a gate electrode stack includes forming a tunnel oxide layer, a floating gate electrode layer, a dielectric layer, and a control gate layer on a doped silicon semiconductor substrate. Then form source/drain regions in the substrate. Next, form a surface P+ doped halo region in the surface of the N+ source region juxtaposed with the control gate electrode. The P+ halo region is surrounded by the N+ source region. The result is a device which is erased by placing a negative voltage of about -10V on the control gate and a positive voltage of about 5V on the combined source region/halo region to produce accumulation of holes in the channel which distributes the flow of electrons into the channel rather than concentrating the electrons near the interface between the source region and the edge of the tunnel oxide layer. The tunnel oxide layer has a thickness from about 70 Å to about 120 Å.
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10. A flash eeprom memory device including:
a semiconductor substrate comprising doped silicon with the substrate having a surface, a gate electrode stack comprising a tunnel oxide layer, a floating gate electrode, a dielectric layer, and a control gate formed over the surface of the semiconductor substrate, a source region and a drain region formed in the substrate self-aligned with the gate electrode stack with the source region and the drain region overlapping the gate electrode stack, and an asymmetric arrangement with a surface halo region formed only in the surface of the source region surrounded by the source region and juxtaposed with the gate electrode stack and with a slight overlap of the halo region with the gate electrode stack, whereby the channel erase function can be performed with a similar bias condition to the source erase function.
19. A flash eeprom memory device including:
a semiconductor substrate comprising doped silicon, field oxide regions on the surface of the substrate, a gate electrode stack comprising a tunnel oxide layer, a floating gate electrode, a dielectric layer, and a control gate formed over the formed over the surface of the semiconductor substrate, a source region and a drain region formed in the substrate self-aligned with the gate electrode stack with the source region and the drain region overlapping the gate electrode stack, and an asymmetric arrangement with a surface halo region formed only in the surface of the source region surrounded by the source region and juxtaposed with the gate electrode stack and with a slight overlap of the halo region with the gate electrode stack, whereby the channel erase function can be performed with a similar bias condition to the source erase function.
1. A flash eeprom memory device including a doped substrate composed of silicon semiconductor material having a gate electrode stack formed on the top surface of the substrate, a source region and a drain region formed in the surface of the doped substrate comprising:
the gate electrode stack comprising a floating gate electrode, and a control gate formed over the top surface of the substrate, the source region and the drain region being located in the surface of the substrate, with the source region and the drain region being located aside from the gate electrode stack in overlapping relationship with the gate electrode stack, and a surface halo region formed only in the surface of the source region extending partially into the source region and surrounded by the source region and the halo region being juxtaposed with the gate electrode stack with a slight overlap in position of the halo region with the gate electrode stack, and the drain region being formed without a halo region, whereby the channel erase function can be performed with a similar bias condition to the source erase function.
2. The device of
3. The device of
5. A device in accordance with
the contact region is doped with boron P type dopant with a dose from about 5 E 14 ions/cm2 to about 5 E 15 ions/cm2.
6. The device of
7. The device of
8. The device of
9. The device of
11. The device of
12. The device of
13. The device of
14. The device of
the tunnel oxide layer has a thickness from about 70 Å to about 120 Å, and the contact region is doped with boron P type dopant with a dose from about 5 E 14 ions/cm2 to about 5 E 15 ions/cm2.
15. The device of
16. The device of
17. A device in accordance with
18. A device in accordance with
20. The device of
21. The device of
23. The device of
the tunnel oxide layer has a thickness from about 70 Å to about 120 Å, and the contact region is doped with boron P type dopant with a dose from about 5 E 14 ions/cm2 to about 5 E 15 ions/cm2.
24. The device of
25. The device of
26. A device in accordance with
27. The device of
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This is a division of patent application Ser. No. 09/102,122, filing date Jun. 19, 1998 now U.S. Pat. No. 6,087,219, Highly Reliable Flash Memory Structure With Halo Source, assigned to the same assignee as the present invention.
1. Field of the Invention
This invention relates to semiconductor devices and particularly to erasable programmable flash memory devices.
2. Description of Related Art
Holes induced by source erase cause a reliability problem in Flash memory devices. Although use of negative gate source erase alleviates hot hole injection, the problem is that it does not eliminate hot hole generation.
U.S. Pat. No. 5,395,773 of Ravindhran et al. shows a MOSFET with a gate penetrating halo implant. However, the halo implant is below the source/drain (S/D) regions and is for a different purpose from the halo ion implant of the invention.
An advantage of this invention is that a surface halo source structure is used in which an N-type region surrounds a P-type region forming a combined P-type/N-type source region. The result is provision of a channel erase function performed at the same bias voltage as the source erase, which eliminates hole injection and hole generation. Thus channel erase can be achieved with a bias condition similar to source erase. Hot hole injection can be eliminated due to the employment of channel erase.
In accordance with this invention, a Flash EEPROM memory device includes a gate electrode stack formed on the surface of a doped silicon semiconductor substrate and, a source region and a drain region formed in the surface of the doped silicon semiconductor substrate. The device includes a surface halo formed in the surface of the source region juxtaposed with the gate electrode stack without any halo region in the surface of the drain region. Thus, an asymmetric device is provided with the halo region separated from the semiconductor substrate by intervening portions of the source region. Preferably, the source region and the drain region are located in the surface of the substrate, with the source region and the drain region being located aside from the gate electrode stack in overlapping relationship with the gate electrode stack. In addition, a surface halo region is formed in the surface of the source region surrounded by the source region and juxtaposed with the gate electrode stack and with a slight overlap in position of the halo region with the gate electrode stack.
Preferably, a contact region is doped with P type boron dopant with a dose from about 5 E 14 ions/cm2 to about 5 E 15 ions/cm2. The contact region is formed in the doped silicon semiconductor material.
The P type BF2 dopant was ion implanted into a P+ type halo region with a dose from about 5 E 14 ions/cm2 to about 5 E 15 ions/cm2, at an energy from about 10 keV to about 30 keV. The tunnel oxide layer has a thickness from about 70 Å to about 120 Å.
The device is erased with a negative voltage from about -10 Volts to about -15 Volts on the control gate electrode and a positive voltage from about 10 Volts to about 5 Volts on the source region.
The device is erased with voltages applied during the erase mode as follows:
VCG = -10 V | |
VS = 5 V | |
VD = FL | |
VSub = FL | |
VCG = Control Gate Voltage | |
VS = Source Voltage | |
VD = Drain Voltage | |
VSub = P-Well Voltage | |
The foregoing and other aspects and advantages of this invention are explained and described below with reference to the accompanying drawings, in which:
In
Stack ST1 includes a tunnel oxide layer TX1 having a thickness from about 70 Å to about 120 Å formed on the surface of the P-substrate 11 above a channel region CH1 formed in P-substrate 11. Above tunnel oxide layer TX1 is formed a doped polysilicon, floating gate electrode FG1 having a thickness from about 1,000 Å to about 2,000 Å. Next is an Inter-Polysilicon Dielectric layer IPD, preferably composed of ONO (silicon Oxide/silicon Nitride/silicon Oxide). The ONO layer IPD is more broadly an Inter-Polysilicon Dielectric (IPD). On top is a control gate electrode CG1, composed of doped polysilicon having a thickness from about 1,000 Å to about 2,000 Å.
Shown on the left of the gate electrode stack ST1, is an N+ doped source region 16 self-aligned with stack ST1. Source region 16 is located between the gate electrode stack ST1 and the first FOX region 14. An N+ doped drain region 18 self-aligned with stack ST1 is located between gate electrode stack ST1 and the second FOX region 14'. The N+ doped source/drain regions 16/18 are doped with a dose of arsenic dopant ion implanted with a dose from about 5 E 14 atoms/cm2 to about 5 E 15 atoms/cm2 at an energy from about 25 keV to about 40 keV.
The N+ doped source region 16 and the N+ doped drain region 18 respectively overlap the opposing edges of the gate electrode stack ST1 with the channel CH1 of the Flash EEPROM device 10 located between N+ doped source region 16 and the N+ doped drain region 18.
Halo P+ doped region 20 is formed within the N+ doped source region 16 in the surface of the substrate 11 juxtaposed with the gate electrode stack ST1, but with a slight overlap between the halo P+ region 20 with the left edge of the gate electrode stack ST1.
On the right side of device 10 adjacent to drain region 18, a P+ doped contact region 22 is located in substrate 11 between the second FOX region 14' and third FOX 14" on the surface of substrate 11.
Above the interface between source region 16 and P+ doped surface halo region 20 is located a contact X1 connected to voltage source Vs which is set at five Volts (5V).
The cell structure is similar to a stack gate electrode structure except that there is the halo region 20 in the N+ source region in combination with the surface P+ halo region 20. A particular feature of the device of
During the erase condition, the control gate electrode CG1 is negatively biased at a voltage of about -10 Volts while the source region 16 is positively biased at a voltage of about 5 Volts. As a result, the channel CH1 will be in the accumulation mode (having an enhanced concentration of holes) and the N-type source region 16 will be inverted such that a hole channel is formed under the erase bias condition thereby causing the potential of the channel CH1 to be equal to the voltage applied to the source or about 5 Volts. A high electrical field is therefore established between the floating gate electrode and channel CH1 (filled with holes uniformly) such that a channel erase is achieved. The channel erase eliminates the hole generation and injection which occurs in the source erase (whether or not a negative control gate electrode voltage is applied) and to improve the reliability of the Flash Memory device.
In
The voltage Vsub is connected to the P- doped substrate 11. A contact X3 is formed above the P+ doped contact region 22. The P-substrate 11 is connected, via contact region 22, to voltage Vsub, which floats at voltage FL.
The device 11 is erased with a negative voltage from about -10 Volts to about -15 Volts on the control gate electrode CG1 and a positive voltage from about 10 Volts to about 5 Volts on the source region 16 and the halo region 20.
The range of voltages which can be applied during the erase mode are as follows:
TABLE I | |
VCG = -10 V to -15 V | |
VS = 10 V to 5 V | |
VD = FL | |
VSUb = FL | |
VCG = Control Gate Voltage | |
VS = Source Voltage | |
VD = Drain Voltage | |
VSub = P-Sub Voltage | |
Preferably the voltages applied during the erase mode are as follows:
TABLE II | |
VCG = -10 V | |
VS = 5 V | |
VD = FL | |
VSub = FL | |
VCG = Control Gate Voltage | |
VS = Source Voltage | |
VD = Drain Voltage | |
VSub = P-Well Voltage | |
Referring to
The N+ doped source region 216 and the N+ doped drain region 218 respectively overlap the opposing edges of the gate electrode stack ST2 with the channel CH2 of the Flash EEPROM device 210 located between N+ doped source region 216 and the N+ doped drain region 218. The electrons from the floating gate electrode FG2 pass down through the tunnel oxide layer TX2 directly to the source region 216 through a very narrow space as indicated by the arrow through tunnel oxide layer TX2 from the floating gate electrode FG2 to the source region 216.
The voltages applied during the erase mode are as follows:
TABLE III | |
VCG = -10 V | |
VS = 5 V | |
VD = FL | |
VCG = Control Gate Voltage | |
VS = Source Voltage | |
VD = Drain Voltage | |
Alternative Solutions for Alleviation of Hot Hole Injection Negative Gate Erase (Source Erase):
Using the approach of
Channel Erase (NAND operation)
Another way to alleviate hot hole injection is to extract electrons from the floating gate electrode to channel region uniformly so that band-to-band hole injection will not occur as illustrated in the Flash EEPROM device 410 shown in FIG. 4. Flash EEPROM device 410 includes an P-well 412 with a gate electrode stack ST4 centered on the surface of the P-well 412.
Stack ST4 includes a tunnel oxide layer TX4 formed on the surface of the P-well above the channel CH4. Above tunnel oxide layer TX4 is formed a floating gate electrode FG4, an ONO layer IPD and a control gate electrode CG4. Shown on the left of the gate electrode stack ST4, is an N+ doped source region 416. A N+ doped drain region 418 is located to the right of gate electrode stack ST4. Source/drain regions 416/418 are self-aligned with the gate electrode stack ST4.
The N+ doped source region 416 and the N+ doped drain region 418 respectively overlap the opposing edges of gate electrode stack ST4. The channel CH4 of the Flash EEPROM device 410 is located in the P-well 412 between N+ doped source region 416 and the N+ doped drain region 418. The electrons in the floating gate electrode pass through the tunnel oxide layer TX4 to the P-well 412 to the substrate through a wide space all along the tunnel oxide layer TX4, as indicated by the arrows through tunnel oxide layer TX4 from the floating gate electrode FG4 towards the lower surface of P-well 412.
The voltages applied during the erase mode are as follows:
TABLE IV | |
VCG = -10 V | |
VS = FL V | |
VD = FL V | |
VSub = 8 V | |
VCG = Control Gate Voltage | |
VS = Source Voltage | |
VD = Drain Voltage | |
VSub = Substrate Voltage | |
The problem with the channel erase approach shown in
In particular in
Stack ST5 includes a tunnel oxide layer TX5 having a thickness from about 70 Å to about 120 Å formed on the surface of the P-well above the channel CH5. Above tunnel oxide layer TX5 is formed a floating gate electrode FG5, composed of doped polysilicon having a thickness from about 1,000 Å to about 2,000 Å, an ONO layer IPD, and a control gate electrode CG5, composed of doped polysilicon having a thickness from about 1,000 Å to about 2,000 Å.
Shown on the left of the gate electrode stack ST5, is a self-aligned N+ doped source region 516. A self-aligned N+ doped drain region 518 is located to the right of gate electrode stack ST5. The N+ source/drain regions 516/518 are doped with a dose of arsenic dopant from about 5 E14 atoms/cm2 to about 5 E 15 atoms/cm2.
The N+ doped source region 516 and the N+ doped drain region 518 respectively overlap the opposing edges of the gate electrode stack ST5 with the channel CH5 of the Flash EEPROM device 510 located between N+ doped source region 516 and the N+ doped drain region 518 in P-Well 512. The electrons in the floating gate electrode FG5 pass through the tunnel oxide layer TX5 to the P-well 512 in an N-well 513 in the P- doped substrate 511 through a wide space all along the tunnel oxide layer TX5, as indicated by the arrows through tunnel oxide layer TX5 from the floating gate electrode FG5 towards the surface of P-well 512.
The P-well 512 includes a P+ doped region 522 to the right of the drain region 518 and the N-well 513 includes an N+ doped region 524 to the right of the P+ doped region 522. The voltage source Vsub is connected to the P+ doped region 522 and the N+ doped region 524. The N-well 513 is formed in the P-Substrate 511 and the substrate 511 is connected to voltage Vs which is a potential of 0 Volts .
The voltages applied during the erase mode are as follows:
TABLE V | |
VCG = -10 V | |
VS = FL | |
VD = FL | |
VSub = 8 V | |
VB = 0 V | |
VCG = Control Gate Voltage | |
VS = Source Voltage | |
VD = Drain Voltage | |
VSub = Substrate Voltage | |
VB = Ground Voltage | |
In
In accordance with this invention, a P+ doped halo region 620 is formed within and surrounded by the N+ doped source region 616. P+ doped halo region 620 is formed in the surface of the P-substrate 612 juxtaposed with the gate electrode stack ST6, but with a slight overlap of the halo P+ region 620 with the left edge of the gate electrode stack ST6.
The N+ doped source region 616 and the N+ doped drain region 618 respectively overlap the opposing edges of the gate electrode stack ST6. The channel CH6 of the Flash EEPROM device 610 is located between N+ doped source region 616 and the N+ doped drain region 618 in P-substrate 612. The electrons in the floating gate electrode FG6 pass through the tunnel oxide layer TX6 into the P-substrate 612 through a wide space all along the tunnel oxide layer TX6, as indicated by the arrows through tunnel oxide layer TX6 from the floating gate electrode FG6 towards the surface of P-substrate 612 along the channel CH6 and the source and drain regions 616/620 as well as the right edge of the halo region 620.
The P-substrate 612 includes a P+ doped region 622 to the right of the drain region 618 and adjacent thereto, but unlike the device of
The range of voltages which can be applied during the erase mode are as follows:
TABLE VI | |
VCG = -10 V to -15 V | |
VS = 10 V to 5 V | |
VD = FL | |
VSUb = FL | |
VCG = Control Gate Voltage | |
VS = Source Voltage | |
VD = Drain Voltage | |
VSub = P-Well Voltage | |
Preferably the voltages applied during the erase mode are as follows:
TABLE VII | |
VCG = -10 V | |
VS = 5 V | |
VD = FL | |
VSub = FL | |
VCG = Control Gate Voltage | |
VS = Source Voltage | |
VD = Drain Voltage | |
VSub = Substrate Voltage | |
The surface halo source Flash EEPROM memory in accordance with this invention shown in
1. A source biased channel erase feature is provided.
2. In addition, unlike the device of
Since the control gate electrode voltage is significantly negative (VCG=-10V) the channel CH6 accumulates holes.
The source voltage Vs=5V is distributed to the channel CH6 through the accumulated holes formed therein.
Method of Manufacture of Flash EEPROM device with surface halo region.
Then a tunnel oxide layer TX1, having a thickness from about 70 Å to about 120 Å, is formed as shown by block 702 in FIG. 7.
Next, FOX regions 14, 14' and 14" are formed on the surface of device 10 as described in block 704 in FIG. 7.
Then, as described in block 706 in
In block 708, a source/drain mask is formed with an opening over the source/drain regions for the device 10 and then the source/drain regions 16/18 are formed in a self-aligned ion implantation step. Then N+ dopant is ion implanted into source/drain regions 16/18 comprising a dose of arsenic dopant from about 5 E 14 ions/cm2 to about 5 E 15 ions/cm2 at an energy from about 25 keV to about 40 keV. Then the source/drain mask is stripped from the device 10.
Next, referring to block 710 in
Then the halo mask is stripped from the device.
Next, in accordance with block 712 in
Then, the contact region mask is stripped from device 10.
In block 714 contacts to the source 16, the drain region 18, contact region 22 and the N-sub are all provided.
While this invention has been described in terms of the above specific embodiment(s), those skilled in the art will recognize that the invention can be practiced with modifications within the spirit and scope of the appended claims, i.e. that changes can be made in form and detail, without departing from the spirit and scope of the invention. Accordingly all such changes come within the purview of the present invention and the invention encompasses the subject matter of the claims which follow.
Hsu, Ching-Hsiang, Liang, Mong-Song, Chung, Steve S.
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