An interleave frame is formed by combining slots corresponding to the same slot number in each frame when interleave process is performed in a super frame, and the data are read out along row or column direction (i.e. readout direction) and the data are written along the direction opposite to the readout direction in the same memory.
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1. A transmitter applicable to a transmission system capable of transmitting digital data, said digital data being encoded by using an error correction code and being modulated by a modulation scheme, said digital data being transmitted as packet units in multiplexed data with a frame structure consisting of N packets, said transmitter performing interleaving of a super frame unit, and comprising:
means for forming an interleave frame by combining packets corresponding to the same slot number in each frame; write means for sequentially writing data according to a frame number of the interleave frame into a two-dimensionally arrangeable memory along a row or column direction; and readout means for sequentially reading out the written data from the two-dimensionally arrangeable memory along a column or row direction different from the row or column direction of said write means.
2. A receiver applicable to a transmission system capable of transmitting digital data, said digital data being encoded by using an error correction code and being modulated by a modulation technique, said digital data being transmitted as packet units in the multiplexed data with a frame structure consisting of N packets, said receiver performing deinterleaving of a super frame unit, and comprising:
means for forming a deinterleave frame by combining packets corresponding to the same slot number in each frame; write means for sequentially writing data according to a frame number of the deinterleave frame into a two-dimensionally arrangeable memory along a column or row direction corresponding to a readout direction of an interleave process during transmission; and readout means for sequentially reading out the written data from the two-dimensionally arrangeable memory along a row or column direction different from the column or row direction of said write means and corresponding to a writing direction of the interleave process during transmission.
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The present invention relates to an interleaving technique involved in digital modulation and demodulation, especially to a transmitter and a receiver capable of performing the unified interleave and deinterleave without employing an interleave method corresponding to a multiplexing scheme based on each transmission mode when implementing multiplex transmission combining a plurality of transmission modes with different error endurance.
As structural examples, the implementing interleave process will now be described with reference to
In either example, as for the one slot transmitted by QPSK or BPSK, one interleave frame is formed in one super frame. To match the timing of signals after the interleaving, a first-in-first-out (FIFO) memory for storing data with a length of the super frame {(data length of assigned slots)-(length of the interleave frame)} is necessary for the greater assigned slot number (in the above example, the 46 slots or 44 slots data transmitted by the TC-8 PSK).
Since the interleave frame is 204×8 bytes, a FIFO memory is comprised of 204×46×8-204×8=73440 bytes in the example of
However, the capacity of the FIFO memory changes according to the assigned slot number for each of transmission modes in the frame, and a controller controlling the interleave process should be needed because address control is changed according to the change of the capacity of the FIFO memory, thereby complicating a circuit structure.
Therefore, an object of the present invention is to provide a transmitter and a receiver implementing an interleave process simply without changing the circuit configuration by changing the assigned slot number according to the transmission mode in each frame.
In the first aspect of the present invention, there is provided a transmitter applicable to a transmission system capable of transmitting digital data (called the transmission coded signal), which are encoded by using different types of error correction codes and modulated by different types of modulation with schemes, as packet units in the multiplexed data with a frame structure consisting of N packets, said transmitter performing interleaving of a super frame unit, and comprising:
means for forming an interleave frame by combining packets corresponding to the same slot number in each frame;
write means for sequentially writing data according to a frame number of the interleave frame into a two-dimensionally arrangeable memory along a row or a column direction; and
readout means for sequentially reading out the written data from the two-dimensionally arrangeable memory along a column or row direction different from the row or column direction of said write means.
In the second aspect of the present invention, there is provided a receiver applicable to a transmission system capable of transmitting digital data (called transmission coded signal), which are encoded by using different types of error correction codes and are modulated by different types of modulation techniques, as packet unit in the multiplexed data with a frame structure consisting of N packets, said receiver performing deinterleaving of a super frame unit, and comprising:
means for forming a deinterleave frame by combining packets corresponding to the same slot number in each frame;
write means for sequentially writing data according to a frame number of the deinterleave frame into a two-dimensionally arrangeable memory along the column or row direction corresponding to the readout direction of an interleave process during transmission; and
readout means for sequentially reading out the written data from the two-dimensionally arrangeable memory along the row or column direction different from the column or row direction of said write means corresponding to the writing direction of the interleave process during transmission.
A preferred embodiment of the present invention will be described in detail with reference to the drawings.
The present invention relates to an interleave process applicable to digital transmission. In particular, in a transmission system that can transmit mixed data comprising of different types of transmission modes as packet units in the multiplexed data with a frame structure consisting of N packets, an interleave frame is formed by combining slots corresponding to the same slot number in each frame, and the interleave process is performed every interleave frame, thus simply performing the interleave process under the same memory control even though various types of transmission modes in mixed data may be transmitted.
This example refers to a reading and writing process of a transmission system in that interleave in the transmitter and deinterleave in the receiver, which is opposite to the interleave can be performed. A concrete example will be described as follows.
The processings performed by the transmission and reception of the system will be described with reference to FIGS. 3(a) to 3(e).
FIG. 3(b) shows a memory 40 capable of being arrayed in two dimensions. First, when
In the present example, using the memory 40, the interleave process as to the data in the super frame 10 of
As an example, when slot number is 1, the interleave is performed as to the slots #1 of the first to eighth frames 20, and the data is written into the two-dimensional memory 40 along the row direction sequentially from the first slot of the first frame 20. In the present example, the ith data of each frame 20 (shaded area) is written every 203-byte data width.
After the data is written, the data is read out from the memory 40 along the column direction perpendicular to the row direction.
Table 1 shows a sequential arrangement of the actual read addresses and the data read addresses of the first slots according to each frame. Here, the numerals indicate frame-bytes.
TABLE 1 | ||||
Read addresses of first slots (frame-byte) | ||||
Second | 203th | |||
Start | byte | byte | ||
(frame-byte) | (frame-byte) | (frame-byte) | ||
first frame | 1-1 | 2-1 | 3-26 | |
second frame | 4-26 | 5-26 | 6-51 | |
third frame | 7-51 | 8-51 | 1-77 | |
fourth frame | 2-77 | 3-77 | 4-102 | |
fifth frame | 5-102 | 6-102 | 7-127 | |
sixth frame | 8-127 | 1-128 | 2-153 | |
seventh frame | 3-153 | 4-153 | 5-178 | |
eighth frame | 6-178 | 7-178 | 8-203 | |
By doing the readout process, interleave can be performed independently of the assigned slot number every each frame.
Furthermore, by exchanging the readout direction and the write direction, deinterleave can be performed in the receiver (i.e. the deinterleave process can be performed by writing the data according to the readout direction of the interleave and can be performed by reading out the data according to the write direction of the interleave).
On the other hand, when
As described above, according to the present invention, an interleave frame is formed by combining slots corresponding to the same slot number in each frame when the interleave process is performed in a super frame, and the data are read out along the row or column direction (i.e. readout direction) and the data are written along the direction opposite to the readout direction in the same memory. This makes it possible to obviate complicated memory address controllers according to transmission mode structures in the interleave or deinterleave process, thereby enabling a uniform control in any case.
Kumada, Junji, Hashimoto, Akinori, Matsumura, Hajime, Katoh, Hisakazu
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