A pulse-width-modulated DC-DC converter provides an output signal that is feedback to an error amplifier. The converter includes a comparator for comparing the output voltage of the error amplifier with the output voltage of a compensated ramp generator and having its output coupled to a switching transistor. The compensated ramp generator is designed so that the signal proportional to the current (IDrossel) through an inductor is superimposed on the ramp voltage so as to generate an output voltage having a sawtooth waveform with a concave rise.
|
5. A pulse-width-modulated DC-DC converter monolithic integrated circuit, comprising:
a series combination of a switching transistor and an inductor; a smoothing capacitor in series with a switching element for shunting said switching transistor so an input voltage (Vin) applied to said series combination of said switching transistor and said inductor is converted into a higher output voltage (Vout) appearing across said smoothing capacitor; an error amplifier having a first input connected to a voltage divider, to which said output voltage is be applied, and having a second input connected to a reference voltage source (Vref); and a comparator having its first and second inputs connected, respectively, to the output of said error amplifier and to a ramp generator responsive to a signal proportional to current (IDrossel) through said inductor, and having its output coupled to a gate electrode of the switching transistor, wherein said ramp generator superimposes said signal proportional to said current (IDrossel) through said inductor onto said ramp voltage, such that said ramp generator provides an output voltage having a sawtooth waveform with a concave voltage rise.
4. A pulse-width-modulated DC-DC converter integrated circuit, comprising:
a series combination of a switching transistor and an inductor; a smoothing capacitor in series with a switching element for shunting said switching transistor so an input voltage (Vin) applied to said series combination of said switching transistor and said inductor is converted into a higher output voltage (Vout) appearing across said smoothing capacitor; an error amplifier having a first input connected to a voltage divider, to which said output voltage is be applied, and having a second input connected to a reference voltage source (Vref); and a comparator having its first and second inputs connected, respectively, to the output of said error amplifier and to a ramp generator responsive to a signal proportional to current (IDrossel) through said inductor, and having its output coupled to a gate electrode of the switching transistor, wherein said ramp generator comprises means for superimposing said signal proportional to said current (IDrossel) through said inductor onto said ramp voltage, such that said ramp generator provides an output voltage having a sawtooth waveform with a concave voltage rise.
1. A pulse-width-modulated DC-DC converter comprising a series combination of a switching transistor and an inductor, with the switching transistor shunted by a smoothing capacitor in series with a switching element, so that an input voltage (Vin) applied to the series combination of the switching transistor and the inductor is converted into a higher output voltage (Vout) appearing across the smoothing capacitor, an error amplifier having its first input connected to a voltage divider, to which the output voltage can be applied, and having its second input connected to a reference voltage source (Vref), and a comparator having its first and second inputs connected, respectively, to the output of the error amplifier and to a ramp generator compensated by means of a signal proportional to the current (IDrossel) through the inductor, and having its output coupled to the gate electrode of the switching transistor,
characterized in that the compensated ramp generator is so designed that the signal proportional to the current (IDrossel) through the inductor is superimposable on the ramp voltage such that an output voltage having a sawtooth waveform with a concave voltage rise is generable, and the ramp generator is designed so that the sum of a correction current (Icorr), which is proportional to the inductor current (IDrossel), and a constant reference current (Iref) is integrable in the ramp generator so that the output voltage (Vramp) of the ramp generator rises quadratically, wherein for the generation of the correction current (Icorr), a first amplifier is provided, to whose input a voltage (VD) proportional to the inductor current (IDrossel) can be applied, and whose output is connected through a resistor to a first node (K1) of constant potential, to which the correction current (Icorr) is feedable, further characterized in that the constant node potential in the first node (K1) is generated by a second operational amplifier and a reference voltage source (Vref1).
2. A DC-DC converter as claimed in 1, comprising a third transistor whose gate electrode is connected to the gate electrode of the first transistor, wherein the first transistor, the third transistor, and the first amplifier together forming a current mirror having its output connected to the capacitor.
3. A DC-DC converter as claimed in
|
This invention relates to DC-DC converters, and in particular to a pulse-width modulated (PWM) DC-DC converter.
PWM DC-DC converters are widely used, see for example Maxim data sheet MAX 731/MAX 752, 19-4672; Rev 2; dated February, 1993. To generate a constant output voltage, the output voltage is fed back through a voltage divider, compared with a ramp voltage from a ramp generator via an error amplifier and the comparator, and applied to a switching transistor to adjust the duty cycle for the constant output voltage. Connected between the comparator and the switching transistor is a flip-flop to which the clock frequency of a clock is applied for activating the switching transistor.
The stability limit of the feedback DC-DC voltage converter is a function of the current through an inductor and the inverse of the input voltage. The inductor current is a function of the load current and the input voltage. The loop gain is influenced by the inductor current and the inverse of the input voltage. It increases with increasing inductor current, whereas the poles of the system, i.e., the phase shifts of the loop gain, remain unchanged. This results in a reduction of the phase margin and thus produces instability.
To compensate for this effect, capacitors are connected in parallel with the voltage divider which influence the frequency response in such a way that sufficient stability is achieved for a particular range of load currents and of the input voltage. Since the poles, which are determined by the smoothing capacitor and the inductor, are located at very low frequencies, very large compensation capacitors are necessary. These are not suitable for monolithic integration.
Another measure to stabilize the DC-DC converter is to add a voltage proportional to the inductor current to the ramp voltage from the ramp generator with an adder. Use is made of a voltage proportional to the current through the switching transistor. Thus, at high inductor currents, the comparator switches earlier, so that the on time of the switching transistor and the loop gain are reduced. This compensation has the disadvantage that an additional, accurate adder is needed to compensate the ramp generator. Another disadvantage is that at a high inductor current, the loop gain is reduced already at the beginning of the turn-on cycle. As a result, the gain is also reduced at high input voltages, which adversely affects the accuracy of the output voltage.
An object of the invention is to provide an improved pulse-width-modulated DC-DC converter.
Briefly, according to the present invention, a PWM DC-DC converter comprises a series combination of a switching transistor and an inductor, with the switching transistor shunted by a smoothing capacitor in series with a switching element, so that an input voltage applied to the series combination of the switching transistor and the inductor is converted into a higher output voltage appearing across the smoothing capacitor; an error amplifier having its first input connected to a voltage divider, to which the output voltage can be applied, and having its second input connected to a reference voltage source; and a comparator having its first and second inputs connected, respectively, to the output of the error amplifier and to a ramp generator compensated a signal proportional to the current through the inductor, and having its output coupled to the gate electrode of the switching transistor. The compensated ramp generator provides an output voltage having a sawtooth waveform with a concave voltage, wherein the signal proportional to the current through the inductor is superimposable on the ramp voltage.
Through the concave rise of the ramp voltage generated by the compensated ramp generator, a higher slew rate of the ramp voltage is attained. As a result, the gain of the feedback DC-DC converter is reduced only at high inductor currents and low input voltages. Consequently, the frequency response of the DC-DC converter can be held constant despite changes in operating conditions, particularly despite changes in input voltage and load current. A smaller loop gain at high input voltages, and thus a loss of accuracy of the output voltage of the DC-DC converter, is prevented.
In one preferred embodiment of the invention, the ramp generator is designed so that the sum of a correction current, which is proportional to the inductor current, and a constant reference current is integrable in the ramp generator, so that the output voltage of the ramp generator rises quadratically. By this design of the ramp generator, a frequency response of the DC-DC converter independent of the operating conditions is achieved in a simple manner. It is not necessary to use a device occupying a large area, such as an accurate adder.
In another preferred embodiment of the invention, the integration of the sum of the correction current and the constant reference current is accomplished by supplying the correction current and the constant reference current to a capacitor which can be discharged by a parallel-connected switching element at the frequency of the signal applied to the gate electrode of the switching transistor. A quadratic rise of the ramp voltage is thus obtained in a simple manner.
To generate the correction current, a first amplifier may advantageously be provided, to whose input a voltage proportional to the inductor current can be applied, and whose output is connected through a resistor to a first node of constant potential, to which the correction current can be supplied. For the amplifier, a unity-gain buffer can be used. It can be implemented with a feedback operational amplifier. The operational amplifier may have an output stage that includes a first reference current source in series with a first transistor connected in common-source configuration.
To generate the constant node potential in the first node, a second operational amplifier may be provided. The first input of the second operational amplifier is connected to a first constant reference voltage source, and the second input is connected to the first node. The first node makes the constant node potential available over a low-resistivity path and is connected to the output of the second operational amplifier. The output stage of the second operational amplifier may include a second reference current source in series with a second transistor connected in common-source configuration. Thus, the sum of the correction current and the constant reference current can flow into the node.
In yet another preferred embodiment of the invention, a current mirror is provided which mirrors the sum of the correction current and the constant reference current produced at the node onto the capacitor. The current mirror can be formed from the first and second operational amplifiers and a third transistor connected in common-source configuration. The gate of the third transistor is connected to the gate of the first transistor, and the drain of the third transistor is connected to the capacitor. In another embodiment, the gate of the third transistor is connected to the gate of the second transistor, and the drain of the third transistor is connected to the capacitor via a second current mirror.
The first transistor and the second transistor may have a fixed relationship to each other in terms of their electrical characteristics. In the case of MOSFET transistors, this is achieved by fixed W/L (width/length) ratios of the transistors. With the first and second reference current sources, currents having a fixed relationship to each other may be generable. If the reference current sources generate equal currents, and the first and second transistors have the same electrical characteristics, equal conditions exist in the circuit, so that a good match of the individual circuit elements is obtained, whereby electrical influences and influences of temperature or of mask alignment errors are avoided.
The signal proportional to the inductor current can be determined from the voltage drop across the switching transistor. This is possible since the switching transistor is operated in the triode region, so that it behaves as a resistor. Methods of determining the inductor current are known from the prior art, for example from German patent application P 198 12 299.3. Advantageously, the circuit is implemented using monolithic integrated circuit technology.
These and other objects, features and advantages of the present invention will become apparent in light of the following detailed description of preferred embodiments thereof, as illustrated in the accompanying drawings.
The output of the comparator 8 is connected through a flip-flop 20 to the gate of the switching transistor 2. The flip-flop 20 is controlled with a signal of frequency fclock from a clock. It is an R-S (reset-set) flip-flop with a reset input R, a set input S, and an active output Q, which is connected to the gate of the switching transistor 2. The frequency fclock of the signal from the clock is adapted to the frequency of the signal from the ramp generator 9. The output signal of the comparator 8 determines the frequency for switching the switching transistor 2.
Through the feedback provided around the pulse-width-modulated DC-DC converter, the duty cycle of the switching transistor is adjusted, whereby the output voltage Vout is regulated. At an excessive output voltage Vout, the output voltage Verror of the error amplifier is reduced. This reduces the on time TE of the switching transistor and, thus, the output voltage Vout of the DC-DC converter.
A third transistor 19, the first operational amplifier 12, and the output stage of the latter, which includes the first reference current source 14 and the first transistor 15, form a current mirror. The gate of the third transistor 19 is connected to the gate of the first transistor 15, and the drain of the third transistor 19 is connected to the capacitor 10. The first transistor 15 and the second transistor 18 have a fixed relationship to each other in terms of their electrical characteristics. Currents having a fixed relationship to each other are generated with the first and second reference current sources 14, 16. The first transistor 15 and the second transistor 18 may have the same electrical characteristics, and the first and second reference current sources 14, 16 may generate equal currents. In that case, particularly good matching of the overall system is achieved. Errors due to mismatches are avoided. The overall circuit can be implemented using monolithic integrated technology. The signal proportional to the inductor current IDrossel can be determined from the voltage drop across the switching transistor 2.
Although the present invention has been shown and described with respect to several preferred embodiments thereof, various changes, omissions and additions to the form and detail thereof, may be made therein, without departing from the spirit and scope of the invention.
Patent | Priority | Assignee | Title |
11567520, | Apr 07 2021 | Texas Instruments Incorporated | Exponential-based slope compensation |
6696821, | Feb 14 2002 | MONTEREY RESEARCH, LLC | DC-DC converter, duty-ratio setting circuit and electric appliance using them |
6734656, | Dec 10 2001 | INTERSIL AMERICAS LLC | Buck regulator with monolithic N- channel upper FET and pilot current sensing |
6753723, | Apr 03 2002 | Infineon Technologies Americas Corp | Synchronous buck converter with improved transient performance |
6781354, | Apr 03 2002 | Infineon Technologies Americas Corp | Synchronous buck converter with output current sensing |
6784650, | Nov 14 2000 | Polaris Innovations Limited | Circuit configuration for generating a controllable output voltage |
6803750, | Apr 03 2002 | Infineon Technologies Americas Corp | Multiphase synchronous buck converter with improved output current sharing |
6815938, | Apr 02 2002 | Rohm Co., Ltd. | Power supply unit having a soft start functionality and portable apparatus equipped with such power supply unit |
6828762, | Jul 05 2001 | BEL POWER SOLUTIONS INC | Inductor current sensing in isolated switching regulators and related methods |
6882132, | Oct 29 2002 | Infineon Technologies AG | DC voltage chopper for DC voltage |
6894464, | Apr 03 2002 | Infineon Technologies Americas Corp | Multiphase synchronous buck converter with improved power loss balancing |
6912144, | Aug 19 2004 | International Rectifier Corporation | Method and apparatus for adjusting current amongst phases of a multi-phase converter |
6920054, | Dec 04 2002 | STMicroelectronics S.A. | Pulse width modulated generator |
6997753, | Oct 22 2003 | W L GORE & ASSOCIATES, INC | Apparatus, system and method for improved calibration and measurement of differential devices |
7176669, | Mar 09 2004 | Denso Corporation | Switching regulator with frequency modulation to vary frequency based on a load condition, and control method therefor |
7298125, | Apr 26 2006 | Microchip Technology Incorporated | Right half-plane zero compensation and cancellation for switching regulators |
7388413, | Jul 14 2005 | Microsemi Corporation | Ramp generator with fast reset |
7391242, | Apr 07 2007 | Sawtooth waveform generator | |
7489121, | Nov 16 2005 | INTERSIL AMERICAS LLC | Compensation offset adjustment scheme for fast reference voltage transitioning |
7567067, | Aug 20 2004 | SAMSUNG DISPLAY CO , LTD | Power supply, display device, and light source driving apparatus |
7638995, | Jan 18 2005 | SHENZHEN XINGUODU TECHNOLOGY CO , LTD | Clocked ramp apparatus for voltage regulator softstart and method for softstarting voltage regulators |
7986154, | May 02 2008 | Sony Ericsson Mobile Communications AB | Capacitive sensing slide detection |
8129918, | Aug 20 2004 | SAMSUNG DISPLAY CO , LTD | Power supply, display device, and light source driving apparatus |
8138740, | Jan 29 2010 | IML International | Non-linear compensation ramp for current mode pulse width modulation |
9143034, | May 13 2013 | uPI Semiconductor Corp.; UPI SEMICONDUCTOR CORP | DC-DC controller and multi-ramp signal operating method thereof |
9608510, | Dec 02 2014 | Chengdu Monolithic Power Systems Co., Ltd. | Switching regulator and the method thereof |
Patent | Priority | Assignee | Title |
4546421, | Mar 28 1984 | WESTINGHOUSE NORDEN SYSTEMS INCORPORATED | Flyback feedforward pulse width modulation regulator |
5469029, | May 26 1993 | AGFA-GEVAERT, N V | Deflection apparatus for raster scanned CRT displays |
5982156, | Apr 15 1997 | The United States of America as represented by the Secretary of the Air; AIR FORCE, UNITED STATES | Feed-forward control of aircraft bus dc boost converter |
6011706, | Apr 09 1997 | SGS-THOMSON MICROELECTRONICS S R L | Control of the output power of a DC-DC converter upon varying the switching frequency |
DE9117264, | |||
EP498553, | |||
JP3234442, |
Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
Aug 03 1999 | GREITSCHUS, NORBERT | Micronas Intermetall GmbH | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 010163 | /0744 | |
Aug 09 1999 | Micronas GmbH | (assignment on the face of the patent) | / | |||
Jul 25 2000 | Micronas Intermetall GmbH | Micronas GmbH | CHANGE OF NAME SEE DOCUMENT FOR DETAILS | 011164 | /0084 | |
Jul 27 2009 | Micronas GmbH | TRIDENT MICROSYSTEMS FAR EAST LTD | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 023134 | /0885 | |
Apr 11 2012 | TRIDENT MICROSYSTEMS, INC | ENTROPIC COMMUNICATIONS, INC | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 028146 | /0054 | |
Apr 11 2012 | TRIDENT MICROSYSTEMS FAR EAST LTD | ENTROPIC COMMUNICATIONS, INC | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 028146 | /0054 | |
Apr 30 2015 | EXCALIBUR ACQUISITION CORPORATION | ENTROPIC COMMUNICATIONS, INC | MERGER AND CHANGE OF NAME SEE DOCUMENT FOR DETAILS | 035706 | /0267 | |
Apr 30 2015 | ENTROPIC COMMUNICATIONS, INC | ENTROPIC COMMUNICATIONS, INC | MERGER AND CHANGE OF NAME SEE DOCUMENT FOR DETAILS | 035706 | /0267 | |
Apr 30 2015 | EXCALIBUR SUBSIDIARY, LLC | Entropic Communications, LLC | MERGER AND CHANGE OF NAME SEE DOCUMENT FOR DETAILS | 035717 | /0628 | |
May 12 2017 | Maxlinear, Inc | JPMORGAN CHASE BANK, N A , AS COLLATERAL AGENT | SECURITY AGREEMENT | 042453 | /0001 | |
May 12 2017 | ENTROPIC COMMUNICATIONS, LLC F K A ENTROPIC COMMUNICATIONS, INC | JPMORGAN CHASE BANK, N A , AS COLLATERAL AGENT | SECURITY AGREEMENT | 042453 | /0001 | |
May 12 2017 | Exar Corporation | JPMORGAN CHASE BANK, N A , AS COLLATERAL AGENT | SECURITY AGREEMENT | 042453 | /0001 | |
Jul 01 2020 | JPMORGAN CHASE BANK, N A | MUFG UNION BANK, N A | SUCCESSION OF AGENCY REEL 042453 FRAME 0001 | 053115 | /0842 | |
Jun 23 2021 | MUFG UNION BANK, N A | Maxlinear, Inc | RELEASE BY SECURED PARTY SEE DOCUMENT FOR DETAILS | 056656 | /0204 | |
Jun 23 2021 | MUFG UNION BANK, N A | Exar Corporation | RELEASE BY SECURED PARTY SEE DOCUMENT FOR DETAILS | 056656 | /0204 | |
Jun 23 2021 | MUFG UNION BANK, N A | MAXLINEAR COMMUNICATIONS LLC | RELEASE BY SECURED PARTY SEE DOCUMENT FOR DETAILS | 056656 | /0204 |
Date | Maintenance Fee Events |
Aug 18 2006 | M1551: Payment of Maintenance Fee, 4th Year, Large Entity. |
Apr 30 2008 | ASPN: Payor Number Assigned. |
Jan 28 2010 | ASPN: Payor Number Assigned. |
Jan 28 2010 | RMPN: Payer Number De-assigned. |
Aug 18 2010 | M1552: Payment of Maintenance Fee, 8th Year, Large Entity. |
Aug 18 2014 | M1553: Payment of Maintenance Fee, 12th Year, Large Entity. |
Date | Maintenance Schedule |
Feb 18 2006 | 4 years fee payment window open |
Aug 18 2006 | 6 months grace period start (w surcharge) |
Feb 18 2007 | patent expiry (for year 4) |
Feb 18 2009 | 2 years to revive unintentionally abandoned end. (for year 4) |
Feb 18 2010 | 8 years fee payment window open |
Aug 18 2010 | 6 months grace period start (w surcharge) |
Feb 18 2011 | patent expiry (for year 8) |
Feb 18 2013 | 2 years to revive unintentionally abandoned end. (for year 8) |
Feb 18 2014 | 12 years fee payment window open |
Aug 18 2014 | 6 months grace period start (w surcharge) |
Feb 18 2015 | patent expiry (for year 12) |
Feb 18 2017 | 2 years to revive unintentionally abandoned end. (for year 12) |