Recording equalizer and magnetic recording/reproducing apparatus using the equalizer

Abstract

A recording equalizer for correcting a write timing of magnetic information when the magnetic information is recorded with a magnetic recording head on a magnetic recording medium, includes a buffer for storing a recording object bit and bits before and after the recording object bit and a calculator for calculating a precompensation parameter using the bits stored in the buffer. The calculator calculates the precompensation parameter of the recording object bit by linearly adding influence of a transition existing at a two-previous bit of the recording object bit, influences of a transition at a one-previous bit of the recording object bit and influences of a transition existing at one-following bit of the recording object bit and further adding an offset. The offset is determined to a value such that a write timing of the magnetic information is corrected always in a delaying direction.

Description

CROSS REFERENCES TO RELATED APPLICATIONS

This is a continuation of U.S. Ser. No. 10/079,492, filed Feb. 22, 2002, now U.S. Pat. No. 6,487,031 which is a continuation of U.S. Ser. No. 09/790,613, filed Feb. 23, 2001, which issued as U.S. Pat. No. 6,356,402 on Mar. 12, 2002, and which is a continuation of U.S. Ser. No. 09/085,860, filed May 28, 1998 and issued as U.S. Pat. No. 6,212,024 on Apr. 3, 2001.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to a magnetic recording/reproducing apparatus used for an auxiliary recording apparatus of a computer, or the like. More particularly, it relates to a recording equalizer for correcting an interference between adjacent codes that occurs when magnetic information is recorded, and a magnetic recording/reproducing apparatus using the recording equalizer.

2. Description of the Related Art

Demands for a higher density and a higher memory capacity of magnetic disk apparatuses used as an external storage apparatus of a computer have become stronger and stronger with the progress of so-called "information society". The recording density of the magnetic disk apparatuses has become higher at present at an annual ratio of 40 to 60%. Such a rapid progress of the high density has been supported not only by the development of low noise media but also by the introduction of new technologies such as an MR (Magnetoresistive) head and a PRML (Partial Response Maximum Likelihood) system.

In comparison with a conventional 1-7/PD (Peak Detection) system, the PRMI system records information at a magnetization inversion density (FCI: flux changes per inch) of 1.5 times on a recording medium in the case of the same linear recording density (BPI: bits per inch). Therefore, various counter-measures which have not been necessary in the past, must be taken in order to cope with various phenomena that occur at a high magnetization inversion density and in a high frequency range. One of such phenomena is a non-linear phenomenon at the time of recording represented by an NLTS (Non-Linear Transition Shift). In the PRML system, in particular, linearity of a recording/reproducing channel is required so as to fully exploit its performance.

In the PRML channel, judgment is done by using an amplitude value obtained by sampling a reproduction waveform and for this reason, sampling at a correct timing and equalization to a correct waveform position are essentially necessary. To achieve this object, the magnetization inversion position to be written by a magnetic head to a recording medium must be controlled correctly. If any demagnetizing field exists inside the medium, however, a head magnetic field is modulated and deviation occurs in the magnetization inversion position to be written. The NLS is the phenomenon in which this magnetization inversion position shifts from the inversion position that is expected from the timing of inversion of a recording current. The inversion of the recording current occurs when recording bits are "1".

Among the influences of the NLTS, the influence from one-previous bit is the greatest, and the magnetization inversion position to be written (the magnetization inversion position expected from the inversion timing of the head magnetic field) is shifted in a direction opposite to a travelling direction of a recording head as viewed from the recording medium. To correct such a shift of the recording position, a control method of a magnetization inversion position, which deviates the inversion timing of the head magnetic field in accordance with a recording pattern and controls the magnetization inversion position to a correct position on a medium (precompensation), has been employed in the past.

One of the methods of precompensating for the NLTS delays the inversion timing by a time corresponding to the shift described above from a timing of a basic clock by considering the magnetic field resulting from the magnetization transition occurred at the one-previous bit and further the two-previous bit. This method is described in IEEE Transactions on Magnetics Vol. 26, No. 5, September 1990, p. 2298.

When this method, which executes precompensation of the NLTS by delaying the inversion timing, is applied to a magnetic recording apparatus for achieving a recording density of at least 1.5 giga-bit per square inch, however, the magnetization inversion position gets disturbed and an erroneous operation occurs.

On the other hand, JP-A-8-96312 and JP-A-8-203006. describe recording/reproducing apparatus performing the precompensation.

The former describes a circuit for correcting amplitude characteristics and phase characteristics of a recording current and the latter describes a controller of an amplification gain of read data. Nonetheless, both do not consider the influence of the magnetization transition of the following bits of a recording bit.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a recording equalizer which reduces variance of a magnetization inversion position by improving accuracy of precompensation and is suitable for high density recording, and a magnetic recording apparatus for achieving a recording density of at least 2 giga-bit per square inch by using the recording equalizer.

The recording equalizer for accomplishing the object of the invention described above employs the following construction and has the following features.

The recording equalizer is for precompensating for a write timing of magnetic information when the magnetic information is recorded with a magnetic recording head on a magnetic recording medium, and includes a precompensation parameter calculator for calculating a precompensation parameter. The precompensation parameter calculator adds an offset C so that the write timing of the magnetic information is precompensated always in a delaying direction, and outputs the precompensation parameter. Assuming that a precompensation parameter when a first bit of a isolated dibit spaced apart by at least a 3-bit length from a previous transition and by at least a 2-bit length from a following transition is A, the offset C is decided so that A becomes positive and is smaller than a write basic clock cycle.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a basic structural view of a recording equalizer according to the present invention;

FIG. 2 is a diagram showing the relationship between a bit length to be written and a shift of a transition position;

FIG. 3 is a structural view of a signal processor of a magnetic recording apparatus according to the present invention; and

FIG. 4 is an explanatory view showing the comparison of a write current pulse waveform of the present invention with a waveform of the prior art.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Hereinafter, a preferred embodiment of the present invention will be explained with reference to the accompanying drawings.

(1) Construction of Recording Equalizer

FIG. 1 shows a basic construction of a recording equalizer according to the present invention. The recording equalizer 1 includes a data buffer 2, an offset register 4, a precompensation parameter calculator 5 and a write current driver 6.

Each bit A(n-1), A(n), A(n+1),--of write data is inputted to the data buffer 2. Assuming that a write object bit is A(n), at least previous bits A(n-2) and A(n-1) and a following bit A(n+1) are stored in the data buffer 2 besides the write object bit A(n). The data buffer 2 has a function of transferring this bit information to the precompensation parameter calculator 5 and the write current driver 6 at any time.

The precompensation parameter calculator 5 includes a microprocessor and a memory. The precompensation parameter calculator 5 calculates a precompensation parameter d using the bit sequence sent from the data buffer 2 and the value C of the offset register 4. Since a relative velocity (peripheral velocity) between a recording medium and a magnetic head and a basic frequency (write frequency: frequency of a write PLL circuit) determined by the highest recording density are necessary for this calculation, these values are inputted from the outside. The calculation method of this precompensation parameter will be described later.

After calculating the precompensation parameter d, the precompensation parameter calculator 5 delivers this value d to the write current driver 6. The write current driver 6 has a function of inverting a current polarity in such a manner as to correspond to the A(n) information. In other words, the write current driver 6 inverts the current polarity only when A(n) is a "1" bit.

The write current driver 6 delays this current polarity inversion timing by a time corresponding to the precompensation parameter d.

(2) Calculation Method of Precompensation Parameter

First, an approximate expression used for calculating the precompensation parameter d is determined.

Incidentally, a "11" portion in a bit sequence "-0110-" is referred to as a "dibit". In this dibit, the current polarity inversion occurring at the first "1" portion is referred to as the "first transition" and the current polarity inversion occurring at the second "1" portion, as the "second transition".

The dibit is written to a recording medium by inverting a head magnetic field in accordance with a write clock, that is, under the state where the precompensation is not effected, and a position of actual magnetization inversion on the medium is measured. The difference between the head magnetization inversion position and the magnetization inversion position on the medium is represented by the distance on the medium and is referred to as a "shift".

To measure this shift, a dibit spaced apart by at least a three-bit length from a previous transition and by at least a two-bit length from a following transition, such as "-00110-", is hereby used. The dibit of this type is referred to as an "isolated dibit".

FIG. 2 shows the result of a measurement of the first transition shift S1 and the second transition shift S2 when several dibits are recorded on a magnetic recording medium having a film thickness of 30 nm and a coercive force of 2,400 Oe by using an inductive head having a gap of 200 nm at a recording current of 40 mA. One bit length L of the dibit is plotted on the abscissa and the deviation of the transition positions to be written (expected from the inversion timing of the head magnetic field) from the magnetization inversion position, that is, the shift Sh, is plotted on the ordinate of the diagram. The travelling direction of the recording head as viewed from the recording medium represents the positive direction of the ordinate.

It can be appreciated from FIG. 2 that the smaller the bit length L, the greater the first and second transition shifts S1 and S2. The second transition shift S2, for example, exhibits a shift of 9 nm at a bit length of 150 nm and a shift of 20 nm at a bit length of 100 nm in the direction opposite to the travelling direction of the recording head. In this instance, the first transition shift S1 is 32% of the second transition shift S2 at the respective bit lengths in the opposite direction (or in the travelling direction of the recording head). These relationships can be approximated by the following expressions 1 and 2 by representing the bit length L and the transition shifts (S1 and S2) in the m unit:

S2=-2×10^-22/L²=f(L)(m) expression 1

S1=-R×S2(where R=0.32)(m) expression 2

where f(L) means a function of the bit length L.

The approximate expressions need not always assume the forms of the expressions 1 and 2 and may assume any forms so long as they can approximate the transition shifts for the bit length. For example, the transition shifts for necessary bit lengths may be stored in advance in the form of a table. Generally, the ratio R described above is calculated by measuring several second transition shifts S2 for the bit length L so as to establish a simple approximate expression and examining further at least one first transition shift S1.

FIG. 4 is an explanatory view showing the relationship between a write current pulse waveform which is not precompensated and a write current pulse waveform which is precompensated and a relationship between a write clock and a precompensation parameter. Timechart (a) shows a current pulse waveform for writing information A(-2) to A(5). Timecharts (b) and (c) are explanatory views of a precompensation method without setting an offset and timecharts (d) and (e) are explanatory views of a precompensation method which sets the offset C.

The explanation will be given hereby about the case where a bit sequence "001001100" is recorded on the medium in a bit length of 100 nm, by way of example. In this bit sequence, A(0) satisfies the condition of an isolated transition while A(3) and A(4) satisfy the condition of an isolated dibit. If recording is done at this original inversion timing, the transition position of A(3) shifts in a phase delay direction by about 8 nm while the transition position of A(4) shifts in a phase advance direction by about 20 nm as shown in FIG. 2. The precompensate for these shifts, the inversion timing of the write current should be regulated so that the phase of A(3) advances by 8 nm while that of A(4) delays by 20 nm.

Timechart (b) shows an example of the write current pattern the inversion timing of which is regulated so that the phase of A(3) advances by 8 nm while that of A(4) delays by 20 nm. In other words, as shown in timechart (c), the first transition A(3) of the isolated dibit is advanced by d3 from the write clock T while the second transition A(4) is delayed by d4 from the write clock T. Recording precompensation is not done for the isolated transition A(0) (d0=0) in timechart (c). To execute this precompensation, however, circuits and a write current driver for advancing the inversion timing in A(3), that is, for enabling negative precompensation d3 in a timechart (c) are necessary, and that results in the increase of the production cost. To avoid this negative precompensation, therefore, the offset C is added to the precompensation parameter dn in (c).

When the offset C shown in (d) is set, the waveform of the write current is exactly the same as that of the precompensated waveform shown in (b) with the exception of the overall phase shift (offset C). Each precompensation parameter d0', d3', d4' does not become negative as shown in (e) if an appropriate offset C is set in advance and the offset C is applied to all the bits. Therefore, the circuits for executing negative precompensation are not necessary.

Next, the calculation principle of the precompensation parameter d such as d3', d4', etc., shown in (e) will be explained. The approximate expressions 1 and 2 obtained from FIG. 2 are used for this calculation. The precompensation parameter dn' of A(n) is given by the following expression 3:

dn'=(-ƒ(2L)·A(n-2)·(-1)^{A(n-2)+A(n-1)}-ƒ(L)·A(n-1)·(-1)^A(n-1)-R·ƒ(L)·A(n+1))/v+C(S) expression 3

where

f( ): function of expression 1

L: length of one bit (m)

v: head-medium relative velocity (peripheral velocity) (m/s)

The first term of the expression 3 takes the influences into consideration when any transition exists in the two-previous bit A(n-2) while the second term takes the influences into consideration when any transition exists in the one-previous bit A(n-1). The third term takes the influences into consideration when any transition exists in the one-following bit A(n+1). The value R is in the expression 2 obtained from FIG. 2, which is 0.32. The last term of the expression 3 is the offset C.

Here, the length L of one bit is expressed by the following expression 4:

L=v/fw(m) expression 4

where fw: basic write clock frequency (Hz)

Alternatively, the length L of one bit can be determined from the following expression 5 where S is the disk rotation number per minute and r is the distance of the head position from the disk spindle:

L=2π·r·S/60fw(m) expression 5

The head position may be obtained from a control signal of an actuator for driving the head, or the head position may be written in advance to the leading part of the sector of the medium.

The offset C is set in such a fashion that the precompensation parameter of the first bit of the isolated dibit does not become a negative value and moreover, it is smaller than the cycle of the basic clock. $\begin{array}{cc}\frac{1}{\mathrm{fw}}>C>\frac{\mathrm{S1}}{v}\⁢\⁢\left(s\right)& \text{expression\ \ 6}\end{array}$

More correctly, the offset C varies with a recording density and a peripheral velocity. Since they are different between the inner periphery of the medium and its outer periphery, the value C calculated by the expression 6 becomes greater at positions closer to the inner periphery. To simplify the circuit, however, the offset C satisfying the expression 6 is selected for the case where the recording density attains the highest (generally, the innermost periphery), and this C value is applied to the entire portions. In other words, this C value is stored as a constant in the offset register 4 (shown in FIG. 1).

In this way, the precompensation parameter d for recording A(n) can be calculated from the peripheral velocity, the clock frequency and the bit sequence.

The afore-mentioned expressions 2 and 3 employ R as the constant. Though this R value of 0.32 is determined from the actual measurement values of the shifts S1 and S2, the value varies with the medium and the head used.

Table 1 illustrates the ratio R (R=-S1/S2) of the first transition shift S1 to the second transition shift S2 measured for the combinations of various media and heads. In Table 1, the term "high density recording" represents recording at 250 kFCI. The term "excellent"represents an S/N ratio of at least 30 dB, the term "good" represents an S/N ratio of 26 to 30 dB, the term "fair" represents an S/N ratio of 22 to 26 dB and the term "inferior" represents an S/N ratio of less than 2 dB.

TABLE 1
recording condition
medium				high
coercive	recording	recording	R	density
force	head gap	current	value	recording
2400 Oe	200 nm	40 mA	0.32	good
2400 Oe	400 nm	40 mA	0.59	fair
2400 Oe	600 nm	40 mA	0.70	inferior
2400 Oe	200 nm	30 mA	0.35	good
2400 Oe	200 nm	60 mA	0.35	good
2600 Oe	200 nm	40 mA	0.25	excellent
2800 Oe	200 nm	40 mA	0.16	excellent

It can be appreciated from Table 1 that high density recording can be done when the value R is smaller than 0.6. Though a Co--Pt alloy is used for the medium and a Ni--Fe alloy is used for the write head material in this examination, the value R can be lowered to about 0.05 by improving further the coercive force of the medium and the saturation flux density of the head material and narrowing the gaps.

Practically, therefore, the value R that can be applied to the express 3 satisfies the following relationship:

0.05<R<0.6

When R is smaller than 0.05, a sufficient recording density cannot be obtained and when it is greater than 0.6, a reproduction output cannot be obtained.

(3) Magnetic Recording/Reproducing Apparatus

FIG. 3 is a block diagram of a signal processor of a magnetic recording/reproducing apparatus including the recording equalizer described in section (1). Recording information (data) is first inputted to a modulator 7. The modulator 7 processes the original data in accordance with a predetermined rule so that "0"s exceeding a predetermined number do not exist. The output of this modulator 7 is sent to a precoder 8. The precoder 8 processes the data into a code which is strong to interference between adjacent signals. For example, the precoder 8 equalizes data "00100" to "001 100". The output signal from the precoder 8 is hereby called "A(n)". The A(n) signal is sent to the recording equalizer 1 shown in FIG. 1. The processing in the recording equalizer 1 is the same as the processing described already.

The output from the recording equalizer 1 is assumed to be A(n+d). Here, the value d represents the difference (precompensation parameter) between the write basic clock and the timing at which the actual write operation is made. The precompensation parameter d is calculated, and is controlled, by the recording equalizer 1 as already described. The output from the write current driver (see FIG. 1) disposed in the last stage of the recording equalizer 1 is sent to the write head 15. This output is hereby recorded as the magnetic information on the recording medium 17 by the electromagnetic conversion operation.

When this magnetic information is read out, it is again converted to electric signals by using the electromagnetic conversion operation by a read head 16. The write head 15 may be used also as the read head 16. When the read head 16 is separated from the write head 15, a magnetoresistive (MR) device or a gigamagnetoresistive (GMR) device can be used because they have a high sensitivity and are suitable for high density recording. Since the electric signals from the read head 16 are weak, the signals are first inputted to a pre-amplifier 10 and then to a PR equalizer 11 and an ML decoder 12.

The PR equalizer 11 executes the inverse conversion to that of the processing of the precoder 8. For example, it executes the inverse conversion of the information "001100" to "00100". In this instance, the inverse conversion is done to the "1" and "0" information by conducting a comparison processing of the reproduction waveform with a learning waveform which inputs in advance an inter-code interference. The ML decoder 12 executes decoding in accordance with the rule provided in advance to the modulator output on the basis of the information of several-bits before and after the reproduced information.

The operations of these PR equalizer 11 and ML decoder 12 should be done at a predetermined operation timing. Otherwise an erroneous information would be decoded. It is easily understood by those skilled in the art. Therefore, the PR equalizer 11 and the ML decoder 12 acquire their operation timing by using the output of a common VCO (voltage control oscillator) 13. Finally, the information is serially inputted to the demodulator 14 and the inverse conversion is done to the original form of the recording information (the form containing continuation of "0").

This magnetic recording apparatus controls the magnetization area recorded on the recording medium (the gap between magnetization transitions) to some multiples of the one-bit length and for this reason, the rotation of the disk should be stabilized time-wise. The operations such as the reference of the timing at which new information is stored in the data buffer and the reference of the timing using which as a base the recording current is inverted are synchronized with the same basic write clock in the recording equalizer and consequently, the control described above can be carried out highly accurately.

(4) Modified Embodiment

The afore-mentioned precompensation parameter calculator 5 inputs with the bit sequence, the peripheral velocity, the clock frequency and the offset, and calculates the precompensation parameter for each bit. Instead, it is possible to employ a circuit construction in which a bit judgement circuit is interposed between the data buffer 2 and the precompensation parameter calculator 5 and a correspondence table among the bit sequence, the peripheral velocity, the clock frequency and the precompensation parameter is installed inside the precompensation parameter calculator 5. The precompensation parameters are calculated in advance and stored in the table. In this case, the offset C should be determined while taking the recording density and the peripheral velocity into consideration.

The embodiment described above uses the information A(n-2) of up to the two-previous bit for calculating the precompensation parameter of A(n). Generally, the information A(n-1) up to one-previous bit should be used to improve the speed, and the information up to further one-previous bit should be used to accomplish a higher density. The information up to one-previous bit should be used at a recording density of about 150 kFCI and the information up to three-previous bit must be used beyond a recording density of 300 kFCI. Therefore, the capacity of the data buffer and the number of terms of the calculation expression of the precompensation parameter vary with the recording speed and the recording density that are applied.

Claims

1. A signal processing circuit comprising:

a write current driver;

a table in which a plurality of predetermined values of a compensation parameter d is stored;

a data buffer for storing a bit sequence of write data and

a bit judgment circuit, wherein;

said bit judgment circuit determines a value of said compensation parameter d in accordance with a write object and its previous bit, and

said write driver delays an inversion timing of said object from a write timing clock using said parameter d.

2. A signal processing circuit comprising:

a write current driver;

means for storing a plurality of values of predetermined compensation parameter d,

means for storing a bit sequence of write data;

means for selecting one of said plurality of values of said parameter d, wherein;

said means for storing a bit sequence of write data transfers the bit sequence to said write driver synchronized with a predetermined write clock;

said means for selecting a value of said parameter d selects said compensation parameter d in accordance with a write object bit and its previous bit, and

said write driver delays an inversion timing of said object bit by said parameter d from said write timing clock.

3. A signal processing circuit comprising:

a write current driver;

a data buffer for storing a bit sequence of write data, and

a compensation parameter calculator, wherein

said data buffer transfers said bit sequence to said write driver synchronized with a predetermined write clock;

said compensation parameter calculator determines a compensation parameter d in accordance with a write object bit and its previous bit, and

said write driver delays an inversion timing of said object bit by said parameter d from said write timing clock.

4. A signal processing circuit according to claim 1, further comprising:

a partial response equalizer circuit; and

a maximum likelihood demodulator circuit.

5. A signal processing circuit according to claim 1,

said object bit includes an isolated transition.

6. A signal processing circuit according to claim 1,

said object bit includes an isolated dibit.