A method of finding an unknown value from within a range of values is disclosed that divides the range into weighted subranges and then, beginning with an arbitrary search value within the range, performs a number of simple comparisons to determine the value for each subrange that will result in a match with the target value. This method can also detect those cases where the target value lies outside the range. In one embodiment, the method of finding an unknown value within a range of values is applied to impedance matching. In this embodiment, the output impedance of a pin on an integrated circuit is automatically matched to the impedance of the load connected to it. The output driver has a controllable impedance that can be adjusted within a specific range of impedances to match the external load impedance it is to drive.
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12. A method comprising:
comparing a pin circuit voltage to one-half of a source voltage to determine whether the pin circuit voltage is greater than one-half of the source voltage; and when the pin circuit voltage is not greater than one-half of the source voltage, incrementing a fine counter until the pin circuit voltage is greater than one-half of the source voltage so long as the fine counter is less than its maximum value, wherein the fine counter at least partially determines a variable impedance, wherein the variable impedance comprises a parallel arrangement of serially connected resistor-transistor pairs.
16. A method comprising:
comparing a pin circuit voltage to one-half of a source voltage to determine whether the pin circuit voltage is initially less than one-half of the source voltage; incrementing a coarse counter variable to a value greater than one-half of the source voltage when the pin circuit voltage is initially less than one-half of the source voltage; decrementing a fine counter variable until the value of the coarse counter variable and the fine counter variable equals one-half of the source voltage, when the pin circuit voltage is initially less than one-half of the source voltage; combining the coarse counter variable and the fine counter to create a control signal; and controlling a variable impedance using the control signal.
21. A method comprising:
comparing a pin circuit voltage to one-half of a source voltage to determine whether the pin circuit voltage is initially less than one-half of the source voltage; incrementing a coarse counter to a value greater than one-half of the source voltage, when the pin circuit voltage is initially less than one-half of the source voltage; decrementing a fine counter until the value of the coarse counter and the fine counter equals one-half of the source voltage, when the pin circuit voltage is initially less than one-half of the source voltage; and controlling a variable impedance using the coarse counter and the fine counter, wherein the variable impedance couples the source voltage to an external pin having the pin circuit voltage, and wherein the external pin is coupled to a signal source.
1. A computer program on a memory device, wherein the computer program, when executed on a microprocessor, comprises:
comparing the search value to a target value to determine whether the search value is initially less than the target value; incrementing the coarse counter to a value greater than the target value, when the search value is initially less than the target value; decrementing the fine counter until the value of the coarse counter and the fine counter equals the target value, when the search value is initially less than the target value, wherein the coarse counter and the fine counter represent the search value; decrementing the coarse counter to a value less than the target value, when the search value is initially not less than the target value; and incrementing the fine counter until the value of the coarse counter and the fine counter equals the target value, when the search value is initially not less than the target value.
11. A method for matching a search value to a target value in a range of values having a maximum value and a minimum value, in a system having a coarse counter and a fine counter representing the search value, the method comprising:
comparing the search value to the target value to determine whether the search value is initially less than the target value; incrementing the coarse counter to a value greater than the target value, when the search value is initially less than the target value; decrementing the fine counter until the value of the coarse counter and the fine counter equals the target value, when the search value is initially less than the target value; decrementing the coarse counter to a value less than the target value, when the search value is initially not less than the target value; and incrementing the fine counter until the value of the coarse counter and the fine counter equals the target value, when the search value is initially not less than the target value.
2. A method comprising:
comparing a pin circuit voltage to one-half of a source voltage to determine whether the pin circuit voltage is initially less than one-half of the source voltage, wherein the comparing further comprises receiving an external pin sense signal and receiving a voltage source sense signal at a voltage reduction circuit; incrementing a coarse counter to a value greater than one-half of the source voltage, when the pin circuit voltage is initially less than one-half of the source voltage; decrementing a fine counter until the value of the coarse counter and the fine counter equals one-half of the source voltage, when the pin circuit voltage is initially less than one-half of the source voltage; decrementing the coarse counter to a value less than the pin circuit voltage, when the pin circuit voltage is initially greater than one-half of the source voltage; and incrementing the fine counter until the value of the coarse counter and the fine counter equals one-half of the source voltage, when the pin circuit voltage is initially greater than one-half of the source voltage.
6. A method comprising:
comparing a pin circuit voltage to one-half of a source voltage to determine whether the pin circuit voltage is initially less than one-half of the source voltage, wherein the comparing further comprises receiving an external pin sense signal and receiving a voltage source sense signal at a voltage reduction circuit; incrementing a coarse counter variable to a value greater than one-half of the source voltage, when the pin circuit voltage is initially less than one-half of the source voltage; decrementing a fine counter variable until the value of the coarse counter variable and the fine counter variable equals one-half of the source voltage, when the pin circuit voltage is initially less than one-half of the source voltage; decrementing the coarse counter variable to a value less than the pin circuit voltage, when the pin circuit voltage is initially greater than one-half of the source voltage; and incrementing the fine counter variable until the value of the coarse counter variable and the fine counter variable equals one-half of the source voltage, when the pin circuit voltage is initially greater than one-half of the source voltage.
3. The method of
4. The method of
controlling a variable impedance with an output signal of the coarse counter and an output signal of the fine counter.
7. The method of
controlling a variable impedance with an output signal of the coarse counter and an output signal of the fine counter.
8. The method of
driving the pin circuit voltage to one-half the source voltage.
9. The method of
10. The method of
the metal-oxide-semiconductor field-effect transistor comprises a gate terminal, a source terminal, and a drain terminal, and wherein the output signal of the coarse counter and the output signal of the fine counter control the voltage between the gate terminal and the source terminal to control the impedance between the drain terminal and the source terminal.
13. The method of
when the pin circuit voltage is greater than one-half of the source voltage, decrementing a coarse counter until the pin circuit voltage is not greater than one-half of the source voltage so long as the coarse counter is greater than zero, wherein the coarse counter at least partially determines the variable impedance.
14. The method of
combining the coarse counter and the fine counter to create a control signal to control the variable impedance.
15. The method of
combining the coarse counter and the fine counter create a control signal to drive a pin circuit impedance equal to a signal source impedance.
17. The method of
18. The method of
19. The method of
20. The method of
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This application is a division of U.S. patent application Ser. No. 09/382,525 now U.S. Pat. No. 6,275,116, filed Aug. 25, 1999, the specification of which is incorporated herein by reference.
This invention relates to the field of information processing, and more particularly, to the matching of values in information systems.
Information processing applications must often find a value within a range of values. For example, a sorting system may organize discrete units of information into groups defined by numerical boundaries. Before assigning each discrete unit of information to a group, the relationship between each discrete unit of information and the numerical boundaries must be established. Defining these relationships often requires finding a value within a range of values. In some sorting systems, this is accomplished using a compute intensive sort algorithm in combination with a high performance microprocessor. Unfortunately, high performance microprocessors are expensive, and therefore not suitable for use in products directed to the consumer market.
An analog-to-digital (A/D) converter generates digital output information related to analog input information. The conversion process associated with one type of A/D converter requires manipulating discrete pieces of information, the on and off states of resistor ladder switches, in such a way that the final configuration of resistor ladder switches matches a value within a range of values. Modem A/D converters are designed to operate on a single chip and to function in a variety of end user applications, such as cellular telephones and video games. A single A/D converter design may be required to function in an application that requires eight, twelve, sixteen or more bits of resolution. Designers attempt to provide this flexibility in an AID converter by providing an on chip microprocessor. Unfortunately, the supplied microprocessor often has a limited instruction set, and operates at a low frequency, so the requirements for applications that must operate at both high frequency and high resolution, such as quickly matching a two byte value within a range of values, are difficult to meet.
Some control systems seek to drive a difference signal, which is the difference between an output information signal and an input signal, to zero in order to maintain a constant relationship between the input signal and the output information signal. This process of driving the difference signal to zero may require the identification of a value within a range of values.
In modem digital control systems, the control function is often performed by a microprocessor. In some systems designed primarily for high reliability, such as systems designed for use in satellites, high function may also be required. High function microprocessors tend to fail more often than low function microprocessors, so it is difficult to meet both requirements, and often a low function microprocessor is selected for a particular application. Unfortunately, the same algorithms and software that accomplish tasks on a high function microprocessor, such as identifying a value within a range of values, do not work on low function microprocessors.
For these and other reasons there is a need for the present invention.
The above-mentioned problems and other problems are addressed by the present invention and will be understood by one skilled in the art upon reading and studying the following specification. A method of finding an unknown value from within a range of values is disclosed that divides the range into weighted subranges and then, beginning with an arbitrary search value within the range, performs a number of simple comparisons to determine the value for each subrange that will result in a match with the target value. This method can also detect those cases where the target value lies outside the range.
In one embodiment, the method of finding an unknown value within a range of values is applied to impedance matching. In this embodiment, the output impedance of a pin on an integrated circuit is automatically matched to the impedance of the load connected to it. The output driver has a controllable impedance that can be adjusted within a specific range of impedances to match the external load impedance it is to drive.
In the following detailed description of the invention, reference is made to the accompanying drawings which form a part hereof, and in which are shown, by way of illustration, specific embodiments in which the invention may be practiced. The embodiments are intended to describe aspects of the invention in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and changes may be made without departing from the scope of the present invention. The following detailed description is not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims.
A method of finding an unknown value from within a range of values operates by dividing the range into weighted subranges. Beginning with an arbitrary search value within the range, the method performs a number of simple comparisons to determine the value for each subrange that will result in a match with the target value. This method can also detect those cases where the target value lies outside the range.
The first general step of the method is to define the allowable range and the subranges that will be used. The subranges are defined such that higher order subranges represent some multiple of the next lower order subrange. An example would be the use of the place order of digits in a number to define the subranges for ones, tens, hundreds, etc. In this example the ones subrange is the lowest order subrange and offers the finest resolution. Each higher order subrange is a multiple of the subrange that precedes it, offering a reduction in resolution as a trade off for a larger step size for use in searching for the target value. With the subranges defined, the unknown target becomes a reference to compare the search value against.
Depending on the results of an initial comparison, the search branches to either of two paths to determine the correct value for the highest order subrange needing adjustment in order to achieve a match condition. Upon successful completion of either path, a lower order subrange will be marked as the new highest order subrange for subsequent comparisons and the search continues by branching to the other path. The search alternates between the two paths until the lowest order subrange has been adjusted and a match has been achieved.
In the first path, the search value is greater than or not less than the target value. Beginning with the lowest order subrange, the subrange is set to its minimum value and the resulting new search value is compared against the target value. This process is repeated with each higher order subrange until a) the highest subrange is reached or b) the search value is no longer greater than the target value. If the search value is still greater than the target value when the highest order subrange is reached, then the highest order subrange is decremented until the search value is no longer greater than the target value or until the highest order subrange reaches its minimum value, whichever occurs first. In either case, the highest order subrange has been set to its correct value. If the search value becomes less than or no longer greater than the target value, the next lower subrange is marked as the new highest order subrange for subsequent comparisons and the search branches to a second path. If the search value becomes less than or no longer greater than the target value before the highest order subrange is reached, then all of the higher order subranges have been already set to their correct value. The subrange whose change caused the search value to no longer be greater than the target value is marked as the new highest order subrange and the search branches to the second path. If all subranges become set to their minimum values and the search value is still greater than the target value then an underflow condition has been detected and the search is ended.
In the second path, the search value is less than or not greater than the target value. Beginning with the lowest order subrange, set the subrange to its maximum value and compare the resulting new search value against the target. This process is repeated with each higher order subrange until a) the highest order subrange is reached or b) the search value is greater than or no longer less than the target value. If the search value is still less than the target value when the highest order subrange is reached, then the highest order subrange is incremented until either the search value is no longer less than the target value or the highest order subrange reaches its maximum value. Either of these stopping conditions is a result of the highest order subrange being set to its correct value. If the search value is no longer less than the target value, the next lower order subrange is marked as the new highest order subrange and the search branches to the first path. If the search value becomes greater than or not less than the target value before the highest order subrange is reached, then the subrange whose change caused this condition is marked as the new highest order subrange and the search branches to the first path. If all subranges become set to their maximum value and the search value is still less than the target value, then an overflow condition has been detected and the search is ended.
One embodiment of the algorithm 100 can generally be described with reference to FIG. 1. Initialization occurs at 102 where the lowest order subrange index LOS is set equal to zero and the number of subranges N is selected. The highest order subrange index HOS is set equal to N-1, or one less than the number of subranges, in 104. The search index i is set equal to the lowest order subrange index LOS at 106.
A search value is compared to a target value at 108. If the search value is greater than the target value, then the search proceeds along a first search path by comparing the search index i to the highest order subrange index HOS at 130. If the search index i is not equal to the highest order subrange index HOS, then the value of the subrange indexed by i is set to its minimum value and the search index i is incremented at 132. The new search value resulting from the operation at 132 is then compared to the target value at 134, and if the search value is greater than the target value then the comparison at 130 is performed again. The search will continue in this loop until the search index i is equal to the highest order subrange index HOS at 130 or until the search value is not greater than the target value at 134. If the search value is not greater than the target value at 134, then the control flows to 116 where the highest order subrange index HOS is set equal to the search index i.
If the search index i is equal to the highest order subrange index HOS at 130, then all the lower order subranges have been set to their minimum values and it is necessary to decrease the value of the highest order subrange until the search value is not greater than the target value. The search continues at 138 by comparing the value of subrange indexed by the search index i to its minimum value. If the value of the subrange is not equal to its minimum value, then the value of the subrange is decremented at 140. The new search value resulting from the operation at 140 is compared to the target value at 142. If the search value is not greater than the target value at 142, then the control flows back to the comparison at 138. If the search value is not greater than the target value at 142 then the correct value for the subrange indexed by the highest order subrange index HOS has been found and the control flows to 126.
If the subrange indexed by the search value i is equal to its minimum value at 138 then an underflow condition has been detected and the control flows to 144. This underflow results from the following conditions being met: 1) the highest order subrange being compared at 138 equals its minimum value, 2) the lower order subranges all equal their minimum values, 3) the search value is greater than the target value. Since the first two of these three conditions indicate that the search value is set to its minimum value, it is not possible to decrease the search value further to make it match the target value. From this point control flows to 148.
Returning focus to the original comparison at 108, if the search value is not greater than the target value, then the search proceeds along a second search path by comparing the search index i to the highest order subrange index HOS at 110. If the search index i is not equal to the highest order subrange index HOS, then the value of the subrange indexed by i is set to its maximum value and the search index i is incremented at 112. The new search value resulting from the operation at 112 is then compared to the target value at 114, and if the search value is not greater than the target value then the comparison at 110 is performed again. The search will continue in this loop until the search index i is equal to the highest order subrange index HOS at 110 or until the search value is greater than the target value at 114. If the search value is greater than the target value at 114, then the control flows to 116 where the highest order subrange index HOS is set equal to the search index i.
If the search index i is equal to the highest order subrange index HOS at 110, then all the lower order subranges have been set to their maximum values and it is necessary to increase the value of the highest order subrange until the search value is greater than the target value. The search continues at 118 by comparing the value of the subrange indexed by the search index i to its maximum value. If the value of the subrange is not equal to its maximum value, then the value of the subrange is incremented at 120. The new search value resulting from the operation at 120 is compared to the target value at 122. If the search value is not greater than the target value at 122, then the control flows back to the comparison at 118. If the search value is greater than the target value at 122 then the correct value for the subrange indexed by the highest order subrange index HOS has been found and the control flows to 126.
If the subrange indexed by the search value i is equal to its maximum value at 118 then an overflow condition has been detected and the search control flows to 124. This overflow results from the following conditions being met: 1) the highest order subrange being compared at 118 equals its maximum value, 2) the lower order subranges all equal their maximum values, 3) the search value is not greater than the target value. Since the first two of these three conditions indicate that the search value is set to its maximum value, it is not possible to increase the search value further to make it match the target value. From this point control flows to 148.
In the comparison at 126, if the highest order subrange HOS and the lowest order subrange index LOS are equal, then all the subranges have been set to the values that cause the search value to match the target value. From here the control flows to 148. If the highest order subrange index HOS does not equal the lowest order subrange index LOS at 126, then it is necessary to continue the search to find the correct setting for at least one lower order subrange. The control flows to 128 where the search index i is decremented and the highest order subrange index HOS is set equal to this new value of i, indexing the next lower subrange.
Setting the highest order subrange index HOS to a new value, either at 116 or at 128, marks the successful completion of the current search path control flows to 106 where the search index i is set equal to the lowest order subrange index LOS. Following this the search value is compared to the target value at 108. At the successful completion of the first path, the search value will not be greater than the target value so the control flows to the second path at 110. Likewise, at the completion of the second path, the search value will be greater than the target value so the control flows to the first path at 130. Thus the search alternates between the two search paths until a solution is obtained.
Once a solution has been found, or an underflow or overflow condition has been detected, control flows to 148. At this point the results of the search are stored and control flows to 104 in preparation for a new search to begin.
The embodiment described above has several advantages. First, it rapidly converges to the target value. Second, the individual operations map easily into the instruction set of inexpensive microprocessors, which makes this an attractive method of identifying a target value in a range of values in inexpensive consumer products.
The dynamic operation of one embodiment of a system embodying the method of FIG. 1 and described above is best understood by studying Tables 1-4 that follow.
Tables 1-4 show in detail the progress through a system embodying the method illustrated in the flowchart of
| TABLE 1 | ||
| Lowest Order Subrange (LOS) | ONES | |
| 2nd LOS (LOS+1) | TENS | |
| 3rd LOS (LOS+2) | HUNDREDS | |
| Highest Order Subrange (HOS) | THOUSANDS | |
| EXAMPLE #1 Initial Search Value > Target Value | ||
| Search Range: | 0000-9999 | |
| Initial Search | 4961 | |
| Value: | ||
| Target Value: | 0375 | |
| Beginning | Ending | |
| Search | Search | |
| Value | Value | Comments |
| Search > Target, branch to path #1 | ||
| 4961 | 4960 | LOS set to min. |
| 4960 | 4900 | LOS+1 set to min. |
| 4900 | 4000 | LOS+2 set to min. |
| 4000 | 3000 | Dec HOS |
| 3000 | 2000 | Dec HOS |
| 2000 | 1000 | Dec HOS |
| 1000 | 0000 | Dec HOS |
| Search < Target, HOS found, LOS+2 | ||
| becomes new HOS, branch to path #2 | ||
| 0000 | 0009 | LOS set to max |
| 0009 | 0099 | LOS+1 set to max. |
| 0099 | 0199 | Inc LOS+2 |
| 0199 | 0299 | Inc LOS+2 |
| 0299 | 0399 | Inc LOS+2 |
| Search > Target, LOS+2 found, LOS+1 | ||
| becomes new HOS, branch to path #l | ||
| 0399 | 0390 | LOS set to min. |
| 0390 | 0380 | Dec LOS+1 |
| 0380 | 0370 | Dec LOS+1 |
| Search < Target, LOS+1 found, LOS | ||
| becomes new HOS, branch to path #2 | ||
| 0370 | 0371 | Inc LOS |
| 0371 | 0372 | Inc LOS |
| 0372 | 0373 | Inc LOS |
| 0373 | 0374 | Inc LOS |
| 0374 | 0375 | Inc LOS |
| Search = Target, end. | ||
| TABLE 2 | ||
| Lowest Order Subrange (LOS) | ONES | |
| 2nd LOS (LOS+1) | TENS | |
| 3rd LOS (LOS+2) | HUNDREDS | |
| Highest Order Subrange (HOS) | THOUSANDS | |
| EXAMPLE #2 Initial Search Value <Target Value | ||
| Search Range: | 0000-9999 | |
| Initial Search | 1756 | |
| Value: | ||
| Target Value: | 2104 | |
| Beginning | Ending | |
| Search | Search | |
| Value | Value | Comments |
| Search < Target, branch to path #2 | ||
| 1756 | 1759 | LOS set to max. |
| 1759 | 1799 | LOS+1 set to max. |
| 1799 | 1999 | LOS+2 set to max. |
| 1999 | 2999 | Inc HOS |
| Search > Target, HOS found, LOS+1 | ||
| becomes new HOS, branch to path #1 | ||
| 2999 | 2990 | LOS set to min. |
| 2990 | 2900 | LOS+1 set to min. |
| 2900 | 2800 | Dec LOS+2 |
| 2900 | 2700 | Dec LOS+2 |
| 2900 | 2600 | Dec LOS+2 |
| 2900 | 2500 | Dec LOS+2 |
| 2900 | 2400 | Dec LOS+2 |
| 2900 | 2300 | Dec LOS+2 |
| 2900 | 2200 | Dec LOS+2 |
| 2900 | 2100 | Dec LOS+2 |
| Search < Target, LOS+2 found, LOS+1 | ||
| becomes new HOS, branch to path #2 | ||
| 2100 | 2109 | LOS set to max. |
| Search > Target, LOS+1 found, LOS | ||
| becomes new HOS, branch to path #1 | ||
| 2109 | 2108 | Dec LOS |
| 2108 | 2107 | Dec LOS |
| 2107 | 2106 | Dec LOS |
| 2106 | 2105 | Dec LOS |
| 2105 | 2104 | Dec LOS |
| Search = Target, end. | ||
| TABLE 3 | ||
| Lowest Order Subrange (LOS) | ONES | |
| 2nd LOS (LOS+1) | TENS | |
| 3rd LOS (LOS+2) | HUNDREDS | |
| Highest Order Subrange (HOS) | THOUSANDS | |
| EXAMPLE #3 Target Value < Min Range Value | ||
| Search Range: | 10000-4999 | |
| Initial Search | 4961 | |
| Value: | ||
| Target Value: | 0375 | |
| Beginning | Ending | |
| Search | Search | |
| Value | Value | Comments |
| Search > Target, branch to path #1 | ||
| 4961 | 4960 | LOS set to min. |
| 4960 | 4900 | LOS+1 set to min. |
| 4900 | 4000 | LOS+2 set to min. |
| 4000 | 3000 | Dec HOS |
| 3000 | 2000 | Dec HOS |
| 2000 | 1000 | Dec HOS |
| Search at bottom of range. | ||
| Search > Target, UNDERFLOW, end. | ||
| TABLE 4 | ||
| Lowest Order Subrange (LOS) | ONES | |
| 2nd LOS (LOS+1) | TENS | |
| 3rd LOS (LOS+2) | HUNDREDS | |
| Highest Order Subrange (HOS) | THOUSANDS | |
| EXAMPLE #4 Target Value > Max Range Value | ||
| Search Range: | 10000-4999 | |
| Initial Search | 1756 | |
| Value: | ||
| Target Value: | 5104 | |
| Beginning | Ending | |
| Search | Search | |
| Value | Value | Comments |
| Search < Target, branch to path #1 | ||
| 1756 | 1759 | LOS set to max. |
| 1759 | 1799 | LOS+1 set to max. |
| 1799 | 1999 | LOS+2 set to max. |
| 1999 | 2999 | Inc HOS |
| 2999 | 3999 | Inc HOS |
| 3999 | 4999 | Inc HOS |
| Search at top of range. | ||
| Search < Target, OVERFLOW, end. | ||
The present invention has practical applications in many types of electronic systems. In one application, the present invention may be embodied in memory devices such as static random access memories (SRAM's), as part of a memory package such as single in line memory modules (SIMM's) or dual in line memory modules (DIMM's). As additional SIMM's or DIMM's are added to motherboards of computer systems, the characteristic impedance of the memory bus may change. The present invention allows for the adaptation to changes in the impedance on a memory bus when new memory is added to or removed from the bus by dynamically matching the bus driver impedance with the resulting bus impedance.
Referring to
Signal line 10 and signal line 20 are transmission devices capable of carrying electronic signals. For example, signal line 10 and signal line 20 can be signal carrying lines in an integrated circuit or a memory device, a conductive wire, a wiring pattern on a system board, a strip line, or a coaxial cable. In addition, signal line 10 and signal line 20 need not be the same type of transmission device, nor need they exist in the same electronic subsystem. For example, signal line 10 can be a signal carrying line in an integrated circuit, while signal line 20 can be a coaxial cable connected to the signal carrying line in the integrated circuit.
Controllable impedance 25 is an electronic device having an impedance or a resistance that can be controlled. In one embodiment, controllable impedance 25 comprises a plurality of parallel resistor-transistor pairs. The parallel resistor-transistor pairs define a resistance ladder, and by switching on a transistor in one of the resistor-transistor pairs, a resistor is added to the resistance ladder. After the first resistor is added to the ladder, adding additional resistors to the resistor ladder by turning on a transistor decreases the resistance of the controllable impedance. A parallel arrangement of resistor-transistor pairs is shown in FIG. 2C and is described in more detail below.
In an alternate embodiment, controllable impedance 25 comprises a transistor that has a controllable impedance or resistance. For example, a metal-oxide semiconductor (MOSFET) transistor is an electronic device that has a resistance that can be controlled.
Voltage source 5 can be selected to provide an appropriate value for controllable impedance 25. If controllable impedance 25 requires a positive voltage source to operate, then a positive voltage is selected for voltage source 5. If controllable impedance 25 requires a negative voltage source to operate, then a negative voltage is selected for voltage source 5. In addition voltage source 5 can be powered from a source of voltage, which is often referred to as a system voltage and designated as VCC or VDD.
Impedance matching system 1 ensures that information signals originating on signal line 10 are not reflected back along signal line 10 as they are transmitted to signal line 20. Controllable impedance 25 is dynamically changed to match the impedance of signal line 10 to the impedance of signal line 20. This dynamic matching eliminates reflections at the point where signal line 10 is connected to signal line 20.
Referring to
Variable impedance 140, in one embodiment of the present invention, is a metal-oxide-semiconductor field-effect transistor (MOSFET), which is controlled by the control system 150 to adjust the impedance on input-output (I/O) pin 110. Both n-type and p-type metal-oxide semiconductor field-effect transistors are suitable for use in connection with the present invention, and can be configured with an appropriate voltage source, either positive or negative.
The relationship between the drain-to-source voltage, VDS 225, and the drain current, ID 220, of
Variable impedance 140, in an alternate embodiment of the present invention, is a parallel arrangement of serially connected resistor-transistor pairs coupling VSOURCE voltage 105 to external pin 110. Those skilled in the art will recognize that the resistance of the parallel arrangement of the serially connected resistor-transistor pairs is controlled by switching each transistor on or off in order to either include the resistor in the circuit or exclude the resistor from the circuit.
Referring to
Referring again to
Referring again to
Those skilled in the art will recognize that, in another embodiment of the present invention, a microprocessor can be substituted for state logic system 315, coarse counter 320, and fine counter 325. The flow diagram of FIG. 4A and
Referring to FIG. 4A and
The operation of the flow diagram of FIG. 4A and
At decision block 410, VPIN is compared to VCC/2. If the pin voltage is greater than VCC/2, then fine counter 325 is set to zero. If VPIN is not greater than VCC/2, then fine counter 325 is set to its maximum value.
Assuming that VPIN is greater than VCC/2, the algorithm is prepared to consider executing branch 415 and branch 420. For VPIN greater than VCC/2, the strategy of the algorithm in branch 415 and branch 420 is to decrement coarse counter 320 until VPIN is less than VCC/2, and to then increment fine counter 325 until VPIN equals VCC/2. When VPIN equals VCC/2, the pin circuit impedance matches the signal source impedance. However, if after zeroing fine counter 325, VPIN is not greater than VCC/2, then coarse counter 320 need not be adjusted and only fine counter 325 is adjusted, incremented until it reaches its maximum value or until VPIN equals VCC/2.
Assuming that VPIN is not greater than VCC/2, the algorithm is prepared to consider executing branch 425 and branch 430. For VPIN not greater than VCC/2, the strategy of the algorithm in branch 425 and branch 430 is to increment coarse counter 320 until VPIN is greater than VCC/2 and to then decrement fine counter 325 until VPIN equals VCC/2. When VPIN equals VCC/2, the pin circuit impedance matches the signal source impedance. However, if after setting fine counter 325 to all ones, VPIN is greater than VCC/2, then coarse counter 320 need not be adjusted and only fine counter 325 is adjusted, decremented until it reaches its minimum value or until VPIN equals VCC/2.
The present invention has practical applications in many types of electronic systems. In one application, the present invention may be embodied in memory devices such as static random access memories (SRAM's), as part of a memory package such as single in line memory modules (SIMM's) or dual in line memory modules (DIMM's). As additional SIMM's or DIMM's are added to motherboards of computer systems, the characteristic impedance of the memory bus may change. The present invention allows for the adaptation to changes in the characteristic impedance on a memory bus when new memory is added to or removed from the bus by dynamically matching the bus driver impedance with the resulting bus impedance.
Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement which is calculated to achieve the same purpose may be substituted for the specific embodiment shown. This application is intended to cover any adaptations or variations of the present invention. Therefore, it is manifestly intended that this invention be limited only by the claims and the equivalents thereof.
Porter, John D., Weber, Larren Gene, Thompson, William N.
| Patent | Priority | Assignee | Title |
| 7170364, | Oct 24 2001 | Realtek Semiconductor Corp. | Impedance matching circuit with automatic adjustment and method thereof |
| 7724564, | May 02 2008 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Capacitive divider sensing of memory cells |
| 8194475, | May 02 2008 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Capacitive divider sensing of memory cells |
| Patent | Priority | Assignee | Title |
| 3805028, | |||
| 5095231, | Jul 26 1989 | CSELT - Centro Studi e Laboratori Telecomunicazioni S.p.A. | Automatic system for adjusting the output impedance of fast CMOS drivers |
| 5134311, | Jun 07 1990 | MILAN JANKOVIC | Self-adjusting impedance matching driver |
| 5296756, | Feb 08 1993 | Self adjusting CMOS transmission line driver | |
| 5459440, | Apr 20 1993 | Madge Networks Limited | Automatic impedance matching with potential monitoring means |
| 5606275, | Sep 05 1995 | SHENZHEN XINGUODU TECHNOLOGY CO , LTD | Buffer circuit having variable output impedance |
| 5666078, | Feb 07 1996 | International Business Machines Corporation | Programmable impedance output driver |
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