In one aspect, a method for charge recovery in dynamic circuitry includes discharging a dynamic node during an evaluation interval by input circuitry coupled to the dynamic node responsive to one or more input signals. The discharging includes transferring the charge from the dynamic node to a capacitor during the evaluation time interval. The dynamic node is charged during a precharge interval by a voltage source and precharge timing circuitry coupled to the dynamic node responsive to a precharge signal. The charging includes transferring the charge from the capacitor back to the dynamic node.
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16. A method for charge recovery dynamic circuitry, the method comprising the steps of: a) discharging a dynamic node of first dynamic circuitry by input circuitry for the dynamic circuitry, wherein the discharging includes transferring charge from the dynamic node to a dynamic node of predecessor dynamic circuitry during an evaluation interval of the first dynamic circuitry; and
charging the dynamic node of the first dynamic circuitry during a precharge interval of the first dynamic circuitry, wherein the charging includes transferring charge from a dynamic node of successor dynamic circuitry to the dynamic node of the first dynamic circuitry during the precharge interval for the first dynamic circuitry.
1. dynamic circuitry comprising:
a dynamic node; precharge circuitry coupled to the dynamic node and to a voltage source for charging the dynamic node during a precharge interval responsive to a precharge signal; input circuitry coupled to the dynamic node for selectively discharging the dynamic node during an evaluation interval responsive to one or more input signals; and charge recovery circuitry coupled to the dynamic node for selectively recycling charge to the dynamic circuitry, wherein the charge recovery circuitry comprises a capacitor and circuitry for controlling transfer of charge from the dynamic node to the capacitor during the evaluation time interval and from the capacitor back to the dynamic node during the precharge interval.
11. A method for charge recovery in dynamic circuitry, the method comprising the steps of:
a) discharging a dynamic node during an evaluation interval by input circuitry coupled to the dynamic node responsive to one or more input signals, wherein the discharging includes transferring charge from the dynamic node to a capacitor during the evaluation interval; and b) charging the dynamic node during a precharge interval by precharge circuitry responsive to a precharge signal, the precharge circuitry being coupled to the dynamic node and a voltage source, wherein the charging of the dynamic node includes transferring charge from the capacitor back to the dynamic node during the precharge interval, wherein the dynamic circuitry comprises circuitry for controlling transfer of charge having a first transistor interposed between the input circuitry and the capacitor, and wherein step a) comprises the step of discharging the dynamic node through the first transistor to the capacitor during the evaluation interval.
2. The dynamic circuitry of
3. The dynamic circuitry of
4. The dynamic circuitry of
5. The dynamic circuitry of
6. The dynamic circuitry of
7. The dynamic circuitry of
8. The dynamic circuitry of
9. The dynamic circuitry of
10. The dynamic circuitry of
12. The method of
charging the dynamic node from the capacitor through the second transistor during a first portion of the precharge interval; and discharging the capacitor to ground from the anode through the third transistor during a second portion of the precharge interval.
13. The method of
14. The method of
15. The method of
17. The method of
18. The method of
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1. Field of the Invention
The present invention relates to dynamic logic circuits, and more particularly to dynamic logic circuits having circuitry for reduced power consumption.
2. Related Art
Due to its speed, it is well known to use dynamic circuitry for high-performance applications.
More specifically, during the phase of clock 115 when the clock signal is low, PFET 101 in timing circuitry 120 is turned on and NFET 108 is turned off, which pulls dynamic node 150 up to Vdd. Then during the evaluation phase, that is, during the phase of clock 115 when the clock signal is high, PFET 101 is turned off and NFET 108 is turned on, so that the dynamic node 150 may be selectively pulled down to a low voltage through the NFET's 110 through 107 of input circuitry 122, depending on the state of the inputs on the gates 110 through 113.
The dynamic circuit 100 of
The dynamic circuit 100 also has keeper circuitry 126 coupled to the output 114, Vdd, and the dynamic node 150 for keeping the dynamic node at the precharged state during the evaluation phase despite leakage through the input circuitry 122 and the foot device 108 if none of the inputs are active.
Conventionally, dynamic logic circuits have not been as widely used as have static logic circuits in applications requiring low-power consumption. However, there is a current trend requiring higher performance for embedded processors in applications such as personal digital assistants, cell phones, electronic books, watches, etc. This is particularly brought on by the demand for rendering of images by such devices, such as for Internet browsers. The embedded processors in these applications are frequently battery powered, so there is an increasing need for reduced power consumption in dynamic logic circuits.
The foregoing need is addressed in the present invention, according to which a dynamic circuit includes charge recovery circuitry for controlling the circuitry to reduce power consumption.
More particularly, the dynamic circuit includes a dynamic node and precharge timing circuitry coupled to the dynamic node and to a voltage source for driving the node to a high voltage state during a precharge interval responsive to a precharge signal. The dynamic circuit also includes input circuitry coupled to the dynamic node for selectively discharging the dynamic node to a low voltage state during an evaluation interval responsive to one or more input signals. Charge recovery circuitry of the dynamic circuit has a capacitor and circuitry for controlling transfer of charge from the dynamic node to the capacitor during the evaluation time interval and from the capacitor back to the dynamic node during the pre charge time interval.
In a method form, a method for charge recovery in dynamic circuitry includes discharging a charge from a dynamic node during an evaluation interval by input circuitry coupled to the dynamic node responsive to one or more input signals. The discharging includes transferring the charge from the dynamic node to a capacitor during the evaluation time interval. Then, during a precharge interval the dynamic node is charged to a higher voltage state by precharge timing circuitry coupled to the dynamic node and to a voltage source responsive to a precharge signal. The charging includes transferring the charge from the capacitor to the dynamic node during the precharge interval.
In an alternative method form, the method includes discharging a charge from a dynamic node of a first dynamic circuit during an evaluation interval by input circuitry for the dynamic circuit. The discharging includes transferring the charge from the dynamic node of the first dynamic circuit, by charge recovery circuitry, to a dynamic node of a predecessor dynamic circuit during the evaluation time interval of the first dynamic circuit. The dynamic node of the first dynamic circuit is charged to a higher voltage state during a precharge interval of the first dynamic circuit by precharge timing circuitry for the first dynamic circuit. The charging includes transferring charge from the dynamic node of the a successor dynamic circuit to the dynamic node of the first dynamic circuit during the precharge interval for the first dynamic circuit.
The present invention is advantageous because by recovering charge in the circuitry power consumption is reduced. Other objects and advantages of the invention will become apparent upon reading the following detailed description and upon reference to the accompanying drawings.
The claims at the end of this application set out novel features which applicants believe are characteristic of the invention. The invention, a preferred mode of use, further objectives and advantages, will best be understood by reference to the following detailed description of an illustrative embodiment read in conjunction with the accompanying drawings.
Referring now to
Referring now to
Next, the evaluation signal 315, applied to the gate 215, is deasserted, turning off NFET 208. The endeval signal 334, applied to the gate 234 is also asserted, turning on NFET 232. This discharges the signal 350 on the dynamic node 250 more directly to ground, that is, through NFET 232 rather than through capacitor 230. Next, at the evaluation phase ends with the end evaluation signal 315 and the input signals 310, etc. being de asserted.
Then the precharge phase is begun when the recycle signal 336, applied to the gate 236, is de asserted, turning on PFET 233, which dumps charge from the capacitor 230 back to the dynamic node 250, thereby driving the signal 350 at least partially back to Vdd. It should be understood that this recycle operation is only necessary if the dynamic node signal 350 has been discharged during the evaluation stage, because otherwise there would have been no charge transfer to the capacitor 230 during evaluation and there will be no substantial charge on the capacitor 230 to recover. Therefore, in an embodiment the recycle signal 336 is only the asserted on the condition that the dynamic node signal 350 was discharged.
Next, the recycle signal 336 is reasserted, turning off PFET 233. Then, to complete the precharge phase, the reset signal 316, applied to the gate 216, is deasserted, turning on PFET 201, which completes the driving of the dynamic node signal 350 on node 250 to Vdd. At the same time, the zero capacitor signal 335, applied to the gate 235, is asserted, turning on NFET 231, which shorts the anode of capacitor 230 to ground, thereby insuring that the capacitor 230 is fully discharged.
The amount of charge recovered by the capacitor 230 returning charge to the dynamic node 230 depends upon the size of the capacitor relative to the size of the capacitance of the circuitry connected to the dynamic node, and upon timing, such as timing of the evaluation signal 315 and the recycle signal 336. For example, if the capacitance of capacitor 230 is five times that of the dynamic node 250 then a maximum of about 14% of the charge is recoverable. If the capacitance of capacitor 230 is the same as that of the dynamic node 250 then a maximum of about 25% of the charge is recoverable. Charge recovery considerations thus suggest that a relatively small capacitor 230 is best. However, increasing the capacitance of capacitor 230 relative to that of the dynamic node 250 increases noise margin and speed of operation of the circuit 250. Therefore, it is generally preferred that the capacitor 230 be relatively large in comparison to the dynamic node 250 capacitance, and there is all the more need to discharge the capacitor by NFET 231 at the end of the precharge phase.
Referring now to
The circuitry 420 also includes first second and third NAND gates 445 through 447, the outputs of which provide respective control signals recycle 336, evaluation 315, and zero capacitor 335 applied to respective gates 436, 415, and 435. The output node 414 is also coupled to first inputs of a NAND gate 445 and a NAND gate 446. A second input of NAND gate 445 is coupled to the output of time delay circuit 441. A second input of NAND gate 446 is coupled to the output of time delay circuit 443. A first input of NAND gate 447 is coupled to the output of time delay circuit 442. A second input of NAND gate 447 is coupled to the output of time delay circuit 443.
These signals, which correspond to the signals as shown in the timing diagram of
Referring now to
Identity and operation of circuitry and elements in the dynamic logic circuitry 500 correspond to that of similarly numbered circuitry and elements of the dynamic logic circuitry 200 of FIG. 2. For example, PFET 201 of
Since predecessor dynamic circuitry 580 is dual rail, during an evaluation interval either its output, out 583, or its complementary output, out_b 584, will be high (and the corresponding dynamic node 581 or 582 will be low). If out 583 is high, this will turn on pass gate 560. If, on the other hand, out_b is high, this will turn on pass gate 561. During the evaluation phase of dynamic circuitry 500, charge from the dynamic node 550 needs to be sunk. If out 583 is high, the corresponding dynamic node 581 will be low, and charge from the dynamic node 550 will be sunk to dynamic node 581 when NFET 508 is turned on. If out_b 584 is high, the corresponding dynamic node 582 will be low, and charge from the dynamic node 550 can be sunk to dynamic node 582 when NFET 508 is turned on. This transfer of charge from dynamic node 550 to either dynamic node 581 or 582 initiates the precharge of 581 or 582.
During the precharge phase of dynamic circuitry 500, charge from the dynamic node 550 needs to be restored. This restoring of charge for dynamic circuitry 500 occurs at least partly by transfer of charge from a dynamic node of successor dynamic circuitry 590, just as described above for dynamic circuitry 500 transferring charge to its predecessor circuitry 580.
The description of the present embodiment has been presented for purposes of illustration, but is not intended to be exhaustive or to limit the invention to the form disclosed. Many additional aspects, modifications and variations are also contemplated and are intended to be encompassed within the scope of the following claims. For example, charge recycling PFET's 233 and 433 may be replaced by NFET's with a corresponding change in polarity of the control signals driving their gates.
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