A method and apparatus are provided for laser fuseblow protection in transistors, such as silicon-on-insulator (SOI) transistors. The transistors are connected to a fuse. A pair of diodes are connected in series between a high supply and ground. A common connection of the series connected pair of diodes is connected to a common connection of the fuse and transistors. A charge is shunted to the high supply or ground by the pair of diodes with a first voltage a set value above the high supply and a second voltage a set value below the ground. A pair of protection diodes are provided on each side of the fuse with transistors. The transistors are either connected to one side of the fuse or to both sides of the fuse.
|
2. Apparatus for laser fuseblow protection in transistors connected to a fuse comprising:
a pair of diodes connected in series between a high supply and ground; a common connection of said series connected pair of diodes connected to a connection of the fuse and the transistors; said pair of diodes shunting a charge to said high supply or ground with a first voltage a set value above said high supply and a second voltage a set value below said ground; and the transistors are fuse sense transistors for sensing the presence or absence of the fuse.
1. Apparatus for laser fuseblow protection in transistors connected to a fuse comprising:
a pair of diodes connected in series between a high supply and ground; a common connection of said series connected pair of diodes connected to a connection of the fuse and the transistors; said pair of diodes shunting a charge to said high supply or ground with a first voltage a set value above said high supply and a second voltage a set value below said ground; one side of the fuse being connected to ground; and a second pair of diodes connected in series between a high supply and ground; and a common connection of said series connected second pair of diodes connected to a connection of the fuse and ground.
|
This application is a divisional application of Ser. No. 09/588,247 filed on Jun. 6, 2000, now U.S. Pat. No. 6,509,236.
The present invention relates to a method and apparatus for laser fuseblow protection in silicon-on-insulator (SOI) transistors.
Silicon-on-insulator (SOI) technology is an enhanced silicon technology currently being utilized to increase the performance of digital logic circuits. Utilizing SOI technology designers can increase the speed of digital logic integrated circuits while reducing their overall power consumption. These advances in technology will lead to the development of more complex and faster computer integrated circuits that operate with less power.
As shown in
In a conventional, bulk silicon process, the transistors are built in the top surface of a relatively thick mass of silicon. During a laser fuseblow process, energy that is imparted to the transistors has this thick silicon in which to dissipate this energy. SOI transistors are built on the thin layer of silicon placed on top of a thicker insulator as shown in FIG. 1. Damage to the SOI transistor devices can occur due to the decreased ability to dissipate the resulting charge build up form the laser fuseblow process in the thin layer of silicon.
A need exists for a mechanism for protecting SOI transistors from an excess voltage and charge that can be built up during a laser fuseblow process.
A principal object of the present invention is to provide a method and apparatus for laser fuseblow protection in silicon-on-insulator (SOI) transistors. Other important objects of the present invention are to provide such a method and apparatus for laser fuseblow protection in silicon-on-insulator (SOI) transistors substantially without negative effect and that overcome many of the disadvantages of prior art arrangements.
In brief, a method and apparatus are provided for laser fuseblow protection in transistors, such as silicon-on-insulator (SOI) transistors. The transistors are connected to a fuse. A pair of diodes are connected in series between a high supply and ground. A common connection of the series connected pair of diodes is connected to a common connection of the fuse and transistors. A charge is shunted to the high supply or ground by the pair of diodes with a first voltage a set value above the high supply and a second voltage a set value below the ground.
In accordance with features of the invention, a pair of protection diodes are provided on each side of the fuse with transistors. The transistors are either connected to one side of the fuse or to both sides of the fuse.
The present invention together with the above and other objects and advantages may best be understood from the following detailed description of the preferred embodiments of the invention illustrated in the drawings, wherein:
Having reference now to the drawings, in
In very large scale integrated (VLSI) chips, it is common to have fuses, such as fuse 210 that can be programmed for various reasons. Among these reasons include invoking redundant elements in memory arrays for repairing failing locations or programming identification information. A common method of building and programming such fuses 210 is to build a thin metal wire fuse near the top surface of the chip. The fuse 210 can be programmed by selectively deleting the thin metal using a laser (not shown). The thin wire is connected to a circuit that can sense whether the fuse remains or has been deleted. The laser imparts energy that vaporizes the metal to create an open circuit. The circuit that senses the presence or absence of a fuse 210 must be able to withstand the energy of the laser fuseblow process.
In accordance with features of the preferred embodiment, the problem of protecting the SOI transistors 202, 204, 206 and 208 connected to fuse 210 to withstand the energy of the laser fuseblow process is solved by a plurality of protection diodes 212, 214, 216 and 218. Protection diodes 212, 214, 216 and 218 of the preferred embodiment are designed for protecting the SOI transistors 202, 204, 206 and 208 directly connected to fuse 210.
There are many designs or arrangements for sensing whether a fuse 210 has been blown or not. In all cases transistors are directly connected to fuse 210 either on one side or both sides of the fuse and are prone to damage. In
By designing the protection diodes 212, 214, 216 and 218 to each power supply on each side of the fuse 210 with transistors 202 and 204, and transistors 206 and 208, the transistors 202, 204, 206 and 208 are protected from the otherwise destructive voltages that could damage them. The protection diodes 212, 214, 216 and 218 will shunt the charge to either the ground or high supply if the voltage rises above a diode threshold voltage or around 0.7 Volt above the high supply or drops lower than 0.7 Volt below the ground supply. Transistors are typically designed to withstand these voltages that are only 0.7 Volt above or below typical or expected values during functional operation.
Referring to
By designing the protection diodes 312, 314, 316 and 318 to each power supply on each side of the fuse 310 with transistors 302 and 304, the transistors 302 and 304 are protected from the otherwise destructive voltages that could damage them. The protection diodes 312, 314, 316 and 318 will shunt the charge to either the ground or high supply if the voltage rises above a diode threshold voltage or around 0.7 Volt above the high supply or drops lower than 0.7 Volt below the ground supply.
While the present invention has been described with reference to the details of the embodiments of the invention shown in the drawing, these details are not intended to limit the scope of the invention as claimed in the appended claims.
Aipperspach, Anthony Gus, Christensen, Todd Alan
Patent | Priority | Assignee | Title |
7098491, | Dec 30 2003 | Taiwan Semiconductor Manufacturing Company, Ltd. | Protection circuit located under fuse window |
7804317, | Oct 19 2006 | Advanced Micro Devices, Inc. | Test device for determining charge damage to a transistor |
9318433, | Apr 16 2013 | Fuji Electric Co., Ltd. | Semiconductor device |
Patent | Priority | Assignee | Title |
5986862, | Dec 31 1996 | MagnaChip Semiconductor, Ltd | Electrostatic discharge protection circuit |
6262919, | Apr 05 2000 | Elite Semiconductor Memory Technology Inc. | Pin to pin laser signature circuit |
Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
Aug 09 2001 | International Business Machines Corporation | (assignment on the face of the patent) | / |
Date | Maintenance Fee Events |
Sep 26 2006 | M1551: Payment of Maintenance Fee, 4th Year, Large Entity. |
Jan 03 2011 | REM: Maintenance Fee Reminder Mailed. |
May 27 2011 | EXP: Patent Expired for Failure to Pay Maintenance Fees. |
Date | Maintenance Schedule |
May 27 2006 | 4 years fee payment window open |
Nov 27 2006 | 6 months grace period start (w surcharge) |
May 27 2007 | patent expiry (for year 4) |
May 27 2009 | 2 years to revive unintentionally abandoned end. (for year 4) |
May 27 2010 | 8 years fee payment window open |
Nov 27 2010 | 6 months grace period start (w surcharge) |
May 27 2011 | patent expiry (for year 8) |
May 27 2013 | 2 years to revive unintentionally abandoned end. (for year 8) |
May 27 2014 | 12 years fee payment window open |
Nov 27 2014 | 6 months grace period start (w surcharge) |
May 27 2015 | patent expiry (for year 12) |
May 27 2017 | 2 years to revive unintentionally abandoned end. (for year 12) |