An asymmetric cell and bit design for an MRAM device. The design is asymmetrical with respect to the easy-axis of the cell and has a centroid displaced from bit center along the hard-axis of the cell. This asymmetry is large enough so that manufacturing process variations do not substantially change the switching fields of the bits. In addition, the asymmetry causes the ends of the bits to align in opposite directions in small half-select fields and parallel to each other at large half-select fields, which increases the difference in the switching fields between selected and unselected bits. The combined effect of these two characteristics results in increased bit yield (relative to similarly sized symmetric bits) due to a smaller overlap between selected and unselected bit switching distributions.
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1. A magnetic memory cell comprising:
a first magnetic layer having a pinned magnetization direction; a second magnetic layer having a switchable magnetization direction; and a non-magnetic layer between said first and second magnetic layers, wherein said cell comprises a hard-axis and an easy-axis, an intersection of the hard-axis and easy-axis defining a center of said cell, and at least said second magnetic layer has a centroid that is displaced along the hard-axis from the center.
7. A magnetic memory device comprising:
a plurality of magnetic memory cells organized into an array of rows and columns, each magnetic memory cell comprising: a first magnetic layer having a pinned magnetization direction; a second magnetic layer having a switchable magnetization direction; and a non-magnetic layer between said first and second magnetic layers; wherein said cell comprises a hard-axis and an easy-axis, an intersection of the hard-axis and easy-axis defining a center of said cell, and at least said second magnetic layer has a centroid that is displaced along the hard-axis from the center.
22. A method of storing information in a magnetic memory cell, said method comprises the steps of:
providing a memory cell having a hard-axis and an easy-axis of magnetization, an intersection of the hard-axis and easy-axis defining a center of said cell, the memory cell comprising a magnetic field that is aligned with the easy-axis in a first direction, the memory cell having a centroid that is displaced along the hard-axis from the center; applying a half-select magnetic field to the cell; and applying a switching magnetic field to the cell, said switching magnetic field causing the magnetic to switch from the first direction to the second direction.
14. A processor system comprising:
a processor; and a magnetic memory device coupled to said processor, said magnetic memory device comprising a plurality of magnetic memory cells organized into an array of rows and columns, each magnetic memory cell comprising: a first magnetic layer having a pinned magnetization direction; a second magnetic layer having a switchable magnetization direction; and a non-magnetic layer between said first and said second magnetic layers; wherein said cell comprises a hard-axis and an easy-axis, an intersection of the hard-axis and easy-axis defining a center of said cell, and at least said second magnetic layer has a centroid that is displaced along the hard-axis from the center.
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This application claims the benefit of U.S. Provisional Patent Application No. 60/331,421, filed on Nov. 15, 2001, the entire contents of which are incorporated herein by reference.
The present invention relates generally to memory devices and, more particularly, to an asymmetric cell and bit design for improving the bit yield of a magnetoresistive random access memory (MRAM) device.
Integrated circuit designers have always sought the ideal semiconductor memory: a device that is randomly accessible, can be written or read very quickly, is non-volatile, but indefinitely alterable, and consumes little power. MRAM technology has been increasingly viewed as offering all these advantages.
An MRAM device typically includes an array of magnetic memory cells. A typical magnetic memory cell has a structure which includes magnetic layers separated by a non-magnetic layer. Magnetic vectors in one magnetic layer, typically referred to as the pinned layer, are magnetically fixed or pinned in one direction. The magnetic vectors of the other magnetic layer, often referred to as the storage or sense layer, are not fixed so that its magnetization direction is free to switch between "parallel" and "anti-parallel" states relative to the pinned layer. In response to the parallel state, the magnetic memory cell will have a low resistance state. Conversely and in response to the anti-parallel state, the magnetic memory cell will have a high resistance state. The MRAM device associates these two resistance states with either a logical "1" or a "0" bit value.
A logical "1" or "0" is usually written into the magnetic memory cell by applying external magnetic fields (via an electrical current) that rotate the magnetization direction in the storage layer. Typically, the orientation of magnetization in the storage layer aligns along an axis known as the easy-axis. The external magnetic fields are applied to flip the orientation of magnetization in the storage layer along its easy-axis to either the parallel or anti-parallel orientation with respect to the orientation of magnetization in the pinned layer depending on the desired logic state.
MRAM devices usually include an array of row lines and column lines that are used to apply the external magnetic fields to the magnetic memory cells during writing. The magnetic memory cells are usually located at intersections of the row lines and column lines. A selected magnetic memory cell is usually written by applying electrical currents to the particular row and column lines that intersect at the selected magnetic memory cell.
The magnetic field aligned to the easy-axis is referred to herein as the easy-axis write field while the other field is referred to as the hard-axis write field. It is desired that only the selected magnetic memory cell receives both the easy-axis and hard-axis write fields. Each write field is commonly referred to as a half-select field because individually they cannot switch the contents of cell. In practice, however, the hard-axis write field is usually referred to as the half-select field, while the easy-axis write field is referred to as the switching field.
The bit stored in the selected memory cell is referred to herein as a "selected bit." AR of the remaining memory cells coupled to the column line or row line, which are not the desired selected cell are referred to herein as "unselected cells" and their corresponding bits are "unselected bits." The unselected cells coupled to the particular column line usually receive only the easy-axis write field. Similarly, the unselected cells coupled to the particular row line usually receive only the hard-axis write field. The magnitudes of the easy-axis and hard-axis write fields are usually chosen to be high enough so that the stored bit in the selected magnetic memory cell switches its logic state, but are low enough so that the stored bits in the unselected memory cells, that are subject to only one of the write fields, do not switch. An undesirable switching of a stored bit in an unselected magnetic memory cell (i.e., one that receives only one of the write fields) is commonly referred to as half-select switching.
A serious problem that needs to be overcome in order to build reliable MRAM devices is the distribution of the switching fields that occur in the selected and unselected bits. A distribution of selected or unselected write fields strongly degrades bit yield. This is due to an overlap in the distribution of the write currents between the selected and unselected bits. It has been determined that this problem is attributable in part to the shape of the memory cells.
Referring again to
The problem with the shape of the current magnetic memory cell (i.e., ellipse, rectangle, hexagon) is that they are perfectly symmetrical. Any slight deviation from the perfectly symmetrical shape due to, for example, manufacturing process variations can cause a significant change in the magnetic fields and currents required to write a bit into the cells increasing the distribution of write currents within the array. This decreases write margin (i.e., the difference between the write currents of selected and unselected bits), which reduces bit yield.
Accordingly, there is a desire and need for a cell and bit design that increases the write margin and bit yield in an MRAM device.
The present invention provides a design for memory cells of an MRAM device that increases the write margin and bit yield of the MRAM device.
The above and other features and advantages are achieved by providing an asymmetric cell and bit design, rather than a symmetric design, for an MRAM device. The design is asymmetric when reflected about the easy-axis and has a centroid that is displaced from the bit center along the hard-axis. This asymmetry is large enough so that manufacturing process variations do not substantially change the switching fields of the stored bits. In addition, the asymmetry causes the ends of the bits to align in opposite directions in small half-select fields and parallel to each other at large half-select fields, which increases the difference in the switching fields between selected and unselected bits. The combined effect of these two characteristics results in increased bit yield (relative to similarly sized symmetric cells and bits) due to a smaller overlap between selected and unselected bit switching distributions.
The foregoing and other advantages and features of the invention will become more apparent from the detailed description of exemplary embodiments provided below with reference to the accompanying drawings in which:
In the following detailed description, reference is made to various specific embodiments in which the invention may be practiced. These embodiments are described with sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be employed, and that structural and electrical changes may be made without departing from the spirit or scope of the present invention.
As noted above, a fundamental problem that needs to be overcome in any MRAM device is the distribution of switching fields that results in poor bit yield due to an overlap between the write current distributions of selected and unselected bits. It has been determined that there are various parameters intrinsic to the MRAM cell/bit that could affect the selected and unselected bit distribution overlap. These include, but are not limited to random variations in bit shape from bit to bit, random variations in material parameters from bit to bit, the sequence of fields by which the bit is written, the value of the fields used to write a bit, and magnetic noise.
A major contributor to the width of the switching field distributions relates to the magnetization reversal mode. The magnetization reversal mode can be defined as the sequence of magnetization patterns during the magnetization reversal process (i.e., the switching of the magnetization direction of vector 21 illustrated in
It has been determined that if properly selected, the bit shape and write fields used to write the bit can be used to increase the distance between the mean of the selected and unselected write field distributions (i.e., increase the write margin) and to decrease the width of the write field distributions by locking in a preferred reversal mode.
Bit shape and corresponding symmetry/asymmetry can be quantified using the bit centroid and rotation with respect to the coordinate system illustrated in
The x and y coordinates of a bit's centroid are defined as follows:
The bit rotation is defined as:
Using these definitions, bit symmetry/asymmetry is defined as follow:
Bit symmetry/asymmetry strongly determines magnetization patterns, since the magnetization prefers to align parallel to the edges of the bit.
As shown above with respect to
All bits in the simulation are nominally 270 nm long, by 180 nm wide and 4 nm thick ellipses.
The axes for the graph are the hard-axis write field (Hy) and the easy-axis write fields (Hx). That is, Hy is the half-select field, and Hx is the switching field. The units for the fields in the graph are oersted (Oe). The curves represented by lines 50a, 50b, 60a, 60b, 70a, 70b, 80a, 80b are usually referred to as switching astroids. The memory cell operating points are represented by Hx, Hy pairs. If the operating point is between the two lines of the curve (i.e., inside the astroid), a bit cannot be written into the cell. If, however, the operating point is on the outer left or right of the two lines of the curve (e.g., outside the astroid), the bit can be written into the cell.
The subtle differences in bit shape illustrated in
It should be noted that the present invention also encompasses the effects of material parameter variation as well as dimensional variation. Had material parameter variation and/or dimensional variation been introduced into the above example, the switching field distribution at fixed values of Hy would be larger than those shown in FIG. 8. As noted above, increasing the difference in Hx between the unselected and selected states (Hy=0 and Hy≠0) improves bit yield. The bit shape characterized by equation (6) would have this effect.
Two exemplary switching modes are illustrated in
Thus, simulations of the lopsided asymmetrical bits (asym#2 and asym#3 illustrated in
It should be noted that the cells with the asymmetric bit shapes such that the centroid is displaced from the bit center along the hard-axis can be manufactured by any processing method or technique and that the invention is not to be limited to any such method. Moreover, the layers (e.g., layers 16-18 illustrated in
The system 200 includes a central processing unit (CPU) 202, e.g., a microprocessor, that communicates with the memory circuit 212 and an I/O device 208 over a bus 220. It must be noted that the bus 220 may be a series of buses and bridges commonly used in a processor system, but for convenience purposes only, the bus 220 has been illustrated as a single bus. A second I/O device 210 is illustrated, but is not necessary to practice the invention. The system 200 may also include additional memory devices such as a read-only memory (ROM) device 214, and peripheral devices such as a floppy disk drive 204 and a compact disk (CD) ROM drive 206 that also communicates with the CPU 202 over the bus 220 as is well known in the art. It should be noted that the memory 212 may be embedded on the same chip as the CPU 202 if so desired.
While the invention has been described and illustrated with reference to exemplary embodiments, many variations can be made and equivalents substituted without departing from the spirit or scope of the invention. Accordingly, the invention is not to be understood as being limited by the foregoing description, but is only limited by the scope of the appended claims.
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