An associative memory comprises an array of memory cells arranged in rows and columns, each row comprising a plurality of segments each of which comprises a set of said memory cells, wherein each memory cell has compare circuitry for comparing input data with data stored therein and for generating a cell match signal when said input data matches said stored data and match signal combining circuitry for receiving a match signal from a preceding cell in the set and operable to generate a logical value dependent on the match signal of the current cell and the match signal of the preceding cell whereby each segment generates a resultant segment logical value, the memory further comprising combinatorial logic circuitry associated with each row for combining said resultant segment logical values to generate a final output match signal for that row.
|
9. An associative memory comprising:
a current memory cell that includes a match signal combining circuit, wherein the match signal combining circuit provides a logical value that is derived by comparing a current match signal from the current memory cell with a previous match signal from a previous memory cell, and wherein said previous match signal is generated prior to said current match signal.
10. An associative memory comprising:
a memory row that includes two or more memory segments, wherein each of the memory segments includes two or more memory cells and each of the memory cells includes a match signal combining circuit to provide a memory cell logical value that is derived by comparing a match signal from the memory cell with a previous match signal from a previous memory cell, a segment logical value circuit associated with each of said memory segments that provides a segment logical value derived from the memory cell logical value; and a combinatorial logic circuit associated with the memory row that provides a final output match signal by a comparison of the segment logical values.
1. An associative memory comprising an array of memory cells arranged in rows and columns, each row comprising a plurality of segments each of which comprises a set of said memory cells, wherein each memory cell has compare circuitry for comparing input data with data stored therein and for generating a cell match signal when said input data matches said stored data and match signal combining circuitry for receiving a match signal from a preceding cell in the set and operable to generate a logical value dependent on the match signal of the current cell and the match signal of the preceding cell whereby each segment generates a resultant segment logical value, the memory further comprising combinatorial logic circuitry associated with each row for combining said resultant segment logical values to generate a final output match signal for that row.
19. A method of comparing in put data with stored data in an associative memory comprising:
providing an array of memory cells arranged in memory rows where each row is divided into two or more memory segments; comparing a first input data bit with a first stored data bit in a first memory cell in order to generate a first cell match signal; comparing a second input data bit with a second stored data bit in a second memory cell in order to generate a second cell match signal; comparing said first cell match signal and said second cell match signal in a first match signal combining circuit in order to generate a first logical value; comparing a third input data bit with a third stored data bit in a third memory cell in order to generate a third cell match signal; and comparing said third cell match signal with said first logical value in a second match signal combining circuit in order to generate a second logical value.
2. An associative memory according to
3. An associative memory according to
4. An associative memory according to
5. An associative memory according to
6. An associative memory according to
7. An associative memory according to
8. An associative memory according to
11. The associative memory of
12. The associative memory of
said combinatorial logic circuit comprises a first AND gate to receive the segment logical values from said first pair of memory segments in order to produce a first resultant segment logical value.
13. The associative memory of
a second AND gate to receive the first resultant segment logical value and the segment logical value of the third segment in order to produce a second resultant segment logical value; and a third AND gate to receive the second resultant segment logical value and the segment logical value of the fourth segment in order to produce the final output match signal.
14. The associative memory of
a second AND gate to receive the segment logical values from said second pair of memory segments in order to produce a second resultant segment logical value; and a third AND gate to receive the first and second resultant segment logical values in order to produce said final output match signal.
15. The associative memory of
16. The associative memory of
17. The associative memory of
18. The associative memory of
20. The method of
21. The method of
|
The present invention relates to an associative memory of the type commonly known as a CAM.
As is well known in the art, such memories comprise an array of memory cells, each holding a data bit, the cells being arranged in rows and columns. Each row normally holds a word, for example of 32 bits. Data can be read and written into a CAM in a manner similar to that for a random access memory (RAM). In addition, a CAM cell has an additional function in that it provides a match signal indicating whether a data word input to the CAM array matches a data word already stored in the array. This function can be used to quickly check the contents of the CAM for a word match, by inputting a data word and generating a match signal for any row of the CAM in which all bits of the data word match the bits stored in memory cells of that row. When the match signal for the row is high, this indicates that the input data word is stored in the CAM array.
To perform this function, each CAM cell generates a local or cell match signal which indicates if data input to the cell matches the data already stored in the cell. In order to determine whether or not a complete word is matched, these local match signals need to be somehow combined to generate a match signal for a row. It will readily be appreciated, that as soon as one of the cells fails to match, the match signal for the row is low.
According to this arrangement, the match outputs m0, m1 . . . m32 drive the output transistors 20, 21 . . . 232 in parallel. If any one of the local match signals is low, the output signal MATCH at a so-called common node 8 will be caused to fall.
A disadvantage of this arrangement is that it requires precharge and hold circuitry as represented by transistor 4 and holding circuitry 6, the precharge transistor 4 being required to precharge the common node 8 high in between each match cycle. The precharge logic requires timing analysis etc., which makes it potentially complex to operate.
According to an alternative known arrangement, the cell match signals are supplied in pairs to respective AND gates. The outputs of these AND gates are likewise supplied in pairs to a subsequent logic stage of AND gates. Thus, the match signals are combined in pairs to generate a final logical value for the match signal for each row. For a row of 32 bits, six stages of logic gates are required. Although this overcomes the problems associated with the need for precharge circuitry, the distance between the stages is large, requiring large drive transistors to encompass the distances. However, it is frequently the case that the drive transistors are not utilised, for the simple reason that many of the match outputs will be zero. Thus, this design is inherently redundant.
It is an aim of the present invention to provide an associative memory in which the match cell is generated in an easier and more efficient manner.
According to the present invention there is provided an associative memory comprising an array of memory cells arranged in rows and columns, each row comprising a plurality of segments each of which comprises a set of said memory cells, wherein each memory cell has compare circuitry for comparing input data with data stored therein and for generating a cell match signal when said input data matches said stored data and match signal combining circuitry for receiving a match signal from a preceding cell in the set and operable to generate a logical value dependent on the match signal of the current cell and the match signal of the preceding cell whereby each segment generates a resultant segment logical value, the memory further comprising combinatorial logic circuitry associated with each row for combining said resultant segment logical values to generate a final output match signal for that row.
For a better understanding of the present invention and to show how the same may be carried into effect, reference will now be made by way of example to the accompanying drawings, in which:
The CAM array 10 itself comprises a plurality of CAM cells arranged in rows and columns. According to the described embodiments of the invention, each row of the CAM is organised into segments as will now be described in the following.
According to a first embodiment of the invention illustrated in
According to a second embodiment of the invention illustrated in
That local match signal is supplied to the subsequent cell, cell 2, in the segment. That cell has circuitry for comparing data input to the cell dinp <2> with data stored in it, and also for taking into account the match signal m<1> generated by the preceding cell. It generates a local match signal m<1:2> which has a logical high value only if the data input to the second cell, cell 2, matches the data stored therein and the incoming match signal m<1> from the preceding cell is high. Successive cells in the segment are connected in the same way, with the result that the segment or byte match signal generated by cell 7 m<1:7> is high only if there has been a match in all of the preceding cells.
The data storage portion 52 is similarly associated with data write transistors 56, 58. The data write transistors 56, 58 are controlled by the data write signal wrd. The data inputs dinp, dinn are supplied respectively to the data write transistors in the inverse manner to that in which they are supplied to write the mask storage portion 50. The data storage portion 52 is connected to pass gates 60, 62 each of which receive data dinp and its inverse dinn for matching purposes. The pass gates 60, 62 implement an exclusive OR function which constitutes a comparison. If the data input at the data terminal dinn matches the data stored in the data storage portion 52 of the cell, a match_data signal is set high. If there is no match, the match_data signal is set low.
Each cell also comprises logic circuitry denoted generally by reference numeral 70. The logic circuitry receives the match_data signal 71 from the pass gates 60, 62, the inverse a mask signal not_mask on line 72 from the mask storage portion 50 and a match_in signal which is the local match signal from the preceding cell, denoted m<i> in this case. It will be understood that the cell illustrated in
The match_in signal 74 is supplied to the input of a p-channel transistor 86 connected between the supply voltage V and an output match line 76. The match_in signal 74 is also supplied to an n-channel transistor 88 connected between the common node 85 and ground. The not_mask signal 72 is also supplied to the gate of an n-channel transistor 90 connected in series between the common node 85 and the p-channel transistor 86 which receives the match_in signal 74. The output match line 76 is connected to an inverter 92 which generates the local match signal match_out.
The transistor 86 which receives the match_in signal 74 ensures that the local match signal match_out is low if the input match signal match_in from the preceding cell is low. If the input match signal match_in is low, the p-channel transistor 86 is turned on, allowing the output line 76 to be pulled to the supply voltage V and thus to a high logical value. The inverter 92 thus sets the output match signal match_out to a low logical value in these circumstances.
If the input match signal match_in 74 is high, however, the p-channel transistor 86 is turned off but the n-channel transistor 88 is turned on, allowing the common node 85 to be pulled towards ground. If the match_data signal 71 is also high (indicating a match between the input data dinp and the data stored in the data storage portion 52 of the cell), then the n-channel transistor 82 is turned on which allows the output line 76 to be pulled low. This in turn causes the output match signal match_out to have a high logical value, thereby indicating a match.
Similarly, if the not_mask signal 72 is high, the transistor 90 is turned on, which likewise causes the output line 76 to be pulled low and thus generates a high match_out signal.
In this way, combinatorial logic circuit 70 has the following logical result:
where din represents the positive input data to the cell during a match cycle and data represents the data stored in the data storage portion 52 of the cell.
It will be appreciated that the cell also matches if mask=0.
The CAM design described above has the advantage that it reduces the delay in generating a match signal, but yet does not introduce too many logical stages. Although the overall CAM array layout is increased, the fundamental cell construction can be small because the drive transistor is only ever required to drive its nearest neighbour in terms of the local match signal generated by it. Thus, the combination of reduced transistor size in each CAM cell, and a small number of logical stages of AND gates provides a significant advantage over earlier designs.
Patent | Priority | Assignee | Title |
6785153, | Sep 25 2001 | Micron Technology, Inc. | Tertiary CAM cell |
7145789, | Jan 05 2005 | Texas Instruments Incorporated | Low power low area precharge technique for a content addressable memory |
Patent | Priority | Assignee | Title |
5586288, | Sep 22 1993 | Hilevel Technology, Inc. | Memory interface chip with rapid search capability |
5638315, | Sep 13 1995 | International Business Machines Corporation | Content addressable memory for a data processing system |
5859791, | Feb 06 1997 | FOOTHILLS IP LLC | Content addressable memory |
5999435, | Jan 15 1999 | Intel Corporation | Content addressable memory device |
6081440, | Nov 05 1998 | AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LIMITED | Ternary content addressable memory (CAM) having fast insertion and deletion of data values |
6161164, | Sep 16 1996 | International Business Machines Corp. | Content addressable memory accessed by the sum of two operands |
6175514, | Jan 15 1999 | Intel Corporation | Content addressable memory device |
6188629, | Nov 05 1999 | SAMSUNG ELECTRONICS CO , LTD ; CECIL H KAPLINSKY BYPASS TRUST DATED NOVEMBER 11, 1999, THE; VESSELINA KAPLINSKY MARITAL TRUST DATED NOVEMBER 11, 1999, THE | Low power, static content addressable memory |
Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
Jun 19 2002 | STMicroelectronics Limited | (assignment on the face of the patent) | / | |||
Jul 15 2002 | BARNES, WILLIAM | STMicroelectronics Limited | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 013191 | /0143 |
Date | Maintenance Fee Events |
Nov 30 2006 | M1551: Payment of Maintenance Fee, 4th Year, Large Entity. |
Dec 05 2006 | ASPN: Payor Number Assigned. |
Nov 29 2010 | M1552: Payment of Maintenance Fee, 8th Year, Large Entity. |
Dec 08 2014 | M1553: Payment of Maintenance Fee, 12th Year, Large Entity. |
Date | Maintenance Schedule |
Jun 17 2006 | 4 years fee payment window open |
Dec 17 2006 | 6 months grace period start (w surcharge) |
Jun 17 2007 | patent expiry (for year 4) |
Jun 17 2009 | 2 years to revive unintentionally abandoned end. (for year 4) |
Jun 17 2010 | 8 years fee payment window open |
Dec 17 2010 | 6 months grace period start (w surcharge) |
Jun 17 2011 | patent expiry (for year 8) |
Jun 17 2013 | 2 years to revive unintentionally abandoned end. (for year 8) |
Jun 17 2014 | 12 years fee payment window open |
Dec 17 2014 | 6 months grace period start (w surcharge) |
Jun 17 2015 | patent expiry (for year 12) |
Jun 17 2017 | 2 years to revive unintentionally abandoned end. (for year 12) |