A frame switching apparatus in which it is possible to suppress the operating frequency of the bus and to suppress the cell loss ratio in comparison with that of an ATM cell switching apparatus employing the conventional input buffer system. Since the small capacity buffer Bn-n furnishes a transient storage site for a cell C, a distribution circuit 3n is able to receive a new cell Cn from the input buffer 2n to process the received cell. Therefore, head-of-line blocking is less likely to take place. On the other hand, since the small capacity buffer transfers the cell to only one output port, it is sufficient if the switching matrix SWM is of a N:1 multiplexer structure which is far simpler than a complete cross-bandwidth available register structure.
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1. An apparatus for switching frame data in which data is switched in terms of a pre-set number of frames as a unit, comprising:
input buffer means for storing frame data arriving at an input port from an external data source; distribution means for checking addresses of the frame data stored in said input buffer means and for distributing the frame data to respective output ports; memory means connected to a downstream side of said distribution means in association with said output ports for temporarily storing the frame data distributed by said distribution means; switching means for connecting said memory means to said output ports; and arbitration means for controlling said switching means.
5. A method for switching frame data in which data is switched in terms of a pre-set number of frames as a unit, comprising:
a step of storing frame data arriving at an input port from an external data source in an input buffer; a step of checking addresses of the frame data stored by said step of storing frame data for associatively distributing the frame data to respective output ports; a step of temporarily storing in a memory the frame data distributed by said distribution step in association with said output ports; a step of arbitrating a switching portion between said memory and the output ports in a controlled manner; and a step of transferring the frame data stored in said step of storing frame data to said output ports in response to a use permission of the switching portion arbitrated by said arbitration step.
2. The frame data switching apparatus according to
switching of said frame-based data is performed in an asynchronous transfer mode.
3. The frame data switching apparatus according to
said memory means issues a transfer request to said arbitration means when said frame data are stored in said memory means.
4. The frame data switching apparatus according to
said arbitration means issues a transfer permission depending on a priority when said transfer request is received in a competitive state from said plurality of memory units.
6. The frame data switching method according to
a step of switching the frame-based data is in an asynchronous transfer mode.
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1. Field of the Invention
This invention relates to a frame data exchanging method and apparatus in which data is exchanged in terms of a pre-set number of frames as a unit.
2. Description of the Related Art
In communication application such as remote conferencing, large-scale distributed computing or data base, a high-speed network is required. Thus, high-speed communication by asynchronous transfer mode (ATM) has come to be used. This ATM is a technique of digitizing the information, such as speech, data or picture, splitting the information into information units of constant short lengths, switching at a high speed and transmitting the information to a counterpart side of the communication.
The current ATM switching mechanism employs roughly three systems, namely (1) an input buffer system, (2) an output buffer system and (3) a c-owned buffer system.
(1) In the input buffer system, a memory for transient storage of cells is provided in each input port. The memory is required to store the inputted cells reliably and operates at a speed higher than the information transmitting speed at the input port. The frame transfer occurs in accordance with the inputting sequence, that is in accordance with the first-in first-out (FIFO) system, so that, if the leading cell of the memory competes with other input ports as to acquisition of the output port , there is produced a head-of-line (HOL) blocking phenomenon in which succeeding cells cannot be transferred. The result is that the cells tend to be stagnant in the memory so that the cells tend to overflow from the memory to produce cell loss.
(2) The output buffer system provides a memory at each output port for transient cell storage. If the cell arrives at the input port, this cell needs to be instantly transferred to the memory of the output port. Therefore, the bus interconnecting the memories of the input and output ports needs to be operated at a speed not lower than the information transporting speed of the input port multiplied by the number of the input ports.
(3) The co-owned buffer system provides a sole buffer. The cells arriving at the totality of the input ports are immediately transferred and subsequently the cells stored in the buffer are read out by the output ports. Since the totality of the input ports and output ports communicate with the sole buffer, the bus interconnecting the buffer and the input and output ports needs to be operated at a speed not lower than the speed corresponding to a sum of the information transmission speed at the input port multiplied by the number of the input ports and the information transmission speed of the output port multiplied by the number of the output ports.
In the input buffer system (1), the bus operating speed is lower than that in the output buffer system (2) or in the co-owned buffer system (3), however, the frame loss ratio is higher than that in the output buffer system (2) or in the co-owned buffer system (3). In the output buffer system (2) or in the co-owned buffer system (3), the frame loss ratio is lower than that in the input buffer system (1), however, the bus operating speed is higher than that in the input buffer system (1).
For the above reason, it has been difficult in the conventional ATM switching mechanism to improve the cell switching speed to a value higher than a certain value as the cell loss ratio is suppressed to a lower value.
It is therefore an object of the present invention to provide a frame switching method and apparatus in which it is possible to suppress the bus operating frequency and to suppress the cell (frame) loss ratio to a value lower than that in the ATM switching mechanism employing the conventional input buffer system.
In one aspect, the present invention provides an apparatus for switching frame data in which data is switched in terms of a pre-set number of frames as a unit, including: input buffer means for storing frame data arriving at an input port from outside, distribution means for checking the addresses of the frame data stored in the input buffer means for associatively distributing the respective frame data to output ports, memory means connected to an downstream side of the distribution means in association with the output ports for temporarily storing the frame data distributed by the distribution means in association with the output ports, switching means for connecting the memory means to the output ports and arbitration means for controlling the switching means.
In another aspect, the present invention provides a method for switching frame data in which data is switched in terms of a pre-set number of frames as a unit, including a step of storing frame data arriving at an input port from outside in an input buffer, a step of checking the addresses of the frame data stored by the frame data storage step for associatively distributing the respective frame data to output ports, a step of temporarily storing the frame data distributed by the distribution step in association with the output ports, a step of arbitrating a switching portion between the memory and the output port in a controlled manner and a step of transferring the frame data stored in the storage step to the output port responsive to a use permission of the switching portion arbitrated by the arbitration step.
In accordance with the present invention, there may be provided a frame switching method and apparatus by means of which it is possible to suppress the operating frequency of the bus and to suppress the cell loss ratio in comparison with that in an ATM cell switching apparatus employing the conventional input buffer system.
Referring to the drawings, preferred embodiments of according to the present invention will be explained in detail.
The present embodiment is directed to an ATM cell switching apparatus in which frame data from plural hard disc drives (HDDs), having e.g., MPEG data recorded thereon, to input ports thereof in an asynchronous transfer mode (ATM) in terms of a pre-set number of frames as a unit to output ports thereof. The ATM switching apparatus is usually denoted as an ATM cell switching apparatus.
The ATM cell switching apparatus has four input ports 11, 12, 13 and 14 and four output ports 61, 62, 63 and 64, as shown in FIG. 1. In reality, the number of the input and output ports may be less than 4 or more than 4.
The ATM cell switching apparatus, shown in
The input buffer 2n is able to store 32 of 53 byte cells.
The small capacity memories 41, 42, 43, 44 each include a number of small capacity memories equal to the number of the output ports. For example, the small capacity memory 41 includes four small capacity memories B1-1, B1-2, B1-3 and B1-4, whilst the small capacity memory 42 includes four small capacity memories B2-1, B2-2, B2-3 and B2-4. The small capacity memory 43 includes four small capacity memories B3-1, B3-2, B3-3 and B3-4, whilst the small capacity memory 44 includes four small capacity memories B4-1, B4-2, B4-3 and B4-4. A small capacity memory Bn-n is split into five and stores five cells.
Each of the distribution circuits 31, 32, 33 and 34 checks an address from the ATM header of the ATM cell data to distribute the data to a sole small capacity memory Bn-n of the set of small capacity memories 4n associated with the four output ports.
To the ATM header are allocated five bytes, as shown in
The GFC is used for accessing control in shared media, whilst the VPI and the VCI are used as identifiers for a virtual bus and a virtual channel, respectively. The PT, CLP and the HEC are used as the control information irrelevant to the switching function in the present invention.
Usually, a sum total of 24 bits of the VPI and the VCI are used as address. However, professional users sometimes use these 24 bits plus four bits of the GFC, totalling 28 bits, as address.
In reality, an address is generated from three bits as counted from the LSB of the VPI and five bits as counted from the LSB of the VCI, as shown in
The switching matrix SWM is implemented by providing a sole bus per output port. Therefore, the number of buses is equal to the number of output ports (=4). These buses are controlled by the arbitration circuit 51, 52, 53 and 54 belonging to the output ports 61, 62, 63 and 64 connecting to the respective buses.
The contents controlled by the arbitration circuits 51, 52, 53 and 54 reside in arbitration of the rights for the cells Cn sent from the plural input ports 11, 12, 13 and 14 through the small capacity memories 41,42, 43, 44.
The internal structure of the arbitration circuit 51, is shown in FIG. 4. To this arbitration circuit 51, data buses from the small capacity memories B1-1, B2-1, B3-1 and B4-1 are coupled through the switching matrix SWM. These small capacity memories B1-1, B2-1, B3-1 and B4-1 are uppermost small capacity memories of the four small capacity memories 41, 42, 43, 44. Between the small capacity memories B1-1, B2-1, B3-1 and B4-1 and the arbitration circuit 51 are connected signal lines for cell transfer request RQ# sent from the small capacity memories B1-1, B2-1, B3-1 and B4-1 to the arbitration circuit 51 and signal lines for cell transfer permission AK# sent from the arbitration circuit 51 to the small capacity memories B1-1, B2-1, B3-1 and B4-1. On reception of the above two requests in a competitive state from plural, e.g., two small capacity memories, the arbitration circuit 51 selects one of them by any suitable selection means. If, for example, a signal denoting priority is contained in the transfer request#, a priority verification unit 13 is used to verify the priority to select the transfer request having a higher priority. The arbitration circuit 51 returns a cell transfer permission AK# to the small capacity memory Bn-n which has made the transfer request with the higher priority.
The typical operation is explained with reference to
First, a cell C1 enters the input port 11, as shown in FIG. 5. The cell C1 is stored in the input buffer 21, of the input port 11.
This cell C1 then is outputted from the input buffer 21. The distribution circuit 31 determines an output port which is to be an address, here the output port 61. Correspondingly, the cell C1 is stored in an appropriate one of the small capacity buffers, here the small capacity buffer B1-1 for the cell C1 bound for the output port 61 which has entered the input port 11.
If then the cell C1 enters the small capacity buffer B1-1, this small capacity buffer B1-1 sends a cell transfer request RQ1 to the arbitration circuit, here the arbitration circuit 51 of the output port 61, as shown in FIG. 7.
The arbitration circuit 51 then returns the cell transfer permission to the small capacity buffer B1-1, as shown in FIG. 8.
The small capacity buffer B1-1 then sends the cell C1 through the switching matrix SWM to the output port 61, to halt the cell transfer request RQ1, as shown in FIG.9. The cell C1 then is outputted at the output port 61, as shown in FIG. 10.
The operation in case two small capacity buffers send a cell transfer request to the same output port in a competitive fashion is explained by referring to
First, the cell C1 enters the input port 11,as shown in FIG. 11. This cell C1 is stored in the input buffer 21 of the input port 11. Simultaneously, a cell C4 enters the input port 14, and stored in the input buffer 24 of the input port 14.
The cell C1 is stored by the distribution circuit 31 in the small capacity buffer B1-1, as shown in FIG. 12. Simultaneously, the cell C4 is stored in the small capacity buffer B4-1 by the distribution circuit 34.
The small capacity buffer B1-1 then sends the cell transfer request RQ1 to the arbitration circuit 51, as shown in FIG. 13. Simultaneously, the small capacity buffer B4-1 sends a cell transfer request RQ4 to the arbitration circuit 51.
The arbitration circuit 51 selects one of them by any suitable selection means, such as the priority verification unit 13 of
The small capacity buffer B1-1 then sends the cell Cl to the output port 61, through the switching matrix SWM to halt the cell transfer request RQ1. The arbitration circuit 51 then accepts the cell transfer request RQ4 from the small capacity buffer B4-1 to return the cell transfer permission AK4 to the small capacity buffer B-4.
The cell C1 then exits the output port 61, as shown in FIG. 16. Simultaneously, the small capacity buffer B4-1 sends the cell C4 through the switching matrix SWM to the output port 61 to halt the cell transfer request RQ4. The cell C4 then exits the output port 61, as shown in FIG. 17.
In particular, since the small capacity buffer B1-1 furnishes a temporary storage site for cells, as shown in
Also, since the small capacity buffer transfers a cell to only one output port, it suffices if the switching matrix SWM has a N:1 multiplexer structure. This is far simpler than the complete crossbar structure.
Moreover, it suffices if the small capacity buffer outputs its memory contents to the switching matrix SWM in a FIFO sequence. This sort of the circuit can be implemented as circuit operating at an elevated speed.
With the above-described ATM cell switching apparatus, provided with the small capacity buffer, it is possible to suppress the frequency of occurrence of the HOL blocking phenomenon, which is a defect of the input buffer system capable of suppressing the operating frequency of the internal bus of the ATM cell switching apparatus .
In
In more detail,
For comparison,
In
It is also seen from
The ATM cell switching apparatus shown in
In the ATM cell switching apparatus of the present invention, in which characteristics close to those of the output buffer system may be obtained by providing a sufficient number of stages of small capacity memories, the performance achieved is close to that of the lower graph for the output buffer system.
In the above-described ATM cell switching apparatus, in which cells are stored on the address basis, means for burst transfer or means for lump transfer of plural cells can more effectively be applied. This serves for suppressing the bus operating frequency.
Kunito, Yoshiyuki, Miyoshi, Yutaka, Hasegawa, Junichi
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