Internally generating test vectors on a microchip during a burnin stage allows for better toggle coverage while not requiring external memory. A test access port (TAP) controller which accepts signals from a user and indicates to a linear feedback shift register (lfsr) that the microchip is in the burnin stage. The lfsr then may generate a set of pseudorandom values using a polynomial. The values are then shifted one per clock cycle into the internal scan chain of flips-flops on the chip, which toggles the internal state of the chip. New pseudorandom values are also generated one-by-one during the shift. By using this approach, the internal states of the chip are toggled without the use of an external memory for the burnin system.
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1. A microchip test design for internally generating test vectors during a burnin test including:
a test access port (TAP) controller having a first input, a second input, and an output; a linear feedback shift register (lfsr) having an input and an output, said input of said lfsr coupled to said output of said TAP controller, wherein said lfsr further includes an xor gate having five inputs and an output, an output on each of a last, second-to-last, third-to-last, twenty-second-to-last, and first lfsr flip-flops coupled to an input of said xor gate, said output of said xor gate coupled to an input of said first lfsr flip-flop; one or more flip flops organized in an internal scan chain, a first of said one or more flip-flops having an input coupled to said output of said LPSR, a last of said one or more flip-flops having an output coupled to said second input of said TAP controller; and said TAP controller further including a test data output (TDO).
2. The microchip test design of
3. The microchip test design of
4. The microchip test design of
5. The microchip test design of
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1. Field of the Invention
The present invention relates to the field of microchip design. More specifically, the present invention relates to the use of internally generated vectors for the burnin system for testing a microchip.
2. The Background
When constructing a microchip, it is typical to run what is called a "burn-in" test on the circuits in the chip. Burn-in is a long, thorough, carefully controlled preliminary test performed in order to stabilize a chip's electrical characteristics after manufacture and to ensure that it will function according to rated specifications. For microchips, a commonly run burn-in test is to run the chip at a high temperature for an extended period of time (such as 48 hours).
Microchips are often designed with test circuitry built-into the chip for use in the test phase of development. The circuitry not be used after shipment of the chip to customers, but the built-in circuitry allows tests to be performed by test facilities at a high rate of speed. A common test design is called a full scan design, which gives observability and controllability over internal states of the microchip to whoever is running the tests. When this capability is used along with the high temperature test, this allows every state of every flip-flop in the circuit to be tested at the high temperature, and oftentimes will reveal a problem in design or manufacture that no other test uncovered.
The goal in designing good test circuitry in this area, therefore, is to be able to toggle as many internal nodes of the microchip as possible during the burn-in stage in order to make the whole chip function during testing, which provides the maximum amount of stress testing of the microchip. This has generally been accomplished by designing the test circuitry to utilize automatic test pattern generation (ATPG) vectors generated by a software tool accompanying the microchip. The ATPG vectors are loaded into a memory, and then sequentially fed to the microchip in order to test all the possible states of the flip-flops in the circuit during burnin.
There is limited memory, however, available in the burnin system. Adding external memory adds additional costs to the burnin process. What is needed is an efficient solution which allows for better toggle coverage while still utilizing the limited memory available.
Internally generating test vectors on a microchip during a burnin stage allows for better toggle coverage while not requiring external memory. A test access port a (TAP) controller which accepts signals from a user and indicates to a linear feedback shift register (LFSR) that the microchip is in the burnin stage. The LFSR then may generate a set of pseudorandom values using a polynomial. The values are then shifted one per clock cycle into the internal scan chain of flips-flops on the chip, which toggles the internal states of the chip. New pseudorandom values are also generated one-by-one during the shift. By using this approach, the internal states of the chip are toggle without the use of an external memory for the burnin system.
In the following description, a preferred embodiment of the invention is described with regard to preferred process steps and data structures. However, those skilled in the art will recognize, after perusal of this application, that embodiments of the invention may be implemented using at least one general purpose computer operating under program control, and that modification of the general purpose computer to implement the components, process steps, and/or data structures described herein would not require undue invention.
In accordance with a presently preferred embodiment of the present invention, the components, process steps, and/or data structures are implemented on a microchip using logic circuitry. This implementation is not intended to be limiting in any way. Different implementations may be used and may include software, computing platforms, program storage devices and/or computer programs. In addition, those of ordinary skill in the art will readily recognize that devices of a less general purpose nature, such as hardwired devices, devices relying on FPGA (field programmable gate array) or ASIC (application specific integrated circuit) technology, or the like, may also be used without departing from the scope and spirit of the inventive concepts disclosed herewith.
In accordance with a specific embodiment of the present invention, a linear feedback shift register (LFSR) is implemented within the test circuitry on the microchip. The LFSR generates random test vectors and then shifts them into the internal scan chain of the chip. This allows all the possible states of the flip-flops in the internal scan chain to be toggled without utilizing a memory. The design of the LFSR allows the burnin process to be accomplished without the use of an external memory, and also provides for better toggle coverage.
A seed is setup prior to the burnin instruction activation. When control signals are received by the LFSR from the TAP Controller 10 indicating that random test vectors should be generated, the LFSR uses a polynomial to randomly generate the vectors. All random pattern sensitive circuitry may then be protected by enabling the control signals that force them into safe states. In a specific embodiment of the present invention, the polynomial used is x32+x22+x2+x+1. The LFSR 12 sends test values to an internal scan chain of flip-flops 22, which tests the flip-flops, the output of the internal scan chain 22 leading back to the TAP Controller 10. The output will be available on a test data output (TDO) line from the TAP Controller 10.
Thus the present invention allows for the toggling of the logic during a burnin stage by using internally generated vectors, eliminating the need for external. memory and therefore reducing overhead while producing better toggle coverage.
While embodiments and applications of this invention have been shown and described, it would be apparent to those skilled in the art having the benefit of this disclosure that many more modifications than mentioned above are possible without departing from the inventive concepts herein. The invention, therefore, is not to be restricted except in the spirit of the appended claims.
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