In one embodiment, a first dielectric layer (32) that overlies a fuse (16) and a bonding pad (30) is etched with a first etch process. This first etch process exposes a portion (40) of a second dielectric layer (20) that underlies the first dielectric layer (32) and overlies the fuse (16). In addition, the first etch process also forms a bond pad opening (38) that exposes a portion (42) of an anti-reflective layer (28) that forms a portion of the bonding pad (30). A second etch process is then used to etch the exposed portion (42) of the anti-reflective layer (28) and the exposed portion (40) of the second dielectric layer (20) at substantially the same rate to form a fuse window (45) overlying the fuse (16). The second etch process prevents over etching of the second dielectric layer (20), and thus exposure of the underlying fuse (16).
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32. A method for forming an integrated circuit comprising the steps of:
providing a semiconductor substrate; forming a fuse overlying the semiconductor substrate; forming a first dielectric layer overlying the fuse; forming a bonding pad overlying the first dielectric layer, wherein the bonding pad comprises an anti-reflective layer overlying a conductive layer; and etching a portion of the anti-reflective layer and a portion of the first dielectric layer to leave a remaining portion of the first dielectric layer overlying the fuse and to expose a portion of the conductive layer, the anti-reflective layer having a first etch rate and the first dielectric layer having a second etch rate, wherein the second etch rate is within 20 percent of the first etch rate such that an etch selectivity of approximately 1:1 is achieved between the anti-reflective layer and the first dielectric layer.
13. A method for forming an integrated circuit comprising the steps of:
providing a semiconductor substrate; forming a fuse overlying the semiconductor substrate; forming a first dielectric layer overlying the fuse; forming a bonding pad overlying the first dielectric layer, wherein the bonding pad comprises an anti-reflective layer overlying a conductive layer; and etching a portion of the anti-reflective layer and a portion of the first dielectric layer to leave a remaining portion of the first dielectric layer overlying the fuse and to expose a portion of the conductive layer, the anti-reflective layer having a first etch rate and the first dielectric layer having a second etch rate, wherein the first etch rate and the second etch rate are substantially the same such that an etch selectivity of approximately 1:1 is achieved between the anti-reflective layer and the first dielectric layer.
27. A method for forming an integrated circuit comprising the steps of:
providing a semiconductor substrate; forming a first dielectric layer overlying the semiconductor substrate; forming a fuse overlying the first dielectric layer, wherein the fuse comprises aluminum; forming a second dielectric layer overlying the fuse; forming a bonding pad overlying the second dielectric layer, wherein the bonding pad comprises a titanium nitride layer overlying a conductive layer; forming a third dielectric layer overlying the fuse and the bonding pad; etching the third dielectric layer to form an exposed portion of the second dielectric layer and to form an exposed portion of the titanium nitride layer, wherein the exposed portion of the second dielectric layer overlies the fuse and the conductive layer is not exposed; and etching the exposed portion of the titanium nitride layer and the exposed portion of the second dielectric layer to form an exposed portion of the conductive layer and to leave a portion of the second dielectric layer overlying the fuse, the exposed portion of the titanium nitride layer having a first etch rate and the exposed portion of the second dielectric layer having a second etch rate, wherein the second etch rate is within 20 percent of the first etch rate such that an etch selectivity of approximately 1:1 is achieved between the exposed portion of the titanium nitride layer and the exposed portion of the second dielectric layer.
8. A method for forming an integrated circuit comprising the steps of:
providing a semiconductor substrate; forming a first dielectric layer overlying the semiconductor substrate; forming a fuse overlying the first dielectric layer, wherein the fuse comprises aluminum; forming a second dielectric layer overlying the fuse; forming a bonding pad overlying the second dielectric layer, wherein the bonding pad comprises a titanium nitride layer overlying a conductive layer; forming a third dielectric layer overlying the fuse and the bonding pad; etching the third dielectric layer to form an exposed portion of the second dielectric layer and to form an exposed portion of the titanium nitride layer, wherein the exposed portion of the second dielectric layer overlies the fuse and the conductive layer is not exposed; and etching the exposed portion of the titanium nitride layer and the exposed portion of the second dielectric layer to form an exposed portion of the conductive layer and to leave a portion of the second dielectric layer overlying the fuse, the exposed portion of the titanium nitride layer having a first etch rate and the exposed portion of the second dielectric layer having a second etch rate, wherein the first etch rate and the second etch rate are substantially the same such that an etch selectivity of approximately 1:1 is achieved between the exposed portion of the titanium nitride layer and the exposed portion of the second dielectric layer.
20. A method for forming an integrated circuit comprising the steps of:
providing a semiconductor substrate; forming a first conductive layer overlying the semiconductor substrate; removing a portion of the first conductive layer to define a fuse and a conductive interconnect; forming a first dielectric layer overlying the fuse and the conductive interconnect; forming a bonding pad overlying the first dielectric layer, wherein the bonding pad comprises an anti-reflective layer overlying a second conductive layer, and wherein the bonding pad is electrically shorted to the conductive interconnect; forming a second dielectric layer overlying the fuse and the bonding pad; etching the second dielectric layer using a first etch process to form an exposed portion of the first dielectric layer and to form an exposed portion of the anti-reflective layer, wherein the exposed portion of the first dielectric layer overlies the fuse, and wherein the second conductive layer is not exposed by the first etch process; and etching the exposed portion of the anti-reflective layer and the exposed portion of the first dielectric layer using a second etch process to leave a remaining portion of the first dielectric layer overlying the fuse and to expose a portion of the second conductive layer, the exposed portion of the anti-reflective layer having a first etch rate and the exposed portion of the first dielectric layer having a second etch rate, wherein the second etch rate is within 20 percent of the first etch rate such that an etch selectivity of approximately 1:1 is achieved between the exposed portion of the anti-reflective layer and the exposed portion of the first dielectric layer.
1. A method for forming an integrated circuit comprising the steps of:
providing a semiconductor substrate; forming a first conductive layer overlying the semiconductor substrate; removing a portion of the first conductive layer to define a fuse and a conductive interconnect; forming a first dielectric layer overlying the fuse and the conductive interconnect; forming a bonding pad overlying the first dielectric layer, wherein the bonding pad comprises an anti-reflective layer overlying a second conductive layer, and wherein the bonding pad is electrically shorted to the conductive interconnect; forming a second dielectric layer overlying the fuse and the bonding pad; etching the second dielectric layer using a first etch process to form an exposed portion of the first dielectric layer and to form an exposed portion of the anti-reflective layer, wherein the exposed portion of the first dielectric layer overlies the fuse, and wherein the second conductive layer is not exposed by the first etch process; and etching the exposed portion of the anti-reflective layer and the exposed portion of the first dielectric layer using a second etch process to leave a remaining portion of the first dielectric layer overlying the fuse and to expose a portion of the second conductive layer, the exposed portion of the anti-reflective layer having a first etch rate and the exposed portion of the first dielectric layer having a second etch rate, wherein the first etch rate and the second etch rate are substantially the same such that an etch selectivity of approximately 1:1 is achieved between the exposed portion of the anti-reflective layer and the exposed portion of the first dielectric layer.
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9. The method of
10. The method of
11. The method of claims 8, wherein the step of etching the exposed portion of the titanium nitride layer and the exposed portion of the second dielectric layer is further characterized as etching the exposed portion of the titanium nitride layer and the exposed portion of the second dielectric layer in a plasma comprising oxygen, carbon, and fluorine.
12. The method of
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40. The method of
the second dielectric layer includes nitrogen; and the second dielectric layer is formed before etching the exposed portion of the anti-reflective layer.
41. The method of
the third dielectric layer includes nitrogen; and the third dielectric layer is formed before etching the exposed portion of the titanium nitride layer.
42. The method of
43. The method of
the second dielectric layer includes nitrogen; and the second dielectric layer is formed before etching the exposed portion of the anti-reflective layer.
44. The method of
the third dielectric layer includes nitrogen; and the third dielectric layer is formed before etching the exposed portion of the titanium nitride layer.
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This invention relates generally to integrated circuits, and more specifically to a method for forming fuse windows and bond pad openings in an integrated circuit.
The semiconductor industries continuing drive toward integrated circuits with ever decreasing geometries coupled with its pervasive use of highly reflective interconnect materials such as polysilicon, aluminum, refractory metals and metal silicides has led to increased photolithography patterning problems. Unwanted reflections from these underlying interconnect materials during the photoresist patterning process cause the interconnect photoresist pattern and the resulting interconnect to be distorted. This problem is further compounded when photolithographic imaging tools having ultraviolet and deep ultraviolet exposure wavelengths are used to generate the photoresist patterns.
One technique proposed to minimize reflections from an underlying reflective interconnect material is to form an anti-reflective coating over it prior to photoresist patterning. However, integration of the anti-reflective coating into the fabrication process has been problematic. For example, it has been found that bond pads formed using a titanium nitride anti-reflective coating have poor adhesion to subsequently formed wire bonds. Therefore, the titanium nitride anti-reflective coating must be removed prior to forming the wire bond to the bonding pad. Removal of this titanium nitride anti-reflective coating, however, adversely affects the formation of fuse windows on other portions of the integrated circuit. More specifically, if fuse windows and bonding pad openings are formed at the same time, then the fuse window is over etched and the underlying fuse is exposed because the titanium nitride anti-reflective coating etches at a much slower rate than does the dielectric layer overlying the fuse. Exposure of the fuse adversely effects the reliability of the integrated circuit because the fuse may corrode if it is exposed, especially if the integrated circuit uses aluminum fuses.
Accordingly a need exists for a method that reliably allows fuse windows and bond pad openings to be formed within integrated circuits.
In one embodiment, dielectric layer 14 is a layer of plasma deposited oxide which is formed using TEOS as a source gas. Alternatively, dielectric layer 14 may be a layer of silicon nitride, a layer of PSG, a layer of BPSG, an SOG layer, a silicon oxynitride layer, a polyimide layer, a low dielectric constant insulator, or a combination thereof. Dielectric layer 14 may be deposited using conventional plasma deposition techniques, chemical vapor deposition techniques, spin on coating techniques, or a combination thereof.
In one embodiment, fuse 16 and conductive interconnect 18 are formed by depositing a conductive layer comprising aluminum, such as a layer of aluminum (Al), aluminum-silicon (AlSi), aluminum-copper (AlCu), aluminum-copper-silicon (AlCuSi), or the like, onto dielectric layer 14. The conductive layer is then patterned to form fuse 16 and conductive interconnect 18. Alternatively, fuse 16 and conductive interconnect 18 may be formed using other conductive layers, such as a layer of polysilicon, polycide, copper, or the like. In addition, it should be appreciated that fuse 16 and conductive interconnect 18 can also be formed using dissimilar materials. For example, fuse 16 may be formed using a conductive layer comprising aluminum and conductive interconnect 18 may be formed using a conductive layer of copper, in which case two separate deposition and patterning steps would be used to form fuse 16 and conductive interconnect 18. Fuse 16 and conductive interconnect 18 may be forming using conventional deposition techniques, such as sputtering, chemical vapor deposition, plating, or a combination thereof, and conventional patterning techniques, such as plasma etching, chemical mechanical polishing, or a combination thereof.
It should be appreciated that conductive interconnect 18 and fuse 16 are electrically connected to semiconductor devices (not shown) that are formed on semiconductor substrate 12.
In
In
In
In
A patterned polyimide layer 34 is then formed overlying dielectric layer 32. As shown in
In
In
In one embodiment, the patterned polyimide layer 34 is then cured at a temperature of approximately 350°C C. for approximately five hours in an ambient comprising nitrogen after exposed portion 42 and exposed portion 40 have been etched. Exposed portion 44 of conductive layer 26 is then exposed to a plasma comprising oxygen in order to remove residual fluorine from the surface of conductive layer 26, which can adversely effect the adhesion between bonding pad 30 and a subsequent wire bond formed to bonding pad 30. Light from a laser is then transmitted through remaining portion 46 of dielectric layer 20 in order to melt and blow fuse 16, in order to repair defects within the integrated circuit or to program the integrated circuit. In addition, a wire bond is formed to bonding pad 30.
It should be appreciated that the present invention allows wire bonds to be reliably formed to bonding pad 30 since portion 42 of anti-reflective layer 28 is removed prior to wire bonding. In addition, the present invention also allows fuses to be reliably formed because the etch process used to remove portion 42 leaves portion 46 of dielectric layer 20 overlying fuse 16. As a result, fuse 16 is not exposed and corrosion of fuse 16 is prevented. Furthermore, since a controlled thickness of dielectric layer 20 is left overlying fuse 16 it can be reliably blown from die to die and from wafer to wafer.
Thus it is apparent that there has been provided, in accordance with the present invention, a method for forming fuse windows and bond pad openings within an integrated circuit. Although the invention has been described and illustrated with reference to specific embodiments, it is not intended that the invention be limited to these illustrative embodiments. Those skilled in the art will recognize that modifications and variations may be made without departing from the spirit and scope of the invention. Therefore, it is intended that this invention encompass all variations and modifications as fall within the scope of the appended claims.
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