A method and apparatus is provided for selecting one of a plurality of data bus width configurations of a memory device using a logic circuit. The logic circuit includes a plurality of i/O circuits each connected to at least one of a plurality of memory arrays, and at least one address selection data path connected to at least one of the i/O circuits. A signal transmitted on the address selection data path selects one of a plurality of arrays from which to access data for each i/O circuit. When in a larger bus width configuration, each of the i/O circuits is connected to a data bus line. When in a smaller bus width configuration, a subset of the i/O circuits is connected to the data bus line and data from the plurality of memory arrays is output through the subset of i/O circuits, which selectively switch outputs between memory array inputs.
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16. A memory system including a memory device having a settable bus width configuration, said memory device comprising:
a steering logic circuit for selectively outputting data from a plurality of memory arrays in at least one of first and second bus width configurations, wherein said data passes through said steering logic circuit when going from at least one of said plurality of memory arrays to at least one sense amplifier circuit; and a level translator provided between a memory array and said at least one sense amplifier circuit.
1. A logic circuit for outputting data from a memory device using one of a plurality of data bus width configurations, comprising:
a steering logic circuit for selectively outputting data from a plurality of memory arrays in at least one of first and second bus width configurations, wherein said data passes through said steering logic circuit when going from at least one of said plurality of memory arrays to at least one sense amplifier circuit; and a level translator provided between a memory array and said at least one sense amplifier circuit.
49. A method of operating a memory device with a plurality of data bus width configurations, comprising:
selectively outputting data from a plurality of memory arrays in at least one of said plurality of data bus width configurations, wherein said selective output is performed using a steering logic circuit when said data is going from at least one of said plurality of memory arrays to at least one sense amplifier circuit, wherein a level translator included in said steering logic provides a differential input signal to said at least one sense amplifier circuit, said at least on sense amplifier outputting differential data on an output data path.
34. A processor system, comprising:
a processor; and a memory system coupled to said processor through a bus system, said memory system containing a memory device having a settable bus width configuration, said memory device comprising: a steering logic circuit for selectively outputting data from a plurality of memory arrays in at least one of first and second bus width configurations, wherein said data passes through said steering logic circuit when going from at least one of said plurality of memory arrays to at least one sense amplifier circuit; and a level translator provided between a memory array and said at least one sense amplifier circuit. 50. A method of operating a memory device with a plurality of data bus width configurations, comprising:
providing a differential input signal to at least one sense amplifier circuit, said at least one sense amplifier outputting differential data on an output data path; outputting data from a first memory array through a first i/O circuit and from a second memory array through a second i/O circuit when a first bus width configuration is selected; outputting data from a selected one of said first memory array and said second memory array through said second i/O circuit when a second bus width configuration is selected; and setting said second i/O circuit to use one of said first and second data bus width configurations according to a control signal.
17. A memory system including a memory device having a settable bus width configuration, said memory device comprising:
a plurality of i/O circuits each connected to output data from at least one of a plurality of memory arrays and configurable for use with one of a plurality of data bus widths; a level translator provided in a data path of said i/O circuits; and a circuit for selectively operating said first and second i/O circuits in said first and second bus width configurations such that in said first bus width configuration said first i/O circuit outputs data from said first memory array and said second i/O circuit outputs data from said second memory array, and in said second bus width configuration said first i/O circuit does not output data and said second i/O circuit outputs data from said first and second memory arrays.
2. A logic circuit for outputting data from a memory device using one of a plurality of data bus width configurations, comprising:
a plurality of i/O circuits each connected to output data from at least one of a plurality of memory arrays and configurable for use with one of a plurality of data bus widths; a level translator provided in a data path of said i/O circuits; and a circuit for selectively operating said first and second i/O circuits in said first and second bus width configurations such that in said first bus width configuration said first i/O circuit outputs data from said first memory array and said second i/O circuit outputs data from said second memory array, and in said second bus width configuration said first i/O circuit does not output data and said second i/O circuit outputs data from said first and second memory arrays.
35. A processor system, comprising:
a processor; and a memory system coupled to said processor through a bus system, said memory system containing a memory device having a settable bus width configuration, said memory device comprising: a plurality of i/O circuits each connected to output data from at least one of a plurality of memory arrays and configurable for use with one of a plurality of data bus widths; a level translator provided in a data path of said i/O circuits; and a circuit for selectively operating said first and second i/O circuits in said first and second bus width configurations such that in said first bus width configuration said first i/O circuit outputs data from said first memory array and said second i/O circuit outputs data from said second memory array, and in said second bus width configuration said first i/O circuit does not output data and said second i/O circuit outputs data from said first and second memory arrays. 62. A memory system including a memory device having a settable width configuration, said memory device comprising:
a first and second i/O circuit, each connected to output data from at least one of a plurality of memory arrays and configurable for use with one of a first and second data bus width configurations; a circuit for selectively operating said first and second i/O circuits in said first and second bus width configurations such that in said first bus width configuration said first i/O circuit outputs data from said first memory array and said second i/O circuit outputs data from said second memory array, and in said second bus width configuration said first i/O circuit does not output data and said second i/O circuit successively outputs data from said first and second memory arrays; and a switching element for selectively operating of said first and second i/O circuits in said first and second bus width configurations in response to a selection value received on an address input data path; wherein first and second i/O circuits are interconnected such that in said second bus width configuration data from said first memory array passes through said first i/O circuit to said second i/O circuit.
64. A processor system comprising:
a processor; and a memory system coupled to said processor through a bus system, said memory system containing a memory device having a settable bus width configuration, said memory device comprising: a first and second i/O circuit, each connected to output data from at least one of a plurality of memory arrays and configurable for use with one of a first and second data bus width configurations; a circuit for selectively operating said first and second i/O circuits in said first and second bus width configurations such that in said first bus width configuration said first i/O circuit outputs data from said first memory array and said second i/O circuit outputs data from said second memory array, and in said second bus width configuration said first i/O circuit does not output data and said second i/O circuit successively outputs data from said first and second memory arrays; and a switching element for selectively operating of said first and second i/O circuits in said first and second bus width configurations in response to a selection value received on an address input data path; wherein first and second i/O circuits are interconnected such that in said second bus width configuration data from said first memory array passes through said first i/O circuit to said second i/O circuit. 3. A logic circuit as in
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The present invention relates to a method and apparatus for combining different bus-width architectures of a memory device on a single semiconductor chip and, more particularly, to selecting one of a plurality of bus width configurations of a memory device using a logic option circuit.
Memory subsystems for computers and other processor systems provide many memory devices on a common bus to allow larger storage and transmission capacities than can be obtained with a single memory device. In such systems, one or more integrated circuit chips contain the memory devices and permit connection of the memory devices to a data bus. The data bus facilitates the transmission of data between memory devices and other system components, for example a processor.
The data bus commonly consists of a finite number of data paths, the finite number usually being dubbed the "bus width." For most memory subsystems, the bus width is predetermined and fixed, meaning that each of the memory devices must be capable of transmitting and receiving data using a data bus of the predetermined bus width.
Due to the high cost of designing and developing integrated circuit chips, chip manufacturers often will design and produce a single chip having multiple architectures or configurations. Thus the same chip design may be mass-produced and used for a variety of applications, taking advantage of economies of scale and other cost-saving manufacturing techniques. For a chip of this type, after or near the end of fabrication the chip must be configured for use with its intended application.
For chips containing memory devices, a common parameter that varies between applications is the data bus width of the memory subsystem. Some exemplary memory subsystems use a data bus width of 18 bits, others 36 bits, and still others 72 bits. However, these exemplary values are not required and any number of bits may be used for the data bus width. In order to mass-produce memory devices capable of use in a variety of systems having different bus widths, chip manufacturers will often design and fabricate a single chip capable of transmitting and receiving data using one of several bus width configurations. For example, a single chip may be designed to interact with a data bus having a bus width of either 72 bits or 36 bits, depending on the way the chip is configured following fabrication.
The technique used to configure a chip capable of multiple configurations is often termed an "option." Exemplary conventional options include "bond", "via" and "metal" options. The bond, via and metal options each involve different methods of hard-wiring a memory device so that certain logic circuits and data paths are activated to cause the chip to function according to the chosen configuration. For example, a laser option may involve blowing laser fuses on the chip to activate those portions of the chip circuitry that cause the memory devices on the chip to function correctly when connected with a data bus having a width of 36 bits. As another example, a typical metal option may include depositing a small amount of conductive metal in specific locations on the chip to form electrical connections sufficient to cause the memory devices on the chip to function correctly when connected to a data bus having a width of 72 bits.
Bond, via and metal options typically involve adding gates and/or multiplexing circuits in paths where speed of data throughput is critical to the operation of the memory device. The gates and/or multiplexing units usually impose a speed penalty, making their use less desirable. Also, bond, via and metal options often are irreversible, meaning that once the decision is made to use one configuration, the chip may not thereafter be re-configured for use in a different application. In addition, via and metal options usually require that configuration decisions be made at the end of fabrication or immediately following fabrication of the chip, reducing user control of configuration options and thus reducing flexibility.
Therefore, there is a strong desire and need to develop a design for a memory device option that allows user configuration of the bus width at any time, the ability to easily reverse the option that is applied, while imposing a minimum speed penalty.
The present invention provides an apparatus and method for selecting one of a plurality of data bus width configurations of a memory device using a logic circuit. The logic circuit permits reversible selection of one of the available bus width configurations by a user or by the memory subsystem using specialized steering logic circuits and a data path for selecting among the available bus widths. This specialized steering logic circuitry may be embedded in the sense amplification circuitry of a memory device to minimize any speed penalty imposed on critical data paths.
The apparatus and method of the invention includes using a plurality of I/O circuits each connected to at least one of a plurality of memory arrays, and at least one address selection data path connected to at least one of the I/O circuits, wherein memory array data is accessed through a subset of the I/O circuits or though all of the I/O circuits, depending on the desired bus width. For a larger bus width, output paths for each of the I/O circuits are connected to bus lines of the memory system data bus. For a smaller bus width, only the output paths of a subset of the I/O circuits are connected to the bus lines of the memory system data bus.
In one aspect of the invention, a logic circuit is provided wherein a first data bus width may be used to access memory array data through the plurality of I/O circuits when a first selection signal is received on the address selection data path, and a second data bus width may be used to access memory array data through the plurality of I/O circuits when a second selection signal is received on the address selection data path.
In another aspect of the invention, a logic circuit is provided wherein each of the I/O circuits includes data paths for accessing data of more than one of the memory arrays and a select logic unit that indicates which of the more than one memory arrays should be accessed by the I/O circuit. The select logic unit includes an input select logic data path for user or system selection of which of the more than one memory arrays should be accessed by the I/O circuit.
In another aspect of the invention, a logic circuit is provided wherein the plurality of I/O circuits includes first and second I/O circuits, the first I/O circuit being connected to access data in a first memory array, the second I/O circuit being connected to access data in a second memory array or in the first memory array, the input select logic data path of the first I/O circuit selecting for output data from the first memory array and the input select logic data path of the second I/O circuit being connected to the address selection data path for selective output of data from the first memory array or the second memory array.
In another embodiment, a logic circuit is provided wherein the plurality of I/O circuits includes first and second I/O circuits, the first I/O circuit being connected to access data in a first memory array, the second I/O circuit being connected to access data in a second memory array or in the first memory array through the first I/O circuit, the input select logic data path of the first I/O circuit selecting for output data from the first memory array and the input select logic data path of the second I/O circuit being connected to the address selection data path for selective output of data from the first memory array or the second memory array. Data from the first memory array may therefore be output by the first I/O circuit or by the second I/O circuit after passing through the first I/O circuit.
In each of the embodiments described above, the first and second I/O circuits may be connected with a data bus of a fixed data bus width and the I/O circuits may be reversibly configured for use with that fixed data bus width. In a first, larger data bus width configuration, the address selection data path selects data from the second memory array for output from the second I/O circuit and both first and second I/O circuits are connected to the data bus. In a second, smaller data bus width configuration, the address selection data path sequentially selects data from the first and second memory arrays for output from the second I/O circuit, and only the second I/O circuit is connected to the data bus.
These and other advantages and features of the invention will be more clearly understood from the following detailed description which is provided in connection with the accompanying drawings in which:
The invention will now be described with reference to selecting a bus width configuration of a memory device. Conventional memory subsystems may be configured to use one or another of the available bus width configuration options using hardwired lines and multiplexers in the primary output data path, for example as shown in FIG. 1.
For example, in a conventional memory device having a bond, via or metal option, two of the circuits shown in
In the preceding example, configuration to the first, larger bus width permits the first
In the examples just discussed, multiplexers 23, 25 are provided in the output data path of the memory arrays. The multiplexers impose a penalty on the speed of data output in that, for example for a READ operation of the memory device, the time required for the data to be transmitted from the array to the output buffer may be increased due to the additional incremental delays imposed by the multiplexer circuits.
In contrast to the conventional option circuit shown in
The example shown in
The select logic units 38, 44 each have an input select logic data path. The input select logic data path of select logic unit 44 is connected to the user- or system-controlled input signal X36_Address, and the input select logic data path for select logic unit 38 is connected to ground (i.e., it is hardwired low (digital "0")). The X36_Address signal is used to select a data bus width configuration of the memory device. The select logic units 38, 44 may include simple circuit elements that translate a single input selection signal into a plurality of control signals for controlling p-channel transistors (described below in connection with FIG. 4), one per available data array.
The output signals SA0 and SA1 controls the gates of p-channel transistors (see p-channel transistors 78 described below in connection with FIG. 4). For example, when the input signal X36_Address is low (digital "0"), the output signal SA0 is deactivated low (digital "0") and the output signal SA1 is simultaneously transmitted high (digital "1"). On the other hand, when the input signal X36_Address is high (digital "1"), the output signal SA1 is deactivated low (digital "0") and the output signal SA0 is simultaneously transmitted high (digital "1").
The output data paths DO and /DO are differential signals, and hence are deactivated when the signal DO and its complement /DO are connected to each other (e.g., when the gate of the p-channel transistor 62 is not activated). The BlockSelect signal and associated circuitry are included to illustrate the differential nature of the data signals.
The level translator circuit 52 is illustrated in FIG. 4.
For example, in level converter 72a, Wien SA0 is deactivated low, the gate of p-channel transistor 78 is activated, causing the data from Array0 (data0) to be transmitted to the n-channel transistors 74, 76. Simultaneously, the gate of n-channel transistor 76 is deactivated by the low state of the SA0 signal, so the data path of Array0 is disconnected from ground. Instead, the data bits from Array0 (data0) control the gate of n-channel transistor 74. When the gate of n-channel transistor 74 is alternately activated or deactivated by the data values (digital "0" or "1") in the Array0 data (data0), a reference voltage 73 is alternately connected to or disconnected from the output data path DO. In this way, the data in the selected data path is translated from the voltage level of the array output data path to the voltage level of the reference voltage 73. The data1 data path operates in a similar manner in response to the SA1 signal. Each of the level converters 72a . . . 72d operate in this manner to convert the output data from the memory arrays (e.g., data0 and data1).
The embodiment of
The I/O circuits 31', 33' also have data paths for passing data from its respective memory array to another I/O circuit 33', 31'. For example, as shown in
In
The example shown in
Each of the I/O circuits 31', 33' is identical and includes the circuit elements shown in FIG. 6. The SAshift data path is connected to the gate of the p-channel transistors 102, 112 and, through an inverter 106, to the gate of the p-channel transistors 104, 114. Simple BlockSelect circuitry is again included to activate the output when the I/O circuit is selected for operation.
When SAshift is set low (digital "0"), the p-channel transistors 102, 112 connect the memory array data path ArrayData to the sense amplifier 54 for output to the data bus. Alternatively, when the SAshift signal is set high (digital "1"), the output of the inverter 106 causes the p-channel transistors 104, 114 to connect the "nextdoin" data path to the sense amplifier 54 for output to the data bus.
As shown in
However, also as shown in
As shown in
In another embodiment of the invention, a memory system is provided including at least one or a plurality of memory devices constructed with logic option selection circuitry which can be used to select a preferred memory subsystem data bus width configuration using the method and apparatus of the invention described above with reference to
While the invention has been described and illustrated with reference to specific exemplary embodiments, it should be understood that many modifications and substitutions can be made without departing from the spirit and scope of the invention. Accordingly, the invention is not to be considered as limited by the foregoing description but is only limited by the scope of the appended claims.
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