A prefetching control system provided for a processor. The prefetching queue may include an arbiter, a cache queue and a prefetch queue. The arbiter issues requests including read requests. Responsive to a read request, the cache queue issues a control signal. The prefetch queue receives the control signal and an address associated with the read request. When the received address is a member of a pattern of read requests from sequential memory locations, the prefetch queue issues a prefetch request to the arbiter.
|
1. A prefetch queue, comprising:
a plurality of registers, the registers comprising: a page address portion, a home address portion, a marker field comprising a plurality of flag entries, a flag entry in an intermediate position of the marker field that is to correspond to a memory location specified by the page address portion and the home address portion, and a controller. 11. A prefetch queue comprising a plurality of registers, the registers comprising:
fields to store page addresses and home addresses of stored requests, and a marker field comprising a plurality of flag positions, a base flag position that is to correspond to a memory address identified by data stored in the page address and home address fields and flag positions neighboring the base flag position that is to correspond to external memory addresses neighboring the memory address identified by data in the page address and home address fields.
14. A method, comprising:
responsive to a series of read requests from a core execution unit directed to related addresses of a memory, posting corresponding read transactions on an external bus directed to the memory, when a number of read requests in the series exceeds a first threshold, posting a prefetch read transaction on the external bus directed to a next address in the series, thereafter, for each number of new core read requests that are directed to the related addresses equal to a second threshold, posting successive prefetch read transactions on the external bus.
20. A method, comprising:
responsive to a series of read requests from a processing component directed to related addresses of a memory, posting corresponding read transactions on an external bus directed to the memory, each time a number of read requests in the series meets a first threshold, posting a prefetch read transaction on the external bus directed to a next address in the series, and after the number of read requests in the series meets a second threshold, posting successive prefetch read transactions on the external bus for each read request from the processing component.
7. A processor, comprising:
a processor core, and a bus interface unit comprising: an arbiter coupled to the processor core, an internal cache coupled to the arbiter, a transaction queue coupled to the arbiter, and a prefetch queue coupled to the arbiter, comprising: a plurality of registers, the registers comprising: a page address portion, a home address portion, a marker field comprising a plurality of flag entries, a flag entry in an intermediate position of the marker field that is to correspond to a memory location specified by the page address portion and the home address portion, and a controller. 25. A processing system, comprising:
a plurality of agents coupled by a common communication bus, at least one of the agents being a main memory system and another of the agents comprising: a processing core, a bus interface unit coupled to the processing core, and a multimodal prefetch queue coupled to the bus interface unit, to generate a prefetch request in a first mode of operation on each occurrence of a first number of core requests to related addresses of the main memory system and to generate a prefetch request in a second mode of operation on each occurrence of a second number of core requests to the related addresses of the main memory system, wherein the first number is not equal to the second number. 8. A processor comprising:
a processor core, and a bus interface unit comprising: an arbiter coupled to the processor core, an internal cache coupled to the arbiter, a transaction queue coupled to the arbiter, and a prefetch queue coupled to the arbiter, the prefetch queue comprising: a plurality of registers comprising a page address portion, a home address portion and a flag portion, and a controller to compare the page address of a newly received address from a core read request with the page address portions, if there is a match between the newly received address from a core read request and the page address portion, to compare a home address of the newly received address with the home address portion, and to mark a flag in the flag portion of the matching register that is to correspond to a proximity between the home address of the newly received address and the home address portion of the matching register, wherein, if a number of flags exceed a first predetermined threshold, the controller is to cause a prefetch request to be made to a next memory address. 2. The prefetch queue of
the controller is to compare a newly received address against the page address portions, if there is a match between the newly received address portion and the page address portion, the controller is to compare the newly received address with the home address portion of a matching register, if the newly received address differs from the contents of the home address portion of the matching register by a predetermined amount, the controller is to determine whether a number of flags set in the marker field exceeds a predetermined threshold, and if the number of flags exceeds the predetermined threshold, the controller is to identify a prefetch direction based upon a difference between the newly received address and the home address portion of the matching register.
3. The prefetch queue of
the controller is to compare a newly received address against the page address portions, and if there is a match between the newly received address portion and the page address portion, the controller is to compare the newly received address with the home address portion of a matching register and mark a flag in the flag portion of the matching register corresponding to a proximity between the newly received address and the address stored in the matching register.
4. The prefetch queue of
5. The prefetch queue of
the controller is to compare a newly received address against the page address portions, and in the absence of a match, the controller is to store portions of the address in the page address portion and the home address portion of one of the registers.
6. The prefetch queue of
the controller is to compare a newly received address against the page address portions, and if there is a match, the controller is to compare the newly received address against contents of the home address portion of a matching register, and if the newly received address differs from the contents of the home address portion of the matching register by a predetermined amount, the controller is to store a portion of the newly received address in the home address portion of the matching register and clears the flag portion thereof.
9. The processor of
the controller is to compare a newly received address against the page address portions, and in the absence of a match, the controller is to store portions of the address in the page address portion and the home address portion of one of the registers.
10. The processor of
the controller is to compare a newly received address against the page address portions, and upon a match, the controller is to compare the home address of the newly received address against the contents of the home address portions of a matching register, and if the home address of the newly received address differs from the contents of the home address portion of the matching register, the controller is to store the home address of the newly received address in the home address portion of the matching register and clears the flag portion thereof.
12. The prefetch queue of
13. The prefetch queue of
15. The method of
18. The method of
19. The method of
21. The method of
23. The method of
24. The method of
26. The processing system of
29. The processing system of
|
|||||||||||||||||||||||||||
This patent application is a continuation of U.S. application Ser. No. 10/230,289, filed Aug. 29, 2002 now U.S. Pat. No. 6,557,081; which is a continuation of U.S. application Ser. No. 09/474,012, filed Dec. 28, 1999 now U.S. Pat. No. 6,484,239; which is a continuation-in-part of U.S. patent application Ser. No. 08/999,241, entitled "Prefetch Queue," filed Dec. 29, 1997, now U.S. Pat. No. 6,216,208 is incorporated herein by reference and may benefit from the priority thereof.
The present invention relates to a prefetch queue provided for an external cache memory in a processor.
Prefetching is a known technique implemented in processor devices. Prefetching causes data or instructions to be read into the processor before it is called for by the processor's core execution unit ("core"). By having the data available within the processor when the core is ready for it, the core need not wait for the data to be read from slower external memories. Instead, the data is available to the core at the relatively higher data rates of internal buses within the processor. Because prefetching can free a core from having to wait for an external bus transaction to be completed before the core can use the requested data, prefetching can improve processor performance.
If implemented incorrectly, however, prefetching can impair processor performance. By reading data from external memories into the processor, prefetch operations occupy resources on the external bus. Due to the limited size of the core cache, prefetching may write data over other data that the processor may use. Further, prefetching may read data into the processor that may never be used. Thus, prefetching is useful only if it improves processor performance more often than it impairs such performance. Instruction streaming, a type of prefetching, occurs when a core causes data to be read sequentially from several adjacent positions in external memory. Instruction streaming suffers from the above disadvantages.
It is known that prefetching may provide significant performance improvements when a processor either executes instructions or manipulates data held in adjacent memory locations. However, no known prefetching scheme adequately distinguishes programs that perform sequential memory reads from those that perform non-sequential memory reads. Further, many processors, particularly out-of-order superscalar machines, tend to perform several interlaced sequential reads "in parallel." They may read data from sequential memory positions in a first area of memory interspersed with reads from sequential memory positions in a second area of memory. Traditional prefetching techniques do not recognize multiple streams of sequential memory reads as appropriate for prefetching.
Accordingly, there is a need in the art for a prefetch scheme that prefetches only when there exists a pattern demonstrating that performance improvements are to be obtained by prefetching. There is a need in the art for a prefetch scheme that incurs low performance costs for erroneous prefetches. Further, there is a need in the art for a prefetch scheme that detects and observes parallel prefetch operations.
Embodiments of the present invention provide a prefetch queue for an agent that can detect request patterns in both an ascending direction in memory and a descending direction in memory. Having detected a request pattern and a direction, the prefetch queue requests data from a next memory location in the direction.
Embodiments of the present invention provide a prefetch queue for an agent that can identify multiple parallel sequential read patterns from a sequence of read requests issued by an agent core. The prefetch queue also may identify read patterns directed to advancing or retreating locations in memory.
BSUs per se are known. They may include an arbiter 110, a cache memory 120, an internal queue 130, a bus queue 140 and an external bus controller 150. The arbiter 110 may receive requests from a variety of inputs 110a-e, such as from the core 200 and perhaps from other sources such as from the bus queue 140 (communication path not shown). Requests may include a request code representing the type of request being made and, where appropriate, an address identifying a memory location to which the request is directed. The arbiter 110 may prioritize the requests and may implement them in the order of priority.
The cache 120 may be an internal memory. As is known, relative to core cache memories (not shown), the cache 120 typically possesses much greater capacity. For example, a typical cache 120 may be a 128 k memory. By contrast a core data cache 210 may be a 32 k memory and a core instruction cache may be an 8 k memory. The cache 120 may be a unified cache, one that stores both instruction data and variable data (collectively, "data").
Read requests from the arbiter 110 may be input to both the cache 120 and to the internal queue 130. The cache 120 may include control logic (not shown) that can determine whether the requested data is stored in the cache 120. If so, the request is said to "hit" the cache 120. The cache 120 will furnish the requested data to the core 200 over a communication path (also not shown). Otherwise, the request is said to "miss" the cache. The cache 120 may communicate a hit or a miss to the internal queue 130 over a line 122.
The internal queue 130 may include control circuitry and buffer memory to process requests from the arbiter 110. The internal queue 130 also receives hit/miss indicators from the cache 120. If a read request hits the cache 120, the internal queue 130 permits the queued request to terminate as it advances out of the queue 130. But if a read request misses the cache 120, the request should be completed by retrieving the requested data from an external memory (not shown). In this case, when the read request advances out of the internal queue 130, the internal queue 130 causes the request to be entered in the bus queue 140.
The bus queue 140 also may include control circuitry and buffer memory. It may cause external bus transactions to be posted on the external bus 250 pursuant to queued requests issued from within the processor. The bus queue 140 may control operation of the bus 250 via an external bus controller 150. Typically, a bus protocol will have been defined for the bus 250, the bus queue 140 and external bus controller 150 may generate and receive signals in accordance with such a protocol.
In an alternate embodiment, the internal queue 130 and bus queue 140 may be replaced by a unitary queue. Accordingly,
For a read request, an external bus transaction typically causes data of a predetermined unit size to be read to the processor. For example, a single bus transaction may cause 64 bytes of data to be read to the processor. This predetermined unit size often is referred to as a "cache line." Different systems have different cache line sizes. Thus, although a processor may require data of only a portion of a cache line, the processor may read the entire cache line. From the cache line, the processor will use as much data as is required by its program flow.
An embodiment of the present invention provides a prefetch queue 160 for an agent 10. The prefetch queue 160 may monitor read requests issued by the arbiter 110 and determine whether the read requests exhibit one or more predetermined patterns. If any such pattern is identified, the prefetch queue 160 may issue a read request to be issued (a "prefetch request"). The prefetch request may be made prior to a core request for the same data. Prefetching may contribute to improved processor performance by having data stored in the internal cache 120 prior to the time the core 200 requests the data. If the data is present in the cache 120 when the core 200 needs the data, the core 200 will not be forced to wait for the data to be retrieved via the slower external bus. Instead, the core 200 can use the data immediately.
According to an embodiment of the present invention, the prefetch queue 160 may identify predetermined read patterns from the core 200. In a first embodiment, the prefetch queue 160 may monitor read requests issued by the core 200 to determine whether the requests exhibit a pattern of reads in either a forward or a backward direction or memory (i.e. N, N+1, N+2, . . . or N, N-1, N-2, . . . ). The prefetch queue 160 may detect the direction of sequential reads and orient its prefetch requests to correspond to this direction. For example, the prefetch queue 160 may cause prefetches to occur in an ascending or a descending order of memory address.
According to an embodiment, the prefetch queue 160 may identify sequential reads from a larger series of core requests. A series of sequential reads from memory may be interrupted by read requests directed to other memory addresses. Thus, for example, the prefetch queue 160 may identify a sequential read pattern from the following sequence of core read requests: A, B, A+1, C, A+2. While no sequential read pattern may be established for addresses B or C, a sequential read pattern may be detected beginning at address A. Similarly, the prefetch queue 160 may identify sequential read patterns from a sequence of core read requests directed to the following addresses A, B, A+1, B-1, A+2, B-2. In this example, sequential read patterns exist starting at address A and advancing in a forward direction in memory and also starting at address B and advancing in a backward direction in memory.
According to another embodiment, the prefetch queue 160 may be a multi-mode prefetch queue. In this embodiment, the prefetch queue 160 may operate in a first mode prior to detecting a sequential read pattern at an address. This first mode may require a first threshold number of sequential reads to be detected before the prefetch queue 160 determines to issue a prefetch request directed to a next address in the series. The prefetch queue 160 may operate in a second mode after issuing the prefetch request. In the second mode, the prefetch queue 160 may issue prefetch requests after a second, lower threshold number of sequential reads are detected. In one embodiment, in a second mode, a prefetch request may be issued each time the core requests data to a previously prefetched address.
New addresses may be input to the prefetch queue 300 from the arbiter 110 or the internal queue 130 (FIG. 1). The controller 310 may write data to various portions of the queue registers 301-309 over lines 311, 312 and 313.
As is known, external memory typically is organized into units of a predetermined size called "pages." Memory may be allocated to different uses and applications on a page-by-page basis. Each page may include a predetermined number of cache lines. For example, in a system having 4 kilobyte pages, there may be 64 cache lines of 64 bytes each. In other systems, pages and cache lines may be defined to other sizes. For the purposes of this discussion, it suffices to note that an external memory address may include a portions that identify pages and cache line positions of the address.
Within the prefetch cache 300, page ID portions 320 and home address portions 340 of the registers 301-309 may store predetermined portions of the addresses of read requests received from the BSU 100. When an address is stored in a register (say, register 301) the portion that identifies the address's page may be stored in the page ID portion 320 and the portion that identifies the position of the cache line internally to the page may be stored in the home address portion 340.
The marker field 330 in each register 301-309 may maintain a record of past core requests that were directed to locations at or near the home address. If a core request matches the page address stored in a register and is directed to a location that is sufficiently close to the home address, then a flag may be marked. A sequential read pattern may be detected based upon the content of the marker field 330 of a register.
The prefetch queue 300 also may include a mode identifying flag 350 for each register 301-309 identifying whether the address stored therein is part of a sequential read pattern. Thus, the mode identifying flag 350 may distinguish addresses that are part of active prefetches from those addresses where the prefetch queue 300 is merely searching for a read pattern.
When a received address misses the prefetch queue, the prefetch queue stores data from the newly received request in the queue. The prefetch queue may allocate a register and write the page address and cache address portions of the received address into respective page and home address portions of the allocated register speculatively (Step 1030). The prefetch queue may identify a prefetch direction as forward (Step 1040). The prefetch queue also may initialize the flag portion of the allocated register speculatively (Step 1050). Further, the prefetch queue may indicate that no prefetch pattern has been identified for the newly stored address (Step 1060).
If, at Step 1020, the newly received address hit the page queue, the prefetch queue determines whether the address falls within a predetermined range of the address stored in the home address field of the matching register (Step 1070). If so, the prefetch queue marks a corresponding flag in the marker field (Step 1080). The prefetch queue may determine whether the number of flags in the marker field exceeds a threshold number (Step 1090). If so, the prefetch queue may issue a prefetch request (Step 1100). The prefetch queue also may determine whether the matching register, the register that caused the match with the newly received address, has been marked as operating in an active prefetch mode (Step 1110). If not, the prefetch queue may conclude the method for a present iteration of processing (Step 1120). The prefetch queue also may conclude the method if, at step 1090, it was determined that the number of flags did not exceed the threshold number.
If the prefetch queue is operating in an active prefetch mode, the prefetch queue may shift the home address (Step 1130). This simply may require that a home address portion of the newly issued prefetch be written to the home address field of the matching register. The prefetch queue also may reinitialize the marker field, clearing all flags except the flag corresponding to the home address itself (Step 1140). Thereafter, the current iteration of the method may conclude (Step 1120).
At step 1070, if the newly received address does not match the home address field, the prefetch queue determines whether the number of flags in the marker field of the matching register exceeds a threshold (Step 1150). If so, the prefetch queue may set the mode to "active prefetch" (Step 1160). The prefetch queue also may determine whether the home address portion of the newly received address is higher or lower than the address stored in the home address portion of the matching register (Step 1170). If lower, the prefetch queue changes the prefetch direction to backward (Step 1180). Otherwise, the default direction may remain. Thereafter, the prefetch queue may write the newly received address to the home address field and prefetch ahead of the new home address (Steps 1190-1200). The method may reinitialize the marker field (Step 1140) and conclude.
If, at step 1150, the number of flags does not exceed the threshold, the prefetch queue may advance to step 1040, write the home address portion in the home address field of the register, reinitialize the marker field and set the mode as "search for pattern."
In an embodiment, the controller 310 of
In another embodiment, the prefetch queue may operate the method 1000 independently for each register 301-309. Thus, a first register 301 may be designated as operating in a "search for pattern" mode while a second register 302 may be operating in an active "prefetch mode." This independence permits the prefetch queue 300 to detect multiple independent read sequences from the core even if the core read requests from the sequence are interspersed with other requests that are not in the sequence. This property permits the prefetch queue to acquire multiple independent read sequences from the core.
Optionally, the method 1000 may be tailored to address certain boundary conditions that may arise during operation. For example, following step 1150, if the number of flags does not exceed the threshold, the prefetch queue may determine if the request hit the internal cache 120 (FIG. 1). If not, it represents a likely synchronization error between the core and the prefetch queue. In response the prefetch may advance to step 1040 and reset the matching register. Otherwise, it may advance to step 1120 as shown in FIG. 3.
In an embodiment, the prefetch queue may condition operation of steps 1030-1060 on whether the read request hit the internal cache 120 (Step 1210). In such an embodiment, if the request hits the internal cache, the method 1000 may conclude (step not shown). Otherwise, steps 1030-1060 would be performed.
Consider the prefetch queue in operation with respect to a sequence of core requests beginning at an address A. When the first address in the sequence is input to the prefetch queue, the prefetch queue may traverse steps 1030-1060 and write the newly received address to a new queue entry. Thereafter, the core may issue further requests in the sequence that cause flags to be set in the marker field (Step 1080) but are insufficient to raise the total number of flags to pass the threshold of step 1090. For example, if the threshold were set to three, a core request to address A+1 would cause the threshold test to fail. The prefetch queue would perform steps 1070-1090 and conclude.
Eventually, the core may issue enough requests to pass the threshold of step 1090. Using the above example, when the prefetch queue receives a core request to address A+2, a third bit may be set in the marker field. The flags may pass the threshold of Step 1090 and the prefetch queue may issue a prefetch request. In this iteration, the prefetch queue may prefetch an address at A+4. This is appropriate because the core read request to A+2, by virtue of an associated blind prefetch, may cause data at addresses A+2 and A+3 to be read to the agent. After the prefetch, however, because the prefetch queue has not advanced to active prefetch mode, the prefetch queue would conclude the present iteration of the method.
When the prefetch queue receives a core request to address A+3, the prefetch queue again may progress through steps 1070-1110. The prefetch queue may issue a prefetch request to address A+5. Because data at address A+5 may have been read to the agent as part of a blind prefetch associated with the prefetch request A+4, the prefetch request may hit the internal cache 120 (FIG. 1). It need not generate an external bus transaction.
When the prefetch queue receives a core read request to address A+4, the address may hit the page queue but miss the home address queue. In this case, the prefetch queue may advance through steps 1150-1190. The prefetch queue switches modes (to active prefetch mode) and determines the prefetch direction. In this example, the direction does not change; it remains designated as "forward." The prefetch queue also writes A+4 to the home address and prefetches based upon it. In this example, the prefetch queue prefetches to address A+6. Thereafter, additional core read requests in the sequence may cause the prefetch queue to traverse steps 1070-1140.
According to an embodiment, the method 1000 may employ a different threshold at step 1090 when the marker field of a register indicates that the prefetch queue is searching for a pattern than when the marker field indicates that an active prefetch is underway. In the example above, three flags were required for a first prefetch to be made. When an active prefetch is underway, it may be appropriate to lower the required number of flags. Thus, using the foregoing example, the threshold may be dropped to one. This would cause a prefetch to be issued every time a new core request "touched" the marker field.
According to another embodiment, the method 1000 may test only a portion of the marker field during an active prefetch. As shown in
According to a further embodiment, the method 1000 may prefetch two cache lines ahead of the newly received address that caused the prefetch. Such an embodiment is appropriate for use with systems that augment the prefetch request to with a blind prefetch to an adjacent memory location (reading data three cache lines ahead of the newly received address).
The discussion of the foregoing embodiments presents the prefetch queue operating in a physical address space, where external memory locations are addressed by page and cache line locations. Note that the principles of the present invention transcend this specific embodiment. The prefetch queue may be applied to other embodiments using other addressing schemes. For example, the prefetch queue may be applied to a virtual address space where memory is addressed by an object identifier and an offset representing a location within memory. Such an embodiment would include an object ID queue in place of a page queue and an offset queue instead of a home queue. Notwithstanding these modifications, the principles of the present invention find application in such a scheme.
Several embodiments of the present invention are specifically illustrated and described herein. However, it will be appreciated that modifications and variations of the present invention are covered by the above teachings and within the purview of the appended claims without departing from the spirit and intended scope of the invention.
Hill, David L., Prudvi, Chlnna B.
| Patent | Priority | Assignee | Title |
| 6959374, | Jan 29 2003 | Oracle America, Inc | System including a memory controller configured to perform pre-fetch operations including dynamic pre-fetch control |
| 7055016, | Apr 30 2003 | Oracle America, Inc | Computer system including a memory controller configured to perform pre-fetch operations |
| 7975108, | Mar 25 2004 | Intellectual Ventures Holding 81 LLC | Request tracking data prefetcher apparatus |
| 9092336, | Mar 15 2013 | SanDisk Technologies LLC | Write admittance policy for a memory cache |
| 9483404, | Mar 15 2013 | SanDisk Technologies LLC | Write admittance policy for a memory cache |
| Patent | Priority | Assignee | Title |
| 5093777, | Jun 12 1989 | Intel Corporation | Method and apparatus for predicting address of a subsequent cache request upon analyzing address patterns stored in separate miss stack |
| 5371870, | Apr 24 1992 | HEWLETT-PACKARD DEVELOPMENT COMPANY, L P | Stream buffer memory having a multiple-entry address history buffer for detecting sequential reads to initiate prefetching |
| 5586294, | Mar 26 1993 | HEWLETT-PACKARD DEVELOPMENT COMPANY, L P | Method for increased performance from a memory stream buffer by eliminating read-modify-write streams from history buffer |
| 5701426, | Mar 31 1995 | Bull Information Systems Inc.; BULL HN INFORMATIONS SYSTEMS INC | Data processing system and method using cache miss address prediction and forced LRU status in a cache memory to improve cache hit ratio |
| 5740399, | Aug 23 1995 | International Business Machines Corporation | Modified L1/L2 cache inclusion for aggressive prefetch |
| 5761706, | Nov 01 1994 | Hewlett Packard Enterprise Development LP | Stream buffers for high-performance computer memory system |
| 5958040, | May 28 1997 | Hewlett Packard Enterprise Development LP | Adaptive stream buffers |
| 6275918, | Mar 16 1999 | International Business Machines Corporation | Obtaining load target operand pre-fetch address from history table information upon incremented number of access indicator threshold |
| Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
| Apr 01 2003 | Intel Corporation | (assignment on the face of the patent) | / |
| Date | Maintenance Fee Events |
| May 26 2004 | ASPN: Payor Number Assigned. |
| Nov 23 2007 | M1551: Payment of Maintenance Fee, 4th Year, Large Entity. |
| Sep 21 2011 | M1552: Payment of Maintenance Fee, 8th Year, Large Entity. |
| Dec 31 2015 | REM: Maintenance Fee Reminder Mailed. |
| May 25 2016 | EXP: Patent Expired for Failure to Pay Maintenance Fees. |
| Date | Maintenance Schedule |
| May 25 2007 | 4 years fee payment window open |
| Nov 25 2007 | 6 months grace period start (w surcharge) |
| May 25 2008 | patent expiry (for year 4) |
| May 25 2010 | 2 years to revive unintentionally abandoned end. (for year 4) |
| May 25 2011 | 8 years fee payment window open |
| Nov 25 2011 | 6 months grace period start (w surcharge) |
| May 25 2012 | patent expiry (for year 8) |
| May 25 2014 | 2 years to revive unintentionally abandoned end. (for year 8) |
| May 25 2015 | 12 years fee payment window open |
| Nov 25 2015 | 6 months grace period start (w surcharge) |
| May 25 2016 | patent expiry (for year 12) |
| May 25 2018 | 2 years to revive unintentionally abandoned end. (for year 12) |