The invention is a storage cell capacitor and a method for forming the storage cell capacitor having a storage node electrode having a barrier layer interposed between a conductive plug and an oxidation resistant layer. A thick insulative layer protects the sidewalls of the barrier layer during the deposition and anneal of a dielectric layer having a high dielectric constant. The method comprises forming the conductive plug in a thick layer of insulative material such as oxide or oxide/nitride. The conductive plug is recessed from a planarized top surface of the thick insulative layer. The barrier layer is then formed in the recess. The process is continued with a formation of a second insulative layer, a potion of which is removed to form an opening exposing a portion of the barrier layer. An oxidation resistant conductive layer is deposited in the recess and forms at least a portion the storage node electrode of the capacitor. Next a dielectric layer having a high dielectric constant is formed to overly the storage node electrode and a cell plate electrode is fabricated to overly the dielectric layer.
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9. A method of fabricating a capacitor electrode, comprising:
forming a first insulative layer overlying a substrata, with the first insulative layer having a thickness and an opening exposing a portion of the substrate; forming a contact plug within the opening and contacting the substrate, with the contact plug having a height less than the thickness of the first insulative layer to define a recess; and forming a barrier layer within the recess.
17. A method of fabricating a capacitor electrode, comprising:
forming a first insulative layer overlying a substrate, with the first insulative layer having a thickness and having an opening exposing a portion of the substrate; forming a contact plug within the opening and contacting the substrate, with the contact plug having a height less than the thickness to define a recess; forming a first barrier layer within the recess and contacting the contact plug; and forming second barrier layer within the recess and contacting the first barrier layer.
1. A method of fabricating a capacitor electrode, comprising:
forming a first insulative layer overlying a substrate; forming a contact ping contacting the substrate; forming a baffler layer in the first insulative layer and overlying the contact plug, with the barrier layer comprising first and second sublayers having different material compositions; forming a second insulative layer overlying the first insulative layer and the barrier layer; and recessing an oxidation resistant material in the second insulative layer and in contact with the barrier layer, with the oxidation resistant material, the barrier layer and the contact plug defining a first electrode of the capacitor.
26. A method of making a capacitor electrode, comprising:
providing a storage node area at least partly bounded by a doped region of a substrate, and first and second insulative spacers; forming a silicon oxide layer over the doped region and between the first and second insulative spacers, with the silicon oxide layer having a thickness greater than respective heights of the insulative spacers; planarizing the silicon oxide layer; removing a portion of the third silicon oxide layer to expose a portion of the doped region of the substrate within the storage node area; forming a polysilicon contact plug in contact with the exposed portion of the doped region of the substrate, with the contact plug having a height less than that of the silicon oxide layer to define a recess; forming a titanium silicide layer on the polysilicon contact plug and within the recess; and forming a titanium nitride layer on the titanium suicide layer and within the recess.
29. A method of making a capacitor electrode, comprising:
providing a storage node area at least partly bounded by a doped region of a substrate, a first insulative spacer attached to a wordline and second insulative spacer attached to a gate stack; forming an silicon oxide layer over the wordline, the gate stack, and the storage node area, with the silicon oxide layer having a thickness greater than respective heights of the wordline and the gate stack; planarizing the silicon oxide layer; removing a portion of the silicon oxide layer to expose a portion of the doped region of the substrate within the storage node area; forming a polysilicon contact plug in contact with the exposed portion of the doped region of the substrate, with the contact plug being substantially flush with the silicon oxide layer; removing a portion of the polysilicon contact plug to define a recess overlying the storage node area; forming a titanium suicide layer on the polysilicon contact plug and within the recess; and forming a titanium nitride layer on the titanium suicide layer.
2. The method of
forming an opening in the second insulative layer, with the opening exposing a portion of the barrier layer; and forming a layer of the oxidation resistant material within the opening, with the layer of the oxidation resistant material having a thickness less than that of the second insulative layer.
4. The method of
5. The method of
forming a layer including at least one of a metal nitride or a metal suicide; and forming a layer including refractory metals, conductive metal oxides, or metal nitrides.
6. The method of
depositing titanium on the contact plug; annealing the deposited titanium and the contact plug in a nitrogen atmosphere to form a titanium layer, a nitride layer and a titanium silicide layer; and removing the titanium nitride layer and the nitride layer.
7. The method of
8. The method of
12. The method of
13. The method of
forming a layer including at least one of a metal nitride or a metal silicide; and a layer including refractory metals, conductive metal oxides, or metal nitrides.
14. The method of
depositing titanium nitride within the opening and over the first insulative layer; and planarizing the deposited titanium nitride to form a layer of titanium nitride substantially flush with the first insulative layer.
15. The method of
16. The method of
18. The method of
19. The method of
20. The method of
21. The method of
wherein forming the first barrier layer comprises forming a layer including at least one of a metal nitride or a metal silicide; and wherein forming the second barrier layer comprises forming a layer including refractory metals, conductive metal oxides, or metal nitrides.
22. The method of
forming a second insulative layer over the second barrier layer; and recessing an oxidation resistant material in the second insulative layer.
23. The method of
forming an opening in the second insulative layer, with the opening exposing a portion of the second barrier layer; and forming a layer of the oxidation resistant material within the opening, with the layer of oxidation resistant material having a thickness less than that of the second insulative layer.
25. The method of
27. The method of
oxidizing a silicon substrate to define at least one field oxide region; forming a first silicon oxide layer on the silicon substrate and adjacent the one field oxide region; forming a conductively doped polysilicon layer over the silicon oxide layer and the field oxide region; forming a metal silicide layer over the conductively doped polysilicon layer and the field oxide region; forming a second silicon oxide layer over the metal suicide layer; forming a nitride layer over the second silicon oxide layer; removing portions of the first silicon oxide layer, the conductively doped polysilicon layer, the metal silicide layer the second silicon oxide layer, and the nitride layer to define a wordline over the field oxide region and a gate stack on the substrate adjacent the field oxide region, with the wordline having a first wall confronting a second wall of the gate stack; doping a region of the substrate between the first and second walls; forming the insulative spacers on the first and second walls to define the storage node area between the first and second walls and over the doped region of the substrate.
28. The method of
forming another silicon oxide layer over the titanium nitride layer; and recessing an oxidation resistant material in the other silicon oxide layer.
30. The method of
oxidizing a silicon substrate to define at least one field oxide region; forming a first silicon oxide layer on the silicon substrate and adjacent the one field oxide region; forming a conductively doped polysilicon layer over the silicon oxide layer and the field oxide region; forming a metal suicide layer over the conductively doped polysilicon layer and the field oxide region; forming a second silicon oxide layer over the metal silicide layer; forming a nitride layer over the second silicon oxide layer; removing portions of the first silicon oxide layer, the conductively doped polysilicon layer, the metal silicide layer, the second silicon oxide layer, and the nitride layer to define a wordline over the field oxide region and a gate stack on the substrate adjacent the field oxide region, with the wordline having a first wall confronting a second wall of the gate stack; doping a region of the substrate between the first and second walls; forming insulative spacers on the first and second walls to define the storage node area between the first and second walls and over the doped region of the substrate.
31. The method of
forming another silicon oxide layer over the titanium nitride layer; and recessing an oxidation resistant material in the other silicon oxide layer.
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This application is a Continuation of U.S. Ser. No. 09/357,634, filed Jul. 20, 1999 now U.S. Pat. No. 6,495,427, which is a Continuation of U.S. Ser. No. 08/314,117, filed Sep. 27. 1994, now U.S. Pat. No. 6,066,528 which is a Divisional of U.S. Ser. No. 08/104,524, filed Aug. 10. 1993, now U.S. Pat. No. 5,392,189, which is a Continuation-In-Part of U.S. Ser. No. 08/044,331, filed Apr. 2, 1993, now abandoned.
This invention pertains to semiconductor technology, and more particularly to storage cell capacitors for use in dynamic random access memories.
As memory devices become more dense it is necessary to decrease the size of circuit components. One way to retain the storage capacity of a dynamic random access memory (DRAM) device and decrease its size is to increase the dielectric constant of the dielectric layer of the storage cell capacitor. In order to achieve the charge storage efficiency needed in 256 megabit (Mb) memories and above, materials having a high dielectric constant, typically greater than 50, can be used as the dielectric layer between the storage node and the cell plate capacitor electrodes. The dielectric constant is a value characteristic of a material and is proportional to the amount of charge that can be stored in the material when it is interposed between two electrodes. BaxSr(1-x)TiO3 [BST], BaTiO3, SrTiO3, PbTiO3, Pb(Zr,Ti)O3 [PZT], (Pb,La)(Zr,Ti)O3 [PLZT], (Pb,La)TiO3 [PLT], KNO3, and LiNbO3 are among some of the high dielectric constant materials that can be used in this application. These materials have dielectric constant values above 50 and will likely replace the standard Si3N4, SiO2/Si3N4, Si3N4/SiO2, or SiO2/Si3N4/SiO2 composite films used in 256 kilobits (Kb) to 64 megabits (Mb) generations of DRAMs. Si3N4 and SiO2/Si3N4 composite films have dielectric constant values of 7 or less. The storage node and cell plate electrodes are also referred to as first and second electrodes.
Unfortunately high dielectric constant materials are incompatible with existing processes and can not be simply deposited on a polysilicon electrode as was the case for the lower dielectric constant materials, such as Si3N4 and SiO2/Si3N4 composite layers. This incompatibility is a result of the O2 rich ambient present during the high dielectric constant material deposition or during annealing steps. The O2 oxidizes portions of the materials formerly used for the storage node plate. Also the capacitors employing the former materials undergo physical degradation during thermal cycles due to the diffusion of the storage node plate material into the dielectric.
In the storage cell capacitor incorporating BST, described in the IDEM-91 article entitled, A STACKED CAPACITOR WITH (BaxSr1-x)TiO3 FOR 256M DRAM by Koyama et al., some of these aforementioned problems are resolved. The storage node electrode typically comprises a layer of platinum overlying a tantalum barrier layer which, in turn, overlies a polysilicon plug. Platinum is used as the upper portion of the first electrode since it will not oxidize during a BST deposition or subsequent anneal. An electrode that oxidizes would have a low dielectric constant film below the BST, thereby negating the advantages provided by the high dielectric constant material. The tantalum layer is introduced to avoid Si and Pt inter-diffusion and to prevent the formation of SiO2 on top of the platinum surface. In addition, the platinum protects the top surface of the tantalum from strong oxidizing conditions during the BST deposition.
The sidewalls 4 of the tantalum film 1 formed during this process are subject to oxidation during the subsequent deposition of the BST layer. Since the tantalum 1 oxidizes, the polysilicon plug 3 is also susceptible to oxidation. When portions of the polysilicon plug 3 and tantalum 1 are consumed by oxidation the capacitance of the storage cell capacitor is decreased since the storage node electrode is partially covered by a low dielectric constant film. Therefore the memory device cannot be made as dense.
In addition, the storage node contact resistance increases drastically between the polysilicon plug and the tantalum barrier layer as a result of degradation of the tantalum barrier layer during deposition of BST and other high dielectric constant materials.
An object of the invention is to increase density of a memory device by increasing capacitance of storage cell capacitors.
A further object of the invention is decreased contact resistance between the polysilicon electrode and the barrier layer and reduced degradation of the barrier layer.
The storage cell capacitor of the invention features a storage node electrode having a barrier layer which prohibits the diffusion of atoms. The barrier layer may be titanium nitride or another material which prohibits silicon diffusion. The barrier layer is interposed between a conductive plug and a non-oxidizing conductive material, typically platinum. A dielectric layer, typically BaxSr(1-x)TiO3 [BST], is deposited on the non-oxidizing material. The barrier layer is surrounded on its sides and exposed upper portions by one or more insulative layers.
The insulative layers and the non-oxidizing material protect the barrier layer from oxidizing during the deposition and anneal of the BST thereby also eliminating oxidation of the conductive plug. By eliminating oxidation of the barrier layer and oxidation of the conductive plug, capacitance is maximized, and the contact resistance is not affected.
Optionally, the invention also features a low contact resistance material lying between the conductive plug and the barrier layer.
The invention is a storage node capacitor and a method for forming the storage node capacitor having a storage node electrode comprising a barrier layer interposed between a conductive plug and an oxidation resistant conductive layer. The method comprises forming the conductive plug in a thick first layer of insulative material such as oxide or oxide/nitride. The conductive plug is recessed from a planarized top surface of the first insulative layer. The optional low contact resistance material is formed at the base of the recess. The barrier layer is then formed in the recess.
Next a second layer of insulative material is formed overlying the first layer of insulative material and optionally overlying a portion of the barrier layer. The process is continued with a formation of an oxidation resistant conductive layer overlying the barrier layer not covered by the second insulative layer.
Next a dielectric layer, typically having a high dielectric constant, is formed to overly the oxidation resistant conductive layer and a further conductive layer is fabricated to overly the dielectric layer.
Since the barrier layer is protected during the formation of the dielectric layer by both the oxidation resistant conductive layer and the thick insulative layer there is no oxidation of the barrier layer or the contact plug, thereby maximizing capacitance of the storage node and reducing high contact resistance issues.
The method for fabricating the storage cell capacitor of the invention is shown pictorially in
Referring to
The formation of the FETs 22 and wordlines 21 as described are exemplary of one application to be used in conjunction with the present embodiment of the invention. Other methods of fabrication and other applications are also feasible and perhaps equally viable.
In
In general, CMP involves holding or rotating a wafer of semiconductor material against a wetted polishing surface under controlled chemical slurry, pressure, and temperature conditions. A chemical slurry containing a polishing agent such as alumina or silica may be utilized as the abrasive medium. Additionally, the chemical slurry may contain chemical etchants. This procedure may be used to produce a surface with a desired endpoint or thickness, which also has a polished and planarized surface. Such apparatus for polishing are disclosed in U.S. Pat. Nos. 4,193,226 and 4,811,522 which are herein incorporated by reference. Another such apparatus is manufactured by Westech Engineering and is designated as a Model 372 Polisher.
At this juncture buried digit lines may be fabricated as described in U.S. Pat. No. 5,168,073 herein incorporated by reference. In the case where the buried digit lines are formed by the method described in U.S. Pat. No. 5,168,073 an initial thick oxide layer is deposited and planarized and then overlaid with a relatively thick Si3N4 layer which is also planarized. These two layers serve the same function as the oxide layer 40 and may be used in place of oxide layer 40 even in the case where buried digit lines are not formed. When buried digit lines are formed the thick oxide is typically deposited prior to the digit line formation and the Si3N4 is deposited subsequent to the digit line formation. In the case where the thick insulative layer is comprised only of oxide it is possible for oxygen to diffuse through the oxide. By overlying the oxide with Si3N4 it is possible to prohibit oxygen diffusion though the oxide.
Referring to
Referring to
Referring now to
Referring now to
In addition to titanium other refractory metals may be used. These refractory metals may be chosen from the list of refractory metals comprising W, Co, Ta, and Mo.
Alternately a metal nitride, such as TiN, may be deposited instead of a refractory metal. The refractory metal and the metal nitride are both capable of reacting with the polysilicon plug to form a silicide during an anneal.
Referring now to
Referring to
Referring to
At this juncture the invention can take alternate paths. By following one path a crown type storage node capacitor is formed, and by following the second path a planar type storage node capacitor is formed.
Referring to
Referring to
Since the titanium nitride layer 75 is recessed in the oxide layer 40, a thick layer of platinum may be deposited thereby increasing the capacitive area as a result of sidewall contribution. This is accomplished without decreasing the density of the device.
In
In
Referring to
By using a very thick second insulative layer 83 thick platinum electrodes are fabricated, and the capacitance area is increased by the sidewall area contribution. Therefore, the second insulative layer is deposited from at least a thickness of 0.2 micro meters to a thickness of 1.0 micro meters.
Referring to
A very thick second insulative layer 83 increases the sidewall area contribution thereby increasing capacitance. This can be seen by examination of the embodiments of the invention depicted in
The storage node plate of storage node capacitors 89 and 92 can be thought of as comprising just the platinum portion 85 or a combination of the platinum portion 85, the titanium nitride layer 75, the titanium silicide layer 67, and the polysilicon plug 65. Some people like to think of the polysilicon plug as an electrical interconnect to the substrate rather than as a portion of the storage node electrode.
Referring to
Referring to
Referring to
The cell plate layer is formed with the sputter or CVD of a 50 to 200 nm thick cell plate layer 91, 115. The cell plate layer 91, 115 is typically Platinum, TiN or some other conductive material.
Among the suitable materials for a dielectric layer having a high dielectric constant are BaxSr(1-x)TiO3 [BST], BaTiO3, SrTiO3, PbTiO3, Pb(Zr,Ti)O3 [PZT], (Pb,La)(Zr,Ti)O3 [PLZT], (Pb,La)TiO3 [PLT], KNO3, and LiNbO3. In the applicant's invention BST is the preferred material and is deposited at a thickness range of 30 nm-300 nm by RF-magnetron sputtering or deposited by chemical vapor deposition (CVD) in a vapor environment within a temperature range of 200 to 800 degrees Celsius. The actual vapor environment and temperature may vary for the specific dielectric being deposited. These variations are well known to those skilled in the art.
The titanium nitride layer 75 is not oxidized during the application of a high temperature anneal due to the fact that it is protected on its sidewalls by the first insulative layer and that it is protected on its upper surface by the platinum layer and the second insulative layer. Therefore even after the formation of the dielectric layer the recess retains the original titanium nitride 75 formed therein and capacitance is not sacrificed as it would be when portions of the titanium nitride 75 are consumed by oxidation. Therefore capacitance is effectively increased over methods where portions of titanium nitride are oxidized.
The process can be continued or modified to accommodate the steps described in U.S. Pat. No. 5,168,073, previously incorporated by reference, for providing electrical interconnection between a plurality of capacitors thus formed.
By utilizing the method of the preferred embodiments of the invention, a high density memory device is provided featuring a capacitor formed in a compact area as a result of a dielectric layer having a high dielectric constant. The method of the invention provides retention of storage node integrity during an anneal of the dielectric layer and allows for the deposition a very thick platinum layer as a portion of the first electrode.
Although alternate processes have been described for forming the storage cell capacitor it is apparent the processes are equally applicable for the fabrication of other types of capacitors. It should also be apparent to one skilled in the art that changes and modifications may be made to such things as deposition depths, deposit methods, removal methods and the like without departing from the spirit and scope of the invention as claimed.
Sandhu, Gurtej S., Fazan, Pierre C.
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