An apparatus for generating two signals having a predetermined spacing between mutually corresponding signal edges includes first and second delay devices for delaying a clock signal and a complementary clock signal in response to respective first and second control signals. A first control signal generator generates the first control signal on the basis of the clock signal and the delayed clock signal. A second control signal generator generates the second control signal on the basis of the delayed clock signal and the delayed complementary clock signal. The second control signal generator causes the delayed clock signal and the delayed complementary clock signal to have a steady-state condition in which mutually corresponding edges thereof are separated by a pre-determined spacing.
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14. A method comprising:
delaying a clock signal in response to a first control signal, thereby generating a delayed clock signal therefrom; generating a first control signal on the basis of the clock signal and the delayed clock signal; delaying a complementary clock signal in response to a second control signal, thereby generating a delayed complementary clock signal therefrom; generating a second control signal on the basis of the delayed clock signal and the delayed complementary clock signal, the second control signal being selected to cause the delayed clock signal and the delayed complementary clock signal to have a steady-state condition in which mutually corresponding edges thereof are separated by a pre-determined spacing.
1. An apparatus comprising:
a first delay device for delaying a clock signal in response to a first control signal, thereby producing a delayed clock signal; a first control signal generator configured to generate the first control signal on the basis of the clock signal and the delayed clock signal; a second delay device for delaying a complementary clock signal in response to a second control signal, thereby producing a delayed complementary clock signal; and a second control signal generator for generating the second control signal on the basis of the delayed clock signal and the delayed complementary clock signal, the second control signal generator being configured to cause the delayed clock signal and the delayed complementary clock signal to have a steady-state condition in which mutually corresponding edges thereof are separated by a pre-determined spacing.
21. An apparatus for generating a first signal and a second signal separated from the first signal by a selected interval, the apparatus comprising:
a first delay device for delaying a clock signal by an interval controlled by a first control signal, thereby producing a delayed clock signal; a second delay device for delaying a complementary clock signal by an interval controlled by a second control signal, thereby producing a delayed complementary clock signal; a first control signal generator disposed to receive the clock signal and the delayed clock signal, the first control signal generator being configured to generate the first control signal on the basis of a phase difference between the clock signal and the delayed clock signal; a second control signal generator disposed to receive the delayed clock signal and the delayed complementary clock signal, the second control signal generator including means for generating the second control signal on the basis of a phase difference between the delayed clock signal and the delayed complementary clock signal.
2. The apparatus of
3. The apparatus of
a first signal generator in communication with the first delay device and the first control signal generator, the first signal generator being configured to generate the clock signal in response to an external clock signal generated external to the apparatus, and a second signal generator in communication with the second delay device, the second signal generator being configured to generate the complementary clock signal in response to an external complementary clock signal generated external to the apparatus.
4. The apparatus of
a phase detector configured to generate a phase signal indicative of a phase difference between the clock signal and the delayed clock signal; and a charge pump for generating the first control signal in response to the phase signal.
5. The apparatus of
6. The apparatus of
7. The apparatus of
8. The apparatus of
9. The apparatus of
first and second switches controlled by an output of the duty ratio detector; and a capacitor configured to store a charge that depends on states of the first and second switches.
10. The apparatus of
11. The apparatus of
12. The apparatus of
13. The apparatus of
15. The method of
16. The method of
delaying a clock signal comprises delaying a clock signal derived from an externally generated clock signal, and delaying a complementary clock signal comprises delaying a complementary clock signal from an externally generated complementary clock signal.
17. The method of
18. The method of
a first level at intervals between a rising edge of the delayed clock signal and a rising edge of the delayed complementary clock signal, and that is at a second level at intervals between a rising edge of the delayed complementary clock signal and a rising edge of the delayed clock signal.
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The present invention relates to a method and an apparatus for generating two signals with a pre-determined spacing between mutually corresponding signal edges.
This application claims the benefit of the Mar. 28, 2002 priority date of German application DE 102.14.304.8-53, the contents of which are herein incorporated by reference.
Semiconductor devices, such as, for example, DRAM memory devices or other microelectronic apparatuses, are generally provided with delay locked loops (DLLs) in order to synchronize the data output with an external clock signal, or bring them in phase with one another.
In the so-called double data rate scheme, a data bit is driven with the rising clock edge and a data bit is driven with the falling clock edge. If the duty ratio (duty cycle) is assumed to be 0.5, i.e. the HIGH level of the clock signal has the same length as the LOW level of the clock signal, the maximum bit duration amounts to half of the clock period in the double data rate scheme (DDR). However, the clock typically does not have a precise duty ratio of 50%. If the data are then simply driven by the edges, this leads to a shift in the length of the bit duration, i.e. the period of time in which the data are valid.
In order to improve the uniformity of the bit duration, duty ratio correction circuits have been proposed in the past. The aim of a duty ratio correction circuit is to provide a clock on a chip with a duty ratio of 0.5 even if an imprecise external clock signal having a duty ratio that deviates from this is present. However, the previously known methods are difficult to implement and consume a large amount of current, such as e.g. in a DLL with a differential current mode in which the crossover point of the internal clocks is shifted by adding an analog current onto for example the true, but not the complementary, clock path.
An architecture that is already used in delay locked loops (DLLs) has two delay lines in order to eliminate the sensitivity to propagation delay differences between the rising and falling clock edges.
Consequently, with an apparatus according to
The control signal of the delay device 5 (delay line) is generated in a conventional manner by locking the phase of the delayed internal clock signal 11 with the received clock signal 3 and the use of a pump device 6 in accordance with
It is an object of the present invention to provide a method for generating two signals with a pre-determined spacing between the mutually corresponding signal edges and a corresponding apparatus whereby it is possible to correct an imprecise duty ratio of an external clock signal to a precise internal clock signal with a duty ratio of, in particular, 0.5.
According to the invention, this object is achieved by means of the apparatus for generating two signals with a predetermined spacing between the mutually corresponding signal edges as specified in claim 1 and by means of the method according to claim 11.
The idea underlying the present invention consists in shifting an internal clock signal and a shifted internal clock signal with respect to one another in such a way that, in particular, the rising edges of the internal clock signal and of the shifted internal clock signal are spaced apart from one another by, in particular, half a clock period of the period duration of the input clock.
In the present invention, the problem mentioned in the introduction is solved in particular by virtue of the fact that the second delay device (delay line) is driven by an independent second pump device (charge pump) having a slightly modified pump circuit.
In accordance with one preferred development, a second device for generating a second control signal has a duty ratio detector.
In accordance with a further preferred development, the second device for generating the second control signal has a pump device by means of which the second control signal can be generated in a manner dependent on an output signal of the duty ratio detector.
In accordance with a further preferred development, the pump device has switching devices and at least one capacitance.
In accordance with a further preferred development, the switching devices have both p-channel field-effect transistors and n-channel field-effect transistors.
In accordance with a further preferred development, the output signals of the duty ratio detector are coupled only to control terminals of the n-channel field-effect transistors, these n-channel field-effect transistors being embodied in doubled (parallel) fashion, in particular.
In accordance with a further preferred development, the duty ratio detector carries out an edge detection whose output signal has a HIGH level between a rising edge of the delayed internal clock signal and a rising edge of the shifted inverted delayed internal clock signal and a LOW level between a rising edge of the shifted inverted delayed internal clock signal and a rising edge of the delayed internal clock signal.
In accordance with a further preferred development, the method uses an analog delay locked loop (DLL).
In accordance with a further preferred development, the method uses a digital, clock-controlled delay locked loop (DLL).
In accordance with a further preferred development, the method is used to generate a clock signal on a semiconductor device which has a duty ratio of 0.5.
Exemplary embodiments of the invention are illustrated in the drawings and explained in more detail in the description below.
In the figures:
In the figures, identical reference symbols denote identical or functionally identical constituent parts.
The complementary clock signal 4 generated on the chip, in particular, is fed to a second delay device 5B (delay line), which, in a manner dependent on a control signal 15, 16, forwards the complementary clock signal 4 in delayed fashion to a driver stage 23, which provides a shifted inverted delayed internal clock signal 12. The delayed internal clock signal 11 and the shifted inverted delayed internal clock signal 12 are fed to a duty ratio detector 10 (duty cycle detector), which outputs a control signal 13, 14 to a modified pump device 9 (modified charge pump). Any type of edge detector circuit can be used to generate the control signal 13, 14. The modified pump device 9 (modified charge pump) generates from the control signal 13, 14 a control signal 15, 16, in particular a control voltage, for controlling the delay time period of the second delay device 5B.
In the circuit, the delayed internal clock signal 11 is intentionally shifted with respect to an inverted delayed internal clock signal 12, so that the rising edges of the signals 11, 12 in each case have a spacing of half a clock period T/2 of the clock period T of the clock signal 1, 2, 3, 4 from one another. Since, by way of example, only the rising edges are utilized on a chip, this modification guarantees the correction of the duty ratio.
In the left-hand drawing of
The right-hand drawing of
The modified pump device 9 or its output signals 15, 16, i.e. its output voltages, is described by the following system of equations:
where dc denotes the duty ratio of the control signal 13, 14, i.e. the duration of the HIGH level divided by the clock period duration, and C denotes the capacitance of the capacitor 28. I16 designates the saturation current which is driven through the p-channel field-effect transistor 24 by the control voltage 16 present at the gate, and I15 denotes the saturation current which is driven through the n-channel field-effect transistor 25 by the control voltage 15 present at the gate. The left-hand and right-hand parts of the modified pump device 9 (modified charge pump) according to
As a result of the feedback via the duty ratio detector 10 and the modified pump device 9 according to
The realization of a modified pump device 9 according to
In order to avoid the disadvantage set forth with reference to
The right-hand part of the diagrammatic circuit according to
Preferably, all the switching devices indexed with <0:1> are embodied in doubled fashion and are in each case connected in parallel. This dimensioning guarantees that the operating point of the two delay devices 5 (delay lines) is identical if the external clock signal 1 should have an ideal duty ratio of 0.5. The p-channel field-effect transistor 24 in a cascade arrangement is not absolutely necessary, but can be used to switch off the current path in the case of a reset.
The reason for the doubling of the switching devices indexed with <0:1> becomes apparent from the following system of equations:
where the designations set forth with reference to
The explanation given with reference to
The present invention provides an apparatus and a method which realizes the correction of a duty ratio (duty cycle) using comparatively simple means and without a large current consumption.
Although the present invention has been described above using preferred exemplary embodiments, it is not restricted thereto, but rather can be modified in diverse ways. Even though the above examples relate to a circuit for an analog delay locked loop, the use of the same principle can likewise be realized in a digital, i.e. clock-controlled, delay locked loop.
Moreover, the invention is not restricted to the application possibilities mentioned.
Minzoni, Alessandro, Brox, Martin
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