According to some embodiments, a device includes a phase generator to generate m control signals, each of the m control signals associated with a respective signal period, and at least m filters, each of the at least m filters comprising m-n taps, each of the m-n taps to receive one of the m control signals, to acquire a signal sample according to a signal period associated with the received control signal, and to modulate the signal sample according to a weighting coefficient associated with the tap. The device further includes m evaluation circuits, each evaluation circuit associated with a respective one of the at least m filters and to output a sum of signal samples modulated by the taps of the associated filter in response to one of the m control signals associated with a signal period other than the signal periods according to which the signal samples were acquired.
|
1. A device comprising:
a phase generator to generate m control signals, each of the m control signals to represent a respective signal period; at least m filters, each of the at least m filters comprising m-n taps, each of the m-n taps to receive one of the m control signals, to acquire a sample of a data signal according to the signal period represented by the received control signal, and to modulate the sample according to a weighting coefficient input to the tap; and at least m evaluation circuits, each circuit associated with a respective one of the at least m filters and to output a sum of samples modulated by the taps of the associated filter in response to one of the m control signals that represents the signal period that is different from the signal periods according to which the samples were acquired.
19. A method comprising:
generating m control signals, each of the m control signals to represent a respective signal period; receiving m-n of the m control signals with m-n taps of each of at least m filters; acquiring, with each tap, a sample of a data signal according to a signal period represented by the control signal received by the tap; modulating, with each tap, the sample acquired with the tap according to a weighting coefficient input to the tap; and outputting, from one of at least m evaluation circuits, each evaluation circuit associated with a respective one of the at least m filters, a sum of samples modulated by the taps of the associated filter in response to one of the m control signals that represents a signal period that is different from the signal periods according to which the samples were acquired.
24. A method comprising:
generating m control signals, each of the m control signals to represent a respective signal period; acquiring, with each of at least m weighting circuits, each of the at least m weighting circuits to receive a respective one of the m control signals, a sample according to a signal period represented by the respective one of the m control signals; modulating, with each of m-n weighting units of one of the at least m weighting circuits, the acquired sample according to a weighting coefficient input to the weighting unit; receiving, with each of at least m evaluation circuits, one weighted sample from each of m-n weighting circuits; and outputting a sum of the received weighted signal samples in response to one of the m control signals that represents the signal period that is different from the signal periods according to which the samples were acquired.
12. A device comprising:
a phase generator to generate m control signals, each of the m control signals to represent a respective signal period; at least m weighting circuits, each of the at least m weighting circuits to receive a respective one of the m control signals, to acquire a sample of a data signal according to a signal period represented by the respective one of the m control signals, and comprising m-n weighting units, each of the m-n weighting units of one of the at least m weighting circuits to modulate the acquired sample according to a weighting coefficient input to the weighting unit; and at least m evaluation circuits, each evaluation circuit to receive one weighted sample from m-n weighting circuits and to output a sum of the received samples in response to one of the m control signals that represents the signal period that is different from the signal periods according to which the samples were acquired.
26. A system comprising:
a chipset; and a die comprising a microprocessor in communication with the chipset, wherein the microprocessor includes a filter comprising: a phase generator to generate m control signals, each of the m control signals to represent a respective signal period; at least m filters, each of the at least m filters comprising m-n taps, each of the m-n taps to receive one of the m control signals, to acquire a sample of a data signal according to a signal period represented by the received control signal, and to modulate the sample according to a weighting coefficient input to the tap; and at least m evaluation circuits, each circuit associated with a respective one of the at least m filters and to output a sum of samples modulated by the taps of the associated filter in response to one of the m control signals that represents the signal period that is different from the signal periods according to which the signal samples were acquired.
29. A system comprising:
a chipset; and a die comprising a microprocessor in communication with the chipset, wherein the microprocessor includes a filter comprising: a phase generator to generate m control signals, each of the m control signals to represent a respective signal period; at least m weighting circuits, each of the at least m weighting circuits to receive a respective one of the m control signals, to acquire a sample of a data signal according to a signal period represented by the respective one of the m control signals, and comprising m-n weighting units, each of the m-n weighting units of one of the at least m weighting circuits to modulate the acquired sample according to a weighting coefficient input to the weighting unit; and at least m evaluation circuits, each evaluation circuit to receive one weighted sample from m-n weighting circuits and to output a sum of the received samples in response to one of the m control signals that represents the signal period that is different from the signal periods according to which the samples were acquired.
2. A device according to
3. A device according to
4. A device according to
5. A device according to
6. A device according to
7. A device according to
8. A device according to
9. A device according to
11. A device according to
13. A device according to
14. A device according to
15. A device according to
16. A device according to
18. A device according to
20. A method according to
21. A method according to
22. A method according to
23. A method according to
25. A method according to
receiving, with each of the m-n weighting units, a substantially identical sample from the current mirror, and modulating, with each of the m-n weighting units, the sample with the weighting coefficient input to the weighting unit.
27. A system according to
28. A system according to
30. A system according to
|
Small electronic circuits are often used in conjunction with high-frequency signals. However, some transmission materials used in these circuits cause significant signal loss when carrying high frequency signals. For example, signals transmitted at 3 to 4 GHz over a small portion of FR4 substrate may experience 30 to 40 dB of signal loss.
Circuit designers attempt to compensate for this loss by filtering received signals. In one example, received signals are converted to digital signals with an analog-to digital converter and then filtered using a digital filter. Analog-to-digital converters are, however, often costly and difficult to implement at high data rates. Even if analog-to-digital conversion is not problematic for a given high-frequency application, subsequent filtering of the digital high-frequency signals may itself be difficult to design and/or implement.
Analog filters may be used to address the foregoing, but power requirements of these filters usually increase with signal frequency. For example, conventional Finite Impulse Response (FIR) analog filters operate by convolving samples of a received signal with a set of weighting coefficients. A finite state machine typically performs the convolution by rotating the coefficients amongst a set of multipliers for multiplying a fixed signal sample by a weighting coefficient and/or by rotating the signal samples amongst a set of multipliers for multiplying a signal sample by a fixed weighting coefficient. The finite state machine as well as other elements used to perform the convolution adds significantly to the power requirements of the FIR filter, particularly during high-frequency operation.
Voltage-to-current converter 1 includes bias current source 2 coupled to parallel loads 3 and 4, which may comprise resistors. Loads 3 and 4 are respectively coupled to a source of p-channel metal oxide semiconductor (PMOS) transistor 5 and to a source of PMOS transistor 6. Voltage signal Vdata is applied to a gate of transistor 5 and Vdata# is applied to a gate of transistor 6. By virtue of this configuration, voltage-to-current converter 1 converts voltage signal Vdata to differential current signal Idata and outputs Idata from a drain terminal of transistor 6. Similarly, converter 1 converts voltage signal Vdata# to differential current signal Idata# and outputs Idata# from a drain terminal of transistor 5. In a case that converter 1 performs a substantially linear conversion, differential current signals Idata and Idata# together represent a current signal that substantially encodes any data encoded by the differential-mode voltage signal represented by differential voltage signals Vdata and Vdata#.
As shown, current signal Idata is applied to source terminals of PMOS transistors 11 through 14 and current signal Idata# is applied to source terminals of PMOS transistors 15 through 18. Control signals D1 and D2 are applied as shown to base terminals of transistors 11 through 18, wherein {overscore (Di)} denotes the Boolean complement of Di. The weights applied to current signals Idata and Idata# are therefore determined by control signals D1 and D2 and the relative channel width-to-length ratios of transistors 11 through 18. For example, when D1 and D2 are both HIGH, signals received from converter 1 are shunted to ground and the effective multiplication value, or weighting, is zero.
In the illustrated embodiment, the channel width-to-length ratio of transistors 13 through 16 is twice the channel width-to-length ratio of transistors 11, 12, 17 and 18. Therefore, the effective multiplication value is one in a case that D1 is LOW and D2 is HIGH, two in a case that D1 is HIGH and D2 is LOW, and three in a case that both D1 and D2 are LOW. Although weighting unit 10 of
Input ports 25a and 25b receive a differential voltage signal from a transmission line. Samplers 30a through 30d sample the differential signal according to their respective control, or clock, signals clka through clkd. Samplers 30a through 30d each consist of two switches connected to respective capacitors. In operation, the switches are closed upon receipt of a HIGH control signal, and are opened when the control signal is LOW. Accordingly, the capacitors of each of samplers 30a through 30d store a sample of the differential voltage signal to which the capacitor is connected while the control signal is HIGH.
As described with respect to
Weighting units 10a through 10d modulate signals received from respective converters 1a through 1d based on respective weighting coefficients w1 through w4. In a case that coefficients w1 through w4 are two-bit signals, units 10a through 10d may be substantially similar to unit 10 of FIG. 2. Each weighting unit is coupled to one of sign elements 35a through 35c. Sign elements 35a through 35c may comprise two-by-two crossbar switches, and are used to effectively reverse the sign of one of weighting coefficients w1 through w4.
Current signals output from sign elements 35a through 35d are summed by convergent signal lines and sunk into loads 40a and 40b. Voltages developed by these loads represent a filtered differential voltage signal that is input to differential evaluation circuit 50, which may comprise a differential latch. Circuit 50 effectively converts the differential voltage signal into a logic signal indicative of whether a "1" or a "0" was received from the transmission line. In operation, a control signal clke, is transmitted to evaluation circuit 50 at an appropriate timing in order to prepare circuit 50 to evaluate an incoming differential voltage signal.
Also shown in
Decoder 70 receives output from each of evaluation circuits 50a through 50f. Each output reflects a sum of weighted signal samples. As will be described below, only one output per signal period will represent a valid filtered output. Decoder 70 therefore is controlled to determine the valid output in order to generate a filtered differential-mode signal corresponding to the differential-mode voltage signal represented by voltage signals Vdata and Vdata#.
Different sets of control signals are input to each of filters 20a through 20f. More particularly, each tap a through d of each filter 20a through 20f receives a control signal intended to effect a convolution over time as shown in FIG. 5. The convolution is also implemented by inputting appropriate ones of control signals clk1 through clk6 to each of evaluation circuits 50a through 50f so that the circuits generate outputs once each sampler of an associated filter has acquired a new signal sample to be modulated.
As shown in
The table below specifies an arrangement of control signals clk1 through clk6 within the elements of
control | filter | filter | filter | filter | filter | filter | eval. | |
signal | bit-cell | 20a | 20b | 20c | 20d | 20e | 20f | circuit |
clk1 | 1,7, . . . | 30a | -- | -- | 30d | 30c | 30b | 50c |
clk2 | 2,8, . . . | 30b | 30a | -- | -- | 30d | 30c | 50d |
clk3 | 3,9, . . . | 30c | 30b | 30a | -- | -- | 30d | 50e |
clk4 | 4,10, . . . | 30d | 30c | 30b | 30a | -- | -- | 50f |
clk5 | 5,11, . . . | -- | 30d | 30c | 30b | 30a | -- | 50a |
clk6 | 6,12, . . . | -- | -- | 30d | 30c | 30b | 30a | 50b |
Current mirror 90 is comprised of n-channel metal oxide semiconductor transistors and is adapted to generate four current signals substantially identical to the sampled differential current signals received from converter 1e. According to some embodiments of mirror 90, the generated signals are amplified versions of the received signals. Current mirror 90 includes sign elements 95 through 98 that may be used as described above to reverse the sign of a weighting coefficient. In this regard, each of the four signals generated by mirror 90 is transmitted to one of weighting units 10e through 10h for modulation according to one of weighting coefficients w1 through w4.
Numbers located adjacent to the output lines of weighting circuits 80a through 80f indicate weighting coefficients applied to signals carried by those lines. For example, the output line adjacent to the number "3" of weighting circuit 80d carries a signal modulated according to weighting coefficient W3. Since weighting circuit 80d receives control signal clk4, the signal represents "X4*W3" according to the notation of FIG. 5.
The
Thus, embodiments may reduce power requirements by filtering using fixed weighting coefficients and signal samples.
The several embodiments described herein are solely for the purpose of illustration. For example, although the above embodiments are described in conjunction with differential signaling, some embodiments may be used in conjunction with single-ended and/or pseudo-differential signaling. Samplers, voltage-to-current converters, current multipliers, sign elements and evaluation circuits other than those described above may be used in some embodiments, and each of these elements need not be identical across and/or within weighting circuits. Moreover, the ground-referenced PMOS transistors described herein may be substituted with Vcc-referenced n-channel metal oxide semiconductor transistors, and the current sources may be replaced with current sinks. Therefore, persons skilled in the art will recognize from this description that other embodiments may be practiced with various modifications and alterations.
Jaussi, James E., Casper, Bryan K.
Patent | Priority | Assignee | Title |
7286006, | Jun 28 2004 | Intel Corporation | Sign-sign least means square filter |
7573326, | Dec 30 2005 | Intel Corporation | Forwarded clock filtering |
7961039, | Dec 30 2005 | Intel Corporation | Forwarded clock filtering |
8346835, | Jul 24 2006 | Universitaet Stuttgart | Filter structure and method for filtering an input signal |
Patent | Priority | Assignee | Title |
4308618, | Apr 27 1979 | Compagnie Industrielle des Telecommunications Cit-Alcatel | Method of compensating phase noise at the receiver end of a data transmission system |
5841811, | Oct 07 1994 | Massachusetts Institute of Technology | Quadrature sampling system and hybrid equalizer |
6621330, | Jun 04 2002 | Intel Corporation | Discrete-time analog filter |
20020129070, |
Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
Dec 12 2002 | JAUSSI, JAMES E | Intel Corporation | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 013610 | /0405 | |
Dec 12 2002 | CASPER, BRYAN K | Intel Corporation | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 013610 | /0405 | |
Dec 20 2002 | Intel Corporation | (assignment on the face of the patent) | / | |||
Feb 04 2016 | Intel Corporation | BEIJING XIAOMI MOBILE SOFTWARE CO , LTD | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 037733 | /0440 |
Date | Maintenance Fee Events |
Sep 19 2005 | ASPN: Payor Number Assigned. |
Jan 25 2008 | M1551: Payment of Maintenance Fee, 4th Year, Large Entity. |
Feb 04 2008 | REM: Maintenance Fee Reminder Mailed. |
Sep 21 2011 | M1552: Payment of Maintenance Fee, 8th Year, Large Entity. |
Mar 04 2016 | REM: Maintenance Fee Reminder Mailed. |
Jul 19 2016 | M1553: Payment of Maintenance Fee, 12th Year, Large Entity. |
Jul 19 2016 | M1556: 11.5 yr surcharge- late pmt w/in 6 mo, Large Entity. |
Date | Maintenance Schedule |
Jul 27 2007 | 4 years fee payment window open |
Jan 27 2008 | 6 months grace period start (w surcharge) |
Jul 27 2008 | patent expiry (for year 4) |
Jul 27 2010 | 2 years to revive unintentionally abandoned end. (for year 4) |
Jul 27 2011 | 8 years fee payment window open |
Jan 27 2012 | 6 months grace period start (w surcharge) |
Jul 27 2012 | patent expiry (for year 8) |
Jul 27 2014 | 2 years to revive unintentionally abandoned end. (for year 8) |
Jul 27 2015 | 12 years fee payment window open |
Jan 27 2016 | 6 months grace period start (w surcharge) |
Jul 27 2016 | patent expiry (for year 12) |
Jul 27 2018 | 2 years to revive unintentionally abandoned end. (for year 12) |