A circuit arrangement for signaling in telecommunications networks has a first connection and a second connection for a first and a second conductor, respectively, in a transmission line. The first connection is connected to the first input of a rectifier, and the second connection is connected to the second input of said rectifier. The positive output and the negative output of the rectifier are connected to one another via a variable resistance. A third connection for a third conductor in the transmission line can be connected via the series circuit formed by a switch and a first diode to the positive output of the rectifier, and via the series circuit formed by the switch and a second diode to the negative output of the rectifier.
|
1. A circuit arrangement for signaling in telecommunications networks, with a first connection (a) and a second connection (b) for a first and a second conductor, respectively, in a transmission line being connected to the first input and to the second input, respectively, of a rectifier, and with the positive output and the negative output of the rectifier being connected to one another via a variable resistance
wherein a third connection (c) for a third conductor in the transmission line can be connected via the series circuit formed by a switch and a first diode to the positive output of the rectifier, and via the series circuit formed by the switch and a second diode to the negative output of the rectifier.
2. The circuit arrangement as claimed in
a control loop is provided to which a first voltage, which is produced at the positive output of the rectifier, and a second voltage, which is produced at the negative output of the rectifier, are supplied, and the control loop produces a control voltage which controls the variable resistance, and with the transfer function of the control loop being variable.
4. The circuit arrangement as claimed in
the cathode of the first diode is connected to the positive output of the rectifier, and the anode of the second diode is connected to the negative output of the rectifier.
5. The circuit arrangement as claimed in
the control loop has a digital filter, with the transfer function of the control loop being variable by programming the filter coefficients of the digital filter.
6. The circuit arrangement as claimed in
the digital filter is formed by an appropriately programmed digital signal processor.
7. The circuit arrangement as claimed in
the control loop has an analog integrator circuit which is connected upstream of the transistor and integrates the difference between a first and a second input voltage, and whose output signal controls the transistor.
|
The invention relates to a circuit arrangement for signaling in telecommunications networks, as claimed in the preamble of patent claim 1, and as is known from U.S. Pat. No. 4,190,745.
Private branch exchanges (PBX), digital multichannel transmission systems (DAML=Digital Added Main Line) or digital transmission systems (DLC=Digital Loop Carrier) have functions for signaling operating states. For this purpose resistances are connected between the individual transmission lines by, for example, a private branch exchange. A switching center, which is connected to the private branch exchange, then applies a voltage between one line and the other lines, which are short-circuited, and measures the resultant currents through the lines. The switching center can use the measured currents to deduce the resistances connected between the individual transmission lines. By varying the resistance values, for example, the private branch exchange can transmit information about operating states to the switching center. For example, in this case, it is possible to signal whether a voice transmission or a data transmission is intended to take place. Alternatively, the switching center can find out whether the transmission lines are faulty. In this case, however, different resistance values must be provided and the resistance values must be matched to specific national requirements for the transmission lines, particularly when using public telecommunications network transmission lines.
If there are three transmission lines, the measurement is carried out by using switches, which are preferably in the form of relays, to connect resistances between the transmission lines. Two transmission lines are in each case short-circuited to one another, as a result of which two resistances are in each case connected in parallel. The switching center applies a voltage to the remaining transmission lines. The resultant currents through the transmission lines and resistances are measured, and the resistance values are calculated from them. The calculation results are also referred to as a signature. A signature makes it possible, for example, to deduce the state of the transmission lines or a specific operating state. If one of the transmission lines is broken, then no current can flow via this line and the resistance value determined by the switching center in this measurement, or the signature, does not match the predetermined resistance value or the signature for an uninterrupted line. A disadvantage in this case is that the relays for connecting the resistances between the transmission lines are expensive. A correspondingly large number of resistances must be provided if there are a number of different signatures. Furthermore, a resistance must be provided for each transmission line, and these resistances must be matched to the specific national requirements. It is either necessary to construct different circuits for different resistance values, or parallel resistance paths must be provided, with a correspondingly large number of relays.
A circuit arrangement for detecting faults on a subscriber line is known from U.S. Pat. No. 4,710,949, which uses switches that are sensitive to voltage and current and are connected in the lines. A disadvantage in this case is, however, that these switches are highly complex and are thus expensive. Furthermore, these switches can influence the transmission of signals.
The invention is thus based on the technical problem of specifying a circuit arrangement for signaling in telecommunications networks which, firstly, can be matched to different requirements and, secondly, can be constructed with little circuitry complexity.
This object is achieved by a circuit arrangement for signaling in telecommunications networks having the features of patent claim 1. Advantageous refinements of the circuit arrangement can be found in the respective dependent claims.
A circuit arrangement for signaling in telecommunications networks has a first connection and a second connection for a first and a second conductor, respectively, in a transmission line. The first connection is connected to the first input of a rectifier, and the second connection is connected to the second input of said rectifier. The positive output and the negative output of the rectifier are connected to one another via a variable resistance. A third connection for a third conductor in the transmission line can be connected via the series circuit formed by a switch and a first diode to the positive output of the rectifier, and via the series circuit formed by the switch and a second diode to the negative output of the rectifier.
The control loop, the rectifier and the transistor and resistance are used for setting a line impedance during normal operation of a line circuit which, for example, links a digital subscriber circuit to an analog transmission line. Thus, advantageously, the invention provides a circuit arrangement for signaling in telecommunications networks with little additional circuitry complexity--two diodes and one switch. Instead of having to provide a specific resistance for testing each conductor in a transmission line, which is connected by means of a relay between two conductors in the transmission line for testing, already existing circuits are provided with additional circuits for testing the transmission line.
In one preferred embodiment, a control loop is provided to which a first voltage, which is produced at the positive output of the rectifier, and a second voltage, which is produced at the negative output of the rectifier, are supplied. The control loop produces a control voltage which controls the variable resistance. The transfer function of the control loop is variable. A particularly advantageous feature in this case is that the capability to vary the transfer function of the control loop makes it possible to vary the variable resistance, and thus the resistance between two conductors in the transmission line, during testing. The circuit arrangement can thus be matched to specific national requirements, and different signatures can be produced, without changing the circuitry.
It is particularly preferable for the variable resistance to have a transistor.
The cathode of the first diode is preferably connected to the positive output of the rectifier, and the anode of the second diode is preferably connected to the negative output of the rectifier.
The control loop preferably has a digital filter, with the transfer function of the control loop being variable by programming the filter coefficients of the digital filter. It is particularly preferable in this case for the digital filter to be formed by an appropriately programmed digital signal processor.
In one preferred embodiment, the control loop has an analog integrator circuit which is connected upstream of the transistor and integrates the difference between a first input voltage and a second input voltage, and whose output signal controls the transistor.
It is particularly preferable for the transistor to be an n-channel MOSFET.
The circuit arrangement for signaling in telecommunications networks is also suitable for being added to an integrated circuit, by virtue of the use of electronic components. In this case, of course, all the other circuits, such as the control loop, the rectifier and the transistor and resistors, can also be integrated at the same time.
Further advantages, features and application options for the invention will become evident from the following description of exemplary embodiments in conjunction with the drawing. In the drawing:
The circuit arrangement illustrated in
The circuit arrangement for signaling is used in a chip set for connection of a digital subscriber circuit (DSL=Digital Subscriber Line) to an analog telephone line (transmission line). The chip set in this case converts the signals on the analog telephone line to digital signals for further processing by the digital subscriber circuit and, conversely, converts digital signals to analog signals for the digital subscriber circuit for transmission via the analog telephone line.
A switching center can apply various signaling voltages via the transmission line. To do this, the switching center short-circuits two of the three conductors in the transmission line. Furthermore, the circuit arrangement for signaling connects a resistance between the remaining conductor and the two short-circuited conductors. The switching center applies a voltage between the remaining conductor and the two short-circuited conductors. A current flowing via the conductors is measured by the switching center, and this is used to calculate a resistance. If there are no faults on the lines, the calculated resistance will be within a specific predetermined range. In this case, the predetermined range is defined by specific national requirements.
The connections a and b of the circuit arrangement for signaling are connected to a first input and a second input, respectively, of a bridge rectifier 1. A first output 12 and a second output 13 of the bridge rectifier can be connected, respectively, via a first diode D1 and a switch S to the third connection c of the circuit arrangement for signaling and via a second diode D2 and the switch S to the third connection c of said circuit arrangement for signaling. The n-connection of the first diode D1 is in this case connected to the first output 12 of the rectifier 1. The p-connection of the second diode D2 is connected to the second output 13 of the rectifier 1.
The first output 12 of the bridge rectifier 1 is connected to a reference ground potential VSS via the load path of a transistor T1. The second output 13 of the bridge rectifier 1 is connected to the reference ground potential VSS via a resistance R1.
A voltage which is present between the connections a and b is rectified by the bridge rectifier 1. A rectified positive voltage Va is produced at the first output 12 of the bridge rectifier 1. A rectified negative voltage Vb is produced at the second output 13 of the bridge rectifier 1.
The rectified positive voltage Va, whose voltage levels are high, is subdivided via a voltage divider R2 and R3 to produce a lower voltage, in order to avoid overdriving the downstream circuits, in which the signal voltage levels are only low in comparison to the rectified positive voltage.
After being divided, the positive voltage Va and the negative voltage Vb are supplied to a subtraction circuit 5, at whose output a difference voltage Vab is produced.
The difference voltage Vab is then sampled by an analog/digital converter 2 at a sampling rate fs and is converted to a digital signal V' ab.
The digital output signal V' ab from the analog/digital converter 2 is supplied to a digital filter 3. The digital filter 3 can be programmed by a digital control device 10 for matching to specific national requirements and, for this purpose, has a programmable transfer function k. In this case, the digital filter 4 may be in the form of digital hardware, in which the coefficients are programmable. The digital filter may likewise be in the form of a signal processing algorithm in a digital signal processor, in which case the filter function can be adjusted by means of variables.
The output signal VSI from the digital filter 4 is converted by a digital/analog converter 4 to an analog signal VI.
The analog signal VI is supplied to a first input of an analog integrator circuit 6. The negative voltage Vb is supplied via a second input to the analog integrator circuit 6. The analog integrator circuit 6 uses the two input signals to form a difference, which is then integrated. The voltage VSt is produced at the output of the analog integrator circuit 6, and is passed to the control connection of the transistor T1. A line current I is set via the transistor T1. The analog integrator circuit 6 integrates the difference voltage VI-Vb until the difference voltage VI-Vb becomes zero. Thus, from Vb=R1*I=VI, it is possible to derive a conductance value GM=I/VI=1/R1 for the analog integrator circuit 6.
Case 1: The connections a and c are short-circuited. A first voltage V1 is applied between the connection b and the short-circuited connections a and c. The switch S is opened. A first current I1 flows via the path marked by a bold line. A resistance V1/I1 can be calculated from the first voltage V1 and the first current I1, and this is governed by the resistance of the load path through the first transistor T1 and the resistance R1.
Case 2: The connections b and c are shorted-circuited. A second voltage V2 is applied between the connection a and the short-circuited connections b and c. The switch S is opened. A second current I2 flows via the path marked by a bold line. A resistance V2/I2 can once again be calculated from the second voltage V2 and the second current I2, and this is governed by the resistance of the load path through the first transistor T1 and the resistance R1.
Case 3: The connections a and b are short-circuited. A third voltage V3 is applied between the connection c and the short-circuited connections a and b. In this case, the switch S is closed. A third current I3 flows via the path marked by a bold line. A resistance V3/I3 can once again be calculated from the third voltage V3 and the third current I3, and this is governed by the resistance of the load path through the first transistor T1 and the resistance R1.
One conductor in the transmission line is tested in each of the three cases. If the calculated resistance differs from a predetermined value in one of the three cases, then there is a faulty transmission line. Since the calculated resistance value depends on the resistance of the load path through the first transistor T1 and the resistance R1, the resistance of the load path through the transistor T1 can be matched to (for example) specific national requirements by programming the transfer function of the digital filter 3. For this purpose, specific national values for the predetermined resistance can be stored in a memory 11. To this end, the digital control device 10 reads from the memory 11 the values required for programming the specific national resistance, and changes the programming of the digital filter 3 accordingly.
Hauptmann, Jorg, Kahl, Alexander
Patent | Priority | Assignee | Title |
Patent | Priority | Assignee | Title |
4190745, | Dec 01 1978 | AG COMMUNICATION SYSTEMS CORPORATION, 2500 W UTOPIA RD , PHOENIX, AZ 85027, A DE CORP | Call for service and continuity sensor circuit |
4311879, | Jun 02 1980 | AG COMMUNICATION SYSTEMS CORPORATION, 2500 W UTOPIA RD , PHOENIX, AZ 85027, A DE CORP | AC Supervisory signal detector circuit |
5500894, | Dec 03 1993 | Maxim Integrated Products, Inc | Telephone line interface with AC and DC transconductance loops |
EP467367, | |||
EP991218, |
Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
Aug 27 2001 | HAUPTMANN, JORG | Infineon Technologies AG | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 012258 | /0768 | |
Aug 27 2001 | KAHL, ALEXANDER | Infineon Technologies AG | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 012258 | /0768 | |
Sep 24 2001 | Infineon Technologies AG | (assignment on the face of the patent) | / | |||
Jul 03 2009 | Infineon Technologies AG | INFINEON TECHNOLOGIES WIRELESS SOLUTIONS GMBH | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 024483 | /0021 | |
Nov 06 2009 | INFINEON TECHNOLOGIES WIRELESS SOLUTIONS GMBH | Lantiq Deutschland GmbH | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 024529 | /0593 | |
Nov 16 2010 | Lantiq Deutschland GmbH | DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT | GRANT OF SECURITY INTEREST IN U S PATENTS | 025406 | /0677 | |
Mar 03 2015 | Lantiq Deutschland GmbH | LANTIQ BETEILIGUNGS-GMBH & CO KG | MERGER AND CHANGE OF NAME SEE DOCUMENT FOR DETAILS | 045086 | /0015 | |
Mar 03 2015 | LANTIQ BETEILIGUNGS-GMBH & CO KG | LANTIQ BETEILIGUNGS-GMBH & CO KG | MERGER AND CHANGE OF NAME SEE DOCUMENT FOR DETAILS | 045086 | /0015 | |
Apr 15 2015 | DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT | LANTIQ BETEILIGUNGS-GMBH & CO KG | RELEASE OF SECURITY INTEREST RECORDED AT REEL FRAME 025413 0340 AND 025406 0677 | 035453 | /0712 |
Date | Maintenance Fee Events |
Feb 15 2005 | ASPN: Payor Number Assigned. |
Mar 03 2008 | M1551: Payment of Maintenance Fee, 4th Year, Large Entity. |
Mar 01 2012 | M1552: Payment of Maintenance Fee, 8th Year, Large Entity. |
Mar 01 2016 | M1553: Payment of Maintenance Fee, 12th Year, Large Entity. |
Date | Maintenance Schedule |
Sep 07 2007 | 4 years fee payment window open |
Mar 07 2008 | 6 months grace period start (w surcharge) |
Sep 07 2008 | patent expiry (for year 4) |
Sep 07 2010 | 2 years to revive unintentionally abandoned end. (for year 4) |
Sep 07 2011 | 8 years fee payment window open |
Mar 07 2012 | 6 months grace period start (w surcharge) |
Sep 07 2012 | patent expiry (for year 8) |
Sep 07 2014 | 2 years to revive unintentionally abandoned end. (for year 8) |
Sep 07 2015 | 12 years fee payment window open |
Mar 07 2016 | 6 months grace period start (w surcharge) |
Sep 07 2016 | patent expiry (for year 12) |
Sep 07 2018 | 2 years to revive unintentionally abandoned end. (for year 12) |