A non-volatile semiconductor memory device is disclosed, which comprises a memory cell unit including at least one memory cell transistor formed on a semiconductor substrate and having a laminated structure of a charge accumulation layer and a control gate layer, and a selection gate transistor one of the source/drain diffusion layer regions of which is connected to a bit line or a source line and the other of the the source/drain diffusion layer regions of which is connected to the memory cell unit. The shape of the source diffusion layer region of the selection gate transistor is asymmetrical to the shape of the drain diffusion layer region thereof below the selection gate transistor.
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1. A non-volatile semiconductor memory device, comprising:
a plurality of memory cell units comprising at least one memory cell having a laminated gate structure of a charge accumulation layer and a control gate layer formed above a semiconductor substrate, with a gate insulation film provided between the laminated gate structure and the semiconductor substrate; and a plurality of selection gate transistors each having a gate electrode formed on the gate insulation film and source/drain diffusion layers, one of which is connected to each memory cell unit and the other of which is electrically connected to a bit line or a source line, wherein the plurality of selection gate transistors include a pair of selection gate transistors disposed in confrontation with each other across a contact portion connected to the bit line or to the source line and having substantially the same structure; and channel regions of the pair of selection gate transistors have a same impurity concentration in a gate length direction at a depth equal from the boundary between the semiconductor substrate and the gate insulation film as well as a concentration distribution of impurity in the channel regions of the pair of selection gate transistors is different from that of a channel region of the memory cell, and an impurity distribution width in a depth direction of the channel region of each of the pair of selection gate transistors is narrower than that of the channel region of the memory cell.
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This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 2001-023973, filed Jan. 31, 2001; and No. 2001-085821, filed Mar. 23, 2001, the entire contents of both of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device, and particularly to a selection gate transistor in a memory cell portion which is, for example, applied to a NAND type flash memory.
2. Description of the Related Art
A contact hole 34 is formed between the gate electrodes of the selection gate transistors in self-alignment with respect to these gate electrodes. A TEOS film 29 is deposited on the gate sidewalls of the memory cell transistors to improve hot carrier characteristics.
On the other hand, the selection gate transistors are arranged such that the TEOS film 29 of the gate sidewalls thereof is removed before the contact hole 34 is opened to prevent the short-circuit between a contact filling material and the gate electrodes because the TEOS film 29 is etched when the contact hole 34 is opened. Since an impurity is simultaneously ion-implanted in the channel regions and source/drain diffusion layer regions 28 of the memory cell transistors and the selection gate transistors, the impurity distribution in the channel regions and the source/drain diffusion layer regions 28 is similar in the memory cell transistors and the selection gate transistors.
In the NAND type semiconductor memory device, when data "1" is written to a memory cell (i.e. when electrons are not implanted in floating gates and a threshold value in erasing is maintained), the electrons are prevented from being implanted in the floating gates 5 and 11 by charging an initial potential from a bit line through the selection gate transistor connected to the memory cell transistor, applying a writing voltage to a selected word line and applying a transfer voltage to non-selected word lines, and increasing the potential of the channel region of the memory cell transistor making use of capacitance coupling. As a result, the capacitance of the channel region is reduced by decreasing the concentration of the impurity therein so that the potential of the channel region is liable to increase, which improves data "1" writing characteristics.
However, there are such circumstances that the non-volatile semiconductor memory device cannot be normally operated by a decrease in the threshold voltage of the selection gate transistors and an increase in the off-leak current thereof which are caused when the concentration of the impurity in the channel regions is reduced. This is because that the distribution of the impurity in the channel regions of the memory cell transistors is the same as that of the impurity in the channel regions of the selection gate transistors.
In the figure, reference numeral 1 denotes a silicon substrate and reference numeral 3 denotes a well/channel region. The memory cell and selection gate transistor are simultaneously subjected to impurity ion implantation into the well/channel region 3 and formation of a gate insulation film 4.
The memory cell of the NAND memory cell unit has a gate structure where a charge accumulation layer (floating gate) and a control gate layer are stacked one atop the other via an ONO film 13 on a substrate. The floating gate comprises a first layer of polysilicon 5 and a second layer as a floating gate 11 which are deposited in layers. The control gate layer 14 is formed of a polysilicon/WSi laminated film. Here, indicated by reference numeral 15 is a silicon nitride film and 20 is a silicon oxide film. Gate electrodes of the selection gate transistor are designated by reference numerals 5 and 11. Reference numeral 28 denotes a source/drain diffusion layer of the memory cell and selection gate transistor. A contact hole is to be formed between the gate electrodes of the selection gate transistor.
Impurity ion implantation for forming the source/drain diffusion layer 28 of the memory cell and selection gate transistor is carried out simultaneously, and the source/drain diffusion layer 28 of the selection gate transistor is connected to the memory cell unit at one end and is electrically connected to a bit line or source line through the contact hole at the other end.
As mentioned above, since an impurity is implanted simultaneously into the channel regions of the memory cell and selection gate transistor, the impurity distributions of the both channel regions become the same as shown in FIG. 59.
It is known that a NAND type flash memory is adapted to prevent the data of an unselected block being read out at a time of data reading by turning off the selection gate transistor. For this purpose, in order to allow a threshold voltage of the selection gate transistor to satisfy the limitations of the cut-off characteristics, it is necessary to control the impurity concentrations in the channel regions.
The NAND type flash memory, on the other hand, is adapted to prevent electrons to be introduced into the floating gates 5 and 11 when "1" data is written to the memory cell (i.e. when a threshold value during an erased state is maintained without implanting electrons into the floating gate), by charging the memory cell to the initial potential through the bit line via the selection gate transistor connected to the memory cell, applying a write voltage and a transfer voltage to a selected word line and an unselected word line, respectively, and rising the potential of the channel region of the memory cell by means of capacitive coupling. Thus, decreasing each impurity concentrations of the respective channel regions reduces the channel capacity, which facilitates a rise in potential in the channel region and improves the "1" data writing efficiency.
Conventionally, however, since the impurity distributions of the channel regions of the memory cell and selection gate transistor are the same as stated above, when decreasing the impurity distribution in the channel regions in order to improve the "1" data writing efficiency as mentioned before, a trade-off relationship arises in which the threshold voltage of the selection gate transistor decreases and an off-leak current increases.
According to an aspect of the present invention, there is provided a non-volatile semiconductor memory device, comprising:
a memory cell unit including at least one memory cell transistor formed on a semiconductor substrate and having a laminated structure of a charge accumulation layer and a control gate layer; and
a selection gate transistor one of the source/drain diffusion layer regions of which is connected to a bit line or a source line and the other of the source/drain diffusion layer regions of which is connected to the memory cell unit,
wherein the shape of the source diffusion layer region of the selection gate transistor is asymmetrical to the shape of the drain diffusion layer region thereof below the selection gate transistor.
According to another aspect of the present invention, there is provided a non-volatile semiconductor memory device, comprising:
a memory cell unit including at least one memory cell transistor formed on a semiconductor substrate and having a laminated structure of a charge accumulation layer and a control gate layer; and
a selection gate transistor one of the source/drain diffusion layer regions of which is connected to a bit line or a source line and the other of the source/drain diffusion layer regions of which is connected to the memory cell unit,
wherein the channel region between the source diffusion layer region of the selection gate transistor and the drain diffusion layer region thererof includes a region having a different concentration of impurity at the positions thereof which have the same depth from the boundary between the semiconductor substrate and a gate insulation film.
According to a further aspect of the present invention, there is provided a method of manufacturing a non-volatile semiconductor memory device, comprising:
a step of forming gate electrodes of a memory cell transistor and a selection gate transistor having a first conductive type channel region on a semiconductor substrate;
a step of forming a mask having an aperture on the side of the gate electrode of the selection gate transistor opposite to the side thereof facing the memory cell transistor; and
a step of implanting a first conductive type impurity in the semiconductor substrate through the aperture of the mask.
According to a further aspect of the present invention, there is provided a method of manufacturing a non-volatile semiconductor memory device, comprising:
a step of forming gate electrodes of a memory cell transistor and a selection gate transistor having a first conductive type channel region on a semiconductor substrate;
a step of forming a first insulation film on the sidewalls of the gate electrodes of the memory cell transistor and the selection gate transistor;
a step of forming a second insulation film on the first insulation film;
a step of forming a mask having an aperture on the side of the gate electrode of the selection gate transistor opposite to the side thereof facing the memory cell transistor;
a step of removing the second insulation film through the aperture of the mask; and
a step of implanting a first conductive type impurity in the semiconductor substrate through the aperture of the mask.
According to a further aspect of the present invention, there is provided a method of manufacturing a non-volatile semiconductor memory device, comprising:
a step of forming gate electrodes of a memory cell transistor and a selection gate transistor having a first conductive type channel region on a semiconductor substrate;
a step of opening a contact hole through the source/drain diffusion layer region of the selection gate transistor in self-alignment with respect to the gate electrode of the selection gate transistor; and
a step of implanting a first conductive type impurity in the semiconductor substrate through the contact hole.
According to a further aspect of the present invention, there is provided a method of manufacturing a non-volatile semiconductor memory device, comprising:
a step of forming gate electrodes of a memory cell transistor and selection gate transistors having a first conductive type channel region on a semiconductor substrate in such a manner that the space between the gate electrodes of the selection gate transistors is set larger than the space between the gate electrode of the memory cell transistor and the gate electrode of a selection gate transistor; and
a step of implanting a first conductive type impurity in the semiconductor substrate at such an angle that the impurity is not implanted between the gate electrode of the memory cell transistor and the gate electrode of the selection gate transistor and is implanted between the gate electrodes of the selection gate transistors.
According to a further aspect of the present invention, there is provided a non-volatile semiconductor memory device, comprising:
a plurality of memory cell units comprising at least one memory cell having a laminated gate structure of a charge accumulation layer and a control gate layer formed on a semiconductor substrate through a gate insulation film; and
a plurality of selection gate transistors each having a gate electrode formed through the gate insulation film and a source/drain diffusion layer one of which is connected to each memory cell unit and the other of which is electrically connected to a bit line or a source line,
wherein the plurality of selection gate transistors include a pair of first selection gate transistors disposed in confrontation with each other across a contact portion connected to the bit line or to the source line and having substantially the same structure; and
the channel regions of the pair of selection gate transistors have the same impurity concentration in a gate length direction at a depth equal from the boundary between the semiconductor substrate and the gate insulation film as well as the concentration distribution of impurity in the channel regions of the pair of selection gate transistors is different from that of the channel region of the memory cell.
According to a further aspect of the present invention, there is provided a non-volatile semiconductor memory device, comprising:
a plurality of memory cell units comprising at least one memory cell having a laminated gate structure of a charge accumulation layer and a control gate layer formed on a semiconductor substrate through a gate insulation film; and
a plurality of selection gate transistors each having a gate electrode formed through a gate insulation film formed of the same layer as the gate insulation film of the memory cell and a source/drain diffusion layer one of which is connected to each memory cell unit and the other of which is electrically connected to a bit line or a source line,
wherein the plurality of selection gate transistors have a pair of first selection gate transistors disposed in confrontation with each other across a contact portion connected to the bit line or to the source line and having substantially the same structure; and
the effective impurity concentration of the source/drain diffusion layer of the pair of first selection gate transistors is lower than that of the source/drain diffusion layer of the memory cell at a depth equal from the boundary between the semiconductor substrate and the gate insulation film.
According to a further aspect of the present invention, there is provided a non-volatile semiconductor memory device, comprising:
a plurality of memory cell units comprising at least one memory cell having a laminated gate structure of a charge accumulation layer and a control gate layer formed on a semiconductor substrate through a gate insulation film; and
a plurality of selection gate transistors each having a gate electrode formed through a gate insulation film formed of the same layer as the gate insulation film of the memory cell and a source/drain diffusion layer one of which is connected to each memory cell unit and the other of which is electrically connected to a bit line or a source line,
wherein the plurality of selection gate transistors have first selection gate transistors and second selection gate transistors disposed in confrontation with each other through a contact portion connected to the bit line or the source line, and the structure of the first selection gate transistors is substantially different from that of the second selection gate transistors;
the channel regions of the first selection gate transistors have the same impurity concentration in a gate length direction at a depth equal from the boundary between the semiconductor substrate and the gate insulation film as well as the concentration distribution of impurity of the channel regions of the first selection gate transistors is different from that of the channel region of the memory cell; and
each of the second selection gate transistors has a portion in which the impurity concentration of the channel region thereof is different in a gate length direction at the above depth from the boundary between the semiconductor substrate, and the impurity concentration of the portion of the channel region containing a high concentration impurity is the same as that of the channel region of each of the first selection gate transistors at the above depth from the boundary between the semiconductor substrate and the gate insulation film.
According to a further aspect of the present invention, there is provided a non-volatile semiconductor memory device, comprising:
a plurality of memory cell units comprising at least one memory cell having a laminated gate structure of a charge accumulation layer and a control gate layer formed on a semiconductor substrate through a gate insulation film; and
a plurality of selection gate transistor each having a gate electrode formed through a gate insulation film that is formed simultaneously with the gate insulation film of the memory cell and a source/drain diffusion layer one of which is connected to each memory cell unit and the other of which is electrically connected to a bit line or a source line,
wherein the plurality of selection gate transistors have first selection gate transistors and second selection gate transistors disposed in confrontation with each other through a contact portion connected to the bit line or the source line, and the structure of the first selection gate transistors is substantially different from that of the second selection gate transistors;
the impurity concentration of the source diffusion layer of each of the first selection gate transistors is the same as that of the drain diffusion layer thereof at a depth equal from the boundary between the semiconductor substrate and the gate insulation film as well as the effective impurity concentration of the source/drain diffusion layer of each of the first selection gate transistors is lower than that of the source/drain diffusion layer of the memory cell; and
the impurity concentration of the source diffusion layer of each of the second selection gate transistors is different from that of the drain diffusion layer thereof at a depth equal from the boundary between the semiconductor substrate and the gate insulation film as well as the impurity concentration of the source diffusion layer or the drain diffusion layer, which is connected to the bit line or the source line, of each of the second selection gate transistors is the same as that of the source/drain diffusion layer of each of the first selection gate transistors.
According to a further aspect of the present invention, there is provided a non-volatile semiconductor memory device, comprising:
a plurality of memory cell units comprising at least one memory cell having a laminated gate structure of a charge accumulation layer and a control gate layer formed on a semiconductor substrate through a gate insulation film; and
a plurality of selection gate transistor each having a gate electrode formed through a gate insulation film that is formed simultaneously with the gate insulation film of the memory cell and is substantially the same therewith and a source/drain diffusion layer one of which is connected to each memory cell unit and the other of which is electrically connected to a bit line or a source line,
wherein the plurality of selection gate transistors have a pair of selection gate transistors disposed in confrontation with each other across a contact portion connected to the bit line or to the source line; and
the pair of selection gate transistors have substantially the same structure, each of the pair of transistors has a portion in which the impurity concentration of the channel region thereof is different in a gate length direction at a depth equal from the boundary between the semiconductor substrate and the gate insulation film, and the concentration distribution of impurity of the channel region of each transistor is different from that of the channel region of the memory cell.
According to a further aspect of the present invention, there is provided a non-volatile semiconductor memory device, comprising:
a plurality of memory cell units comprising at least one memory cell formed on a semiconductor substrate through a gate insulation film and having a laminated gate structure of a charge accumulation layer and a control gate layer; and
a plurality of selection gate transistor each having a gate electrode formed through a gate insulation film that is formed simultaneously with the gate insulation film of the memory cell and is substantially the same therewith and a source/drain diffusion layer one of which is connected to each memory cell unit and the other of which is electrically connected to a bit line or a source line,
wherein the plurality of selection gate transistors have a pair of selection gate transistors disposed in confrontation with each other across a contact portion connected to the bit line or to the source line and having substantially the same structure; and
the impurity concentration of the source diffusion layer of each of the pair of selection gate transistors is different from that of the drain diffusion layer thereof at a depth equal from the boundary between the semiconductor substrate and the gate insulation film as well as the effective impurity concentration of the source diffusion layer or the drain diffusion layer, which is connected to the bit line or the source line, of each selection gate transistor is lower than that the source/drain diffusion layer of the memory cell.
According to a further aspect of the present invention, there is provided a method of manufacturing a non-volatile semiconductor memory device, comprising:
forming the first conductive type channel regions of a memory cell and selection gate transistors on the surface of a semiconductor substrate;
forming an impurity doping mask having apertures corresponding to only the channel regions of the selection gate transistors on the semiconductor substrate; and
doping a first conductive type impurity in the semiconductor substrate through the mask.
According to a further aspect of the present invention, there is provided a method of manufacturing a non-volatile semiconductor memory device, comprising:
forming first conductive type channel regions of a memory cell and selection gate transistors on the surface of a semiconductor substrate;
forming a gate insulation film on the semiconductor substrate;
forming a part of gate electrodes on the gate insulation film;
forming element isolation regions on the surface layer portion of the semiconductor substrate in self-alignment using the part of gate electrodes as a mask;
forming an impurity doping mask having apertures corresponding to only the channel regions the selection gate transistors on the semiconductor substrate; and
doping a first conductive type impurity in the semiconductor substrate via the part of the gate electrodes through the mask.
According to a further aspect of the present invention, there is provided a method of manufacturing a non-volatile semiconductor memory device, comprising:
forming first conductive type channel regions of a memory cell and selection gate transistors on the surface of a semiconductor substrate;
forming a gate insulation film on the semiconductor substrate;
forming a part of gate electrodes on the gate insulation film;
forming element isolation regions on the surface layer portion of the semiconductor substrate in self-alignment using the part of the gate electrodes as a mask;
forming an impurity doping mask having apertures corresponding to the channel regions the selection gate transistors and to the element isolation region of a transistor constituting the peripheral circuit of memory cell units; and
doping a first conductive type impurity in the semiconductor substrate via the part of the gate electrodes through the mask.
Embodiments of the present invention will be described below with reference to the drawings. In the following description, corresponding components are denoted by the same reference numerals over the entire figures.
First Embodiment
A first embodiment of the present invention is arranged such that the cut-off characteristic of selection gate transistors connected to a memory cell unit are improved by implanting an impurity having the same conductive type as that of channels in the selection gate transistors on the bit line or source line contact sides thereof. A NAND type non-volatile semiconductor memory device according to the first embodiment of the present invention will be described below in detail together with a method of manufacturing the same.
First, a buffer oxide film 2 is formed on the surface of a p-type silicon substrate 1 as shown in FIG. 1. Then, a resist (not shown) is coated and a resist film is formed. Apertures corresponding to a well and a channel region are opened through the resist film by photolithography. Then, an n-type impurity, for example, phosphorus (P) and a p-type impurity, for example, boron (B) are ion-implanted using the resist film as a mask, and n-type well (not shown) and a p-type well/channel region 3 is formed in the p-type silicon substrate 1. Thereafter, the resist film is removed.
As shown in
Thereafter, as shown in
As shown in
As shown in
Thereafter, silicon dioxide (O)/silicon nitride (N)/silicon dioxide (O), polysilicon/tungsten silicide (WSi), and silicon nitride are sequentially deposited. With this deposition, as shown in
Next, a resist film (not shown) is formed, and patterns corresponding to the gate electrodes (control gates and selection gates) are formed in the resist film using photolithography. The silicon nitride film 15 is etched using the resist film as a mask. After the resist film is removed, the polysilicon/WSi laminated film 14, the ONO film 13, the polysilicon film 11, and the polysilicon film 5 are sequentially etched using the silicon nitride film 15 as a mask, and two-layer gate electrodes are formed.
Next, as shown in
Subsequently, as shown in
At this time, the region 22 the concentration of the p-type impurity of which is higher than that of the p-type well/channel regions 3 is formed in the p-type silicon substrate 1 (the p-type well/channel regions 3 in this embodiment) between the gate electrodes 19 of the selection gate transistors. As a result, the effective concentration of impurity (the concentration of impurity obtained by subtracting the concentration of the p-type impurity from the concentration of the n-type impurity) of the n-type source/drain diffusion layer region 23 on the sides of the selection gate transistors is made lower than the effective concentration of impurity of the n-type source/drain diffusion layer regions 24 on the sides of the memory cell transistors.
Further, as shown in
It should be noted that when no p-type impurity would be ion-implanted between the gate electrodes of the selection gate transistors as exemplified in the conventional example, the depth D1 is equal to the depth D2 below the gate electrodes 19 of the selection gate transistors as shown in FIG. 12.
Further, as shown in
Note that when no p-type impurity is ion-implanted between the gate electrodes of the selection gate transistors as exemplified in the conventional example, the distance L1 is equal to the distance L2 as shown in FIG. 14.
As shown in
Further, the concentration of each impurity of the channel region, which comes into contact with a source/drain diffusion layer region 24 in contact with a memory cell transistor, of the selection gate transistor is the same as the concentration of each impurity of the channel region which comes into contact with the n-type source/drain diffusion layer region 24 of the memory cell transistor.
The effective channel length of the selection gate transistors in this embodiment shown in
As described above, in this embodiment, the effective channel length of the selection gate transistors is increased by ion-implanting the p-type impurity that is the same as that of the channels between the gate electrodes of the selection gate transistors. With this arrangement, the short channel effect of the selection gate transistors is improved and the cut-off characteristics thereof are improved.
Further, the improvement of the cut-off characteristics of the selection gate transistors permits the concentration of the impurity in the channel regions of the memory cell transistors to be made lower than the conventional concentration thereof. As a result, data "1" writing characteristics are improved in the memory cell transistors. That is, resistance against non-selection write stress is more improved in, for example, a NAND type non-volatile semiconductor memory device having a memory unit containing a plurality of memory cell transistors as in this embodiment.
Further, in this embodiment, the threshold voltage of the selection gate transistors can be controlled independently of the threshold voltage of the memory cell transistors in the range in which the threshold voltage of the selection gate transistors is set higher than that of the memory cell transistors. As a result, the various characteristics of the memory cell transistors such as data holding characteristics, resistance against read stress, and the like can be improved while maintaining the cut-off characteristics of the selection gate transistors.
That is, the advantage of the embodiment is not particularly limited to the NAND type non-volatile semiconductor memory device but can be effectively obtained by any non-volatile semiconductor memory device having a structure in which selection gate transistors are connected to memory cell transistors.
Next, as shown in
Next, as shown in
Note that, in this embodiment, after the p-type impurity is ion-implanted between the gate electrodes of the selection gate transistors, the n-type impurity is ion-implanted to form the n-type source/drain diffusion layer regions 23 and 24. However, the p-type impurity may be ion-implanted between the gate electrodes of the selection gate transistors after the n-type impurity is ion-implanted to form the n-type source/drain diffusion layer regions 23 and 24.
Second Embodiment
A second embodiment of the present invention relates to a NAND-type non-volatile semiconductor memory device having such a structure that an insulation film such as a TEOS film is formed on the sidewalls of the gate electrodes of memory cell transistors and selection gate transistors, a bit line or source line contact hole is opened between the gate electrodes of the selection gate transistors in self-alignment, and the TEOS film between the gate electrodes of the selection gate transistors and the contact hole is removed. In this device, the cut-off characteristic of the selection gate transistors is improved by implanting an impurity having the same conductive type as that of channels to the selection gate transistors on the bit line or source line contact hole sides thereof. The device according to the second embodiment will be described below together with a method of manufacturing the same.
First, the two-layer gate electrodes shown in
Next, as shown in
Next, as shown in
Further, the depth of the pn junction of the source/drain diffusion layer region 32 on the sides of the selection gate transistors taken in a source-drain direction is made shallower than the depth of the n-type source/drain diffusion layer regions 28 on the sides of the memory cell transistors in the source-drain direction.
Accordingly, the shape of the n-type source/drain diffusion layer regions 28 of the selection gate transistors is made asymmetrical to the shape of the source/drain diffusion layer region 32 thereof. Thus, the distance, where the n-type source/drain diffusion layer region 32 connected to a bit line or a source line overlaps the gate electrode, is made smaller than the distance, where the n-type source/drain diffusion layer region 28 connected to a memory cell transistor overlaps the gate electrode, at the positions thereof which have the same depth from the boundary between the p-type silicon substrate 1 (the p-type well/channel regions 3 in this embodiment) and a gate insulation film 4 (for example, positions along the line B-B in FIG. 20).
The impurity concentration distribution of at positions along the line B-B shown in
Further, according to the second embodiment of the present invention, the ion implantation is performed using the resist film 30 for removing the TEOS films 29 as the mask. With this operation, a photolithography step having only the purpose of carrying out of ion implantation to form the region the concentration of impurity of which is higher than that in the channel can be omitted, whereby a manufacturing cost can be reduced.
Note that the ion implantation that is described with reference to
Next, as shown in
Thereafter, as described above with reference to
Third Embodiment
A third embodiment of the present invention relates to a NAND type non-volatile semiconductor memory device in which a bit line or source line contact hole is opened between the gate electrodes of selection gate transistors in self-alignment. In this device, the cut-off characteristics of the selection gate transistors are improved by implanting an impurity having the same conductive type as that of channels in the selection gate transistors on the bit line or source line contact sides thereof through a contact hole. The device according to the third embodiment of the present invention will be described below together with a method of manufacturing the same.
First, the two-layer gate electrodes shown in
Next, as shown in
Next, as shown in
Next, as shown in
Further, the depth of the pn junction of the source/drain diffusion layer region 39 on the sides of the confronting selection gate transistors in a source-drain direction is made shallower than the depth of the n-type source/drain diffusion layer regions 36 on the sides of the memory cell transistors in the source-drain direction.
Accordingly, the shape of the n-type source/drain diffusion layer regions 36 of the selection gate transistors is made asymmetrical to shape of the source/drain diffusion layer region 39 thereof. Thus, the distance, where the n-type source/drain diffusion layer region 39 connected to a bit line or a source line overlaps the gate electrode, is made smaller than the distance, where the n-type source/drain diffusion layer region 36 connected to a memory cell transistor overlaps the gate electrode, at the positions thereof which have the same depth from the boundary between the p-type silicon substrate 1 (the p-type well/channel regions 3 in this embodiment) and a gate insulation film 4 (for example, positions along the line B-B in FIG. 24).
The impurity concentration distribution at positions along the line B-B shown in
Further, according to the third embodiment of the present invention, the cut-off characteristics of the selection gate transistors can be improved without increasing a photolithography step aiming at performing only ion implantation for forming the region the concentration of impurity of which is higher than that in the channel by performing the ion implantation to the gate electrodes of the selection gate transistors through the contact hole formed in self-alignment even if a photolithography step for exfoliating a TEOS film as described in the second embodiment is omitted. Therefore, the third embodiment can reduce a manufacturing cost as compared with, for example, the first embodiment of the present invention.
However, even if a photolithography step for removing the TEOS film as described in the second embodiment is employed, it is also possible to perform ion implantation to the gate electrodes of the selection gate transistors through the contact hole formed in self-alignment as in the third embodiment of the present invention. The manufacturing cost can be advantageously reduced also in this case.
Then, an n-type impurity is ion-implanted in the p-type silicon substrate 1 (in this embodiment, the n-type source/drain diffusion layer 39) through the contact hole 37, when necessary, and thereby a region 40 having a higher concentration of the n-type impurity is formed.
Thereafter, as described above with reference to
Fourth Embodiment
In a fourth embodiment of the present invention, the cut-off characteristics of selection gate transistors are improved by implanting an impurity having the same conductive type as that of channels in the selection gate transistors on the bit line or source line contact sides thereof at an angle for permitting the impurity to be implanted only between the gate electrodes of the selection gate transistors without implanting the impurity between the gate electrodes of memory cell transistors.
First, the two-layer gate electrodes shown in
Next, as shown in
In general, in a non-volatile semiconductor memory device, the distance 1SGT between the gate electrodes of selection gate transistors is set larger than the distance between the gate electrodes of the memory cell transistors and the distance 1CELL between the gate of a memory cell transistor and the gate of a selection gate transistor because it is necessary to cause the space between the gate electrodes of the selection gate transistors to come into contact with a bit line or a source line. Thus, as shown in
An example for specifically prescribing the angle θ1 is an angle within such a range that when a straight line vertical to the p-type silicon substrate 1 is rotated about the lowest point of the sidewall, which is located on the side of a memory cell transistor, of the gate electrode of a selection gate transistor as a center of rotation, the straight line intersects the gate electrode of the memory cell transistor.
Further, an example for specifically prescribing the angle θ2 is an angle within such a range that when a straight line vertical to the p-type silicon substrate 1 is rotated about the lowest point of the sidewall of a selection gate transistor that confronts the gate electrode of the other selection gate transistor, the straight line does not intersect the gate electrode of the other confronting selection gate transistor.
Note that it is necessary to perform the ion implantation twice at angles "±θ" as shown by the arrows in
Next, as shown in
At this time, the region 41 the concentration of the p-type impurity of which is higher than that in the p-type well/channel regions 3 is formed in the p-type silicon substrate 1 (the p-type well/channel regions 3 in this embodiment) between the gate electrodes of the selection gate transistors. As a result, the effective concentration of impurity (the concentration of impurity obtained by subtracting the concentration of the p-type impurity from the concentration of the n-type impurity) of the n-type source/drain diffusion layer region 43 on the sides of the confronting selection gate transistors is made lower than the effective concentration impurity of the n-type source/drain diffusion layer regions 42 on the sides of the memory cell transistors.
Further, the depth of the pn junction of the source/drain diffusion layer region 43 on the sides of the confronting selection gate transistors is made shallower than the depth of the n-type source/drain diffusion layer regions 42 on the sides of the memory cell transistors in a source-drain direction.
Accordingly, the shape of the n-type source/drain diffusion layer regions 42 of the selection gate transistors is made asymmetrical to shape of the source/drain diffusion layer region 43 thereof. Thus, the distance, where the n-type source/drain diffusion layer region 43 connected to a bit line or a source line overlaps the gate electrode, is made smaller than the distance, where the n-type source/drain diffusion layer region 42 connected to a memory cell transistor overlaps the gate electrode, at the positions thereof which have the same depth from the boundary between the p-type silicon substrate 1 (the p-type well/channel regions 3 in this embodiment) and a gate insulation film 4 (for example, positions along the line B-B in FIG. 26).
The impurity concentration distribution at positions along the line B-B shown in
Further, according to the fourth embodiment, the cut-off characteristics of the selection gate transistors can be improved without increasing a photolithography step aiming at only ion implantation for forming the region the concentration of impurity of which is made higher than that of the channel by implanting the impurity so that the ion implantation angle θ satisfies the condition "θ1<θ<θ2". Therefore, the fourth embodiment can reduce a manufacturing cost as compared with, for example, the first embodiment of the present invention.
Next, as shown in
Thereafter, as described above with reference to
The embodiment shows an example in which the bit line or source line contact hole 26 is not formed in self-alignment with respect to the gate electrodes of the selection gate transistors. However, it is also possible to form the bit line or source line contact hole 26 in self-alignment.
Further, in this embodiment, the n-type impurity for forming the n-type source/drain diffusion layer regions 42 and 43 is ion-implanted after the p-type impurity is ion-implanted between the gate electrodes of the selection gate transistors at the angle θ that satisfies the condition "θ1<θ<θ2". However, the p-type impurity may be ion-implanted between the gate electrodes of the selection gate transistors at the above angle θ after the n-type impurity for forming the n-type source/drain diffusion layer regions 42 and 43 is ion-implanted.
While the element isolation regions 17 are formed after the well/channel regions 3 and the gate insulation film 4 are formed in the first to fourth embodiments, the well/channel regions 3 may be formed after the element isolation regions 17 are formed.
While not shown in the first to fourth embodiments, the n-type source/drain diffusion layer regions of the memory cell transistors and the selection gate transistors may be arranged as an LLD (lightly doped drain) structure by forming sidewalls to the gate electrodes thereof using a generally known method and by ion-implanting an n-type impurity more heavily.
While the first to fourth embodiments exemplify the non-volatile semiconductor memory device having the memory cell unit including the plurality of memory cell transistors, a non-volatile semiconductor memory device having a memory cell unit including at least one memory cell transistor can achieve the above advantage.
Further, it is a matter of course that the first to fourth embodiments can be embodied independently or by being appropriately combined with each other.
Furthermore, the first to fourth embodiments contain various steps of invention that can be also extracted by appropriately combining the plurality of constituent features disclosed in the first to fourth embodiments.
As described above, in each of the embodiments, there can be provided the non-volatile semiconductor memory device, which is excellent in the various characteristics of the memory cell transistors such as data writing characteristics, data maintaining characteristics, resistance against read stress as well as excellent in the cut-off characteristics of the selection gate transistors, and the method of manufacturing the same.
Fifth Embodiment
A fifth embodiment of the present invention describes a NAND type flash memory having a two-layer gate structure having such a structure in which the cut-off characteristics of a selection gate transistor are improved and a method of manufacturing the same with reference to
The fifth embodiment is characterized in that after channel regions of a memory cell and selection gate transistors are formed and element isolation regions are formed, a mask for patterning the channel regions of the selection gate transistors only is formed, then and an impurity is ion-implanted through a part of gate electrodes.
First, as shown in
Next, as shown in
However, the gate insulation film 4 is not limited to a silicon oxide film, but other films such as a silicon nitride film may be used.
Next, as shown in
Next, as shown in
Then, as shown in
Next, as shown in
Next, as shown in
After that, the polysilicon/WSi laminated film 14, ONO film 13, and polysilicon layers 11 and 5 are etched sequentially, whereby gate electrodes 19a and 19b of the selection gate transistors and gate electrodes 18a and 18b of the memory cells are formed.
Next, as shown in
In each channel region of the selection gate transistors, as mentioned above, the P-region 54 having a higher impurity concentration than that of the well region 3 has already been formed as mentioned above. Therefore, the effective impurity concentration (the concentration of impurity obtained by subtracting the concentration of the p-type impurity from the concentration of the n-type impurity) of a source/drain diffusion layer 23 between the two selection gate transistors located adjacent to each other is made smaller than the effective impurity concentration of a source/drain diffusion layer 24 of the memory cells.
In the source/drain impurity diffusion regions extending from either the memory cell or the selection gate transistor, the effective impurity concentration (the concentration of impurity obtained by subtracting the concentration of the p-type impurity from the concentration of the n-type impurity) of the source/drain diffusion layer 23 of the selection gate transistor is lower than that of the source/drain diffusion layer 24 of the memory cell, so that the depth of pn-junction in the source and drain diffusion layers 23 of the selection gate transistor is made smaller than that in the diffusion layers 24 of the memory cell.
That is, the depth of diffusion (i.e. depth of junction) of the source/drain diffusion layer 23 of the selection gate transistor is made different from that of the source/drain diffusion layer 24 of the memory cell. At a certain depth from the boundary between the semiconductor substrate or the p-well 3 and the gate insulation film 4, the distance is, where the source/drain diffusion layer of the selection gate transistor overlaps the gate electrode thereof, is made smaller than the distance 1c, where the diffusion layer of the memory cell overlaps the gate electrode thereof.
Further, the depth xs of pn-junction under the side ends of the gate electrode of the selection gate transistor in the depth direction of the diffusion layer is made smaller than the depth xc of pn-junction under the side ends of the gate electrode of the memory cell in the depth direction of the diffusion layer of the semiconductor substrate.
As is seen from this impurity concentration distribution, the effective impurity concentration in the channel region CH of the selection gate transistor is higher than the effective impurity concentration in the channel region CH of the memory cell. Besides, the effective impurity concentration in the source S/drain D diffusion layer region of the selection gate transistor is lower than the effective impurity concentration in the source S/drain D diffusion layer region of the memory cell.
Generally, as the impurity distribution in a well/channel region is provided as a result of multiple ion implantations and subsequent impurity diffusions through a thermal process, the final impurity distribution thereof is a total combination of the multiple distributions. In this embodiment, an impurity such as phosphorus (P) is introduced into the P-channel region of the selection gate transistor by ion implantation after forming the gate insulation film, a part of the gate electrode (the first polysilicon layer 5), and the element isolation region.
Therefore, the impurity concentration distribution in the channel region of the selection gate transistor in the substrate depth direction shown in
Further, the impurity P doped into the channel region of the selection gate transistor by ion implantation is not affected by the previous thermal processes when the gate insulation film and element isolation region were formed, which reduces diffusion of the impurity. Accordingly, as can be seen from a comparison between FIG. 40 and
That is, as with this embodiment, the controllability of the impurity distribution can be improved by additional ion implantation into the channel region of the selection gate transistor through a part of the gate electrodes after forming the element isolation region.
As discussed above, additional ion implantation of a p-type impurity into the channel region of the selection gate transistor rises the threshold voltage of the selection gate transistor due to the increase in impurity concentration in the channel region and reduces the short channel effect of the selection gate transistor due to the decrease in pn-junction depth, whereby the cut-off characteristics of the selection gate transistor are improved.
Besides, as the threshold voltage of the selection gate transistor can be controlled regardless of the memory cell, the impurity concentration in the well/channel region 3 can be reduced in the range that the threshold voltage of the select transistor is made higher than that of the memory cell, and thus the impurity concentration in the channel region of the memory cell, whereby resistance to the stress per writing at the time of non-selection can be improved.
Next, as shown in
After that, if necessary, a region 27 having a higher n-type impurity concentration is formed in the source/drain diffusion layer 23 between the gate electrodes of the adjacent selection gate transistors by supplying an n-type impurity through the contact hole 26 for ion implantation doping of the semiconductor substrate. When such a region 27 having a higher n-type impurity concentration is formed, it goes without saying that the n-type impurity concentration and effective impurity concentration between the selection gate transistors in
Subsequently, a conductor is formed within the contact hole 26, an interconnecting layer is formed according to a well known method, and then a protection film is deposited thereon, whereby a NAND type flash memory is completed.
According to this embodiment, an open pattern is prepared for a channel region 54 of a selection gate transistor so as not to expose a channel region of a memory cell. Therefore, as shown in
While the description of the embodiment discusses that the element isolation region is formed after forming the well/channel region 3 and gate insulation film 4, the well/channel region 3 and gate insulation film 4 may be formed after forming the element isolation region.
Further, in this embodiment, the source and drain diffusion layers of the memory cells and those of the selection gate transistors may be arranged as an LDD (lightly doped drain) structure which is achieved by forming sidewall oxide films (not shown) on the gate electrode sidewalls of the memory cells and selection gate transistors using a known method, and by ion-implanting a high concentration n-type impurity therein.
Sixth Embodiment
In the description of a sixth embodiment of the present invention, a case where the resist mask for ion implantation to the channel region of the select transistor used in the foregoing fifth embodiment is misaligned to the position intended to form the gate electrode of the select transistor, and a p-type impurity is not doped into a part of the channel region of the selection gate transistor is described with reference to FIG. 44 and FIG. 45. The same reference numerals as used in
First, as in the fifth embodiment, the steps illustrated in
Next, a resist mask is prepared, and a p-type impurity is doped in the channel region at a part corresponding to the selection gate transistor by ion implantation, whereby a region 54 having a higher impurity concentration than that of the memory cell is formed (see FIG. 44). Then, gate electrodes are formed as in the fifth embodiment (see FIG. 44).
At this time, if the resist mask is misaligned to the position intended to form a gate electrode of the selection gate transistor thereon, the aforementioned region 54 having a higher impurity concentration is not formed in the part of the channel region of the selection gate transistor 19a near the memory cell as shown in
On the other hand, a part of the channel region of the selection gate transistor on the side of a bit line or source line contact is formed with the higher impurity concentration region 54 than that of the well channel layer 3. Therefore, the effective impurity concentration (the concentration of impurity obtained by subtracting the concentration of the p-type impurity from the concentration of the n-type impurity) in the diffusion layer 57 of the selection gate transistor 19a on the contact side of the bit line or source line and the effective impurity concentration in the diffusion layer 57 of the selection gate transistor 19b is made smaller than the effective impurity concentration in the diffusion layer 24 of the memory cell.
Further the junction depths in the diffusion layer 57 on the contact side of the bit line or source line of the selection gate transistor 19a and in the diffusion layer 57 of the selection gate transistor 19b is made smaller than the junction depth in the diffusion layer of the memory cell as in the fifth embodiment.
In this impurity concentration distribution, a part of the channel region of the selection gate transistor 19a and the entire channel region of the select transistor 19b have higher effective impurity concentrations than the effective impurity concentration in the channel region of the memory cell.
Besides, the effective impurity concentration in the source/drain diffusion layer regions of the selection gate transistors is lower than the effective impurity concentration in the source/drain diffusion layer regions of the memory cells. Therefore, the threshold voltage of the selection gate transistors rises due to the increase in impurity concentration in the channel region and the short channel effect of the selection gate transistors reduces due to the decrease in pn-junction depth, whereby the cut-off characteristics of the selection gate transistors are improved.
As is mentioned above, as long as the misalignment of the resist mask 53 (
After that, by performing the similar steps as mentioned in the description of fifth Embodiment, a NAND type flash memory is completed. In this case, it goes without saying that the n-type impurity concentration and effective impurity concentration between the selection gate transistors shown in
While the description of this embodiment discusses that the element isolation region is formed after forming the well/channel region 3 and gate insulation film 4, the well/channel region 3 and gate insulation film 4 may be formed after forming the element isolation region.
Further, in this embodiment, the source/drain diffusion layers of the memory cells and those of the selection gate transistors may be arranged as an LDD structure which is achieved by forming sidewall oxide films (not shown) on the gate electrode sidewalls of the memory cells and selection gate transistors using a known method and by ion-implanting a high concentration n-type impurity thereinto.
Seventh Embodiment
In the description of the sixth embodiment, such a structure that one of the two opposite selection gate transistors which interpose a bit line or source line contact portion therebetween can not be additionally doped with a p-type impurity except a part of the channel region thereof was described. However, if desired cut-off characteristics are satisfied, the other selection gate transistor does not necessarily need to be doped with its entire channel region but a part thereof.
In the description of the seventh embodiment, a case where ion implantation is performed for only a part of each channel region of the two selection gate transistors which are oppositely disposed with a contact portion interposed therebetween is described with reference to FIG. 46 and FIG. 47. In
First, as in the fifth embodiment, the steps illustrated in
Next, a resist mask is prepared, and an area in the channel region corresponding to the selection gate transistor is doped with a p-type impurity by ion implantation, whereby a region 54 having a higher impurity concentration than that of the memory cell is formed (see FIG. 46). Then, gate electrodes are formed as in the fifth embodiment (see FIG. 46).
At this time, if a p-type impurity is doped into a substrate area smaller than the area intended to form a channel region of a selection gate transistor, such a region 54 that has a higher impurity concentration than that of the memory cell is not formed near the memory cell in the respective regions of the selection gate transistors 19a and 19b and this area remains with the same impurity concentration as that of the memory cell.
On the other hand, a part of the channel region of the selection gate transistor on the contact side of a bit line or source line is formed with a higher impurity concentration region 54 than that of the well channel layer 3. Therefore, the effective impurity concentration (the concentration of impurity obtained by subtracting the concentration of the p-type impurity from the concentration of the n-type impurity) in a diffusion layer 58 on the contact side of the bit line or source line of each selection gate transistors 19a and 19b is made smaller than the effective impurity concentration in the diffusion layer 24 of the memory cell.
Further, the junction depths in the diffusion layer 58 on the bit line contact side or source line contact side of the selection gate transistors 19a and 19b is made smaller than the junction depth in the diffusion layer of the memory cell as mentioned in the description of fifth Embodiment.
In this impurity concentration distribution, the effective impurity concentration in a part of the respective channel region of each of the selection gate transistors 19a and 19b is higher than the effective impurity concentration in the channel region of the memory cell. Besides, the effective impurity concentration in the source/drain diffusion layer region of the selection gate transistor is lower than the effective impurity concentration in the source/drain diffusion layer region of the memory cell. Therefore, the threshold voltage of the selection gate transistors rises due to the increase in impurity concentration in the channel region and the short channel effect of the selection gate transistors reduces due to the decrease in pn-junction depth, whereby the cut-off characteristics of the selection gate transistors are improved.
As is mentioned above, as long as the misalignment of the resist mask for additional ion implantation to the region intended for a channel region of the selection gate transistor is limited such that the selection gate transistors 19a and 19b satisfy the desired cut-off characteristics, the selection gate transistor can be controlled regardless of the memory cell within the range that the threshold voltage of the select transistor is made higher than that of the memory cell.
Thus, it becomes possible to reduce the impurity concentration in the well/channel region 3 and the impurity concentration in the channel region of the memory cell, whereby resistance to the stress per writing at the time of non-selection can be improved.
After that, by performing the similar steps as mentioned in the description of fifth Embodiment, a NAND type flash memory is completed. At this time, it goes without saying that the n-type impurity concentration and effective impurity concentration between the selection gate transistors shown in
While in this embodiment the element isolation regions are formed after forming the well/channel region 3 and gate insulation film 4, the well/channel region 3 and gate insulation film 4 can be formed after forming the element isolation regions.
Further, in this embodiment, the source/drain diffusion layers of the memory cells and those of the selection gate transistors may be arranged as an LDD structure which is achieved by forming sidewalls (not shown) on the gate electrodes of the memory cells and selection gate transistors using a known method and by ion-implanting a high concentration n-type impurity therein.
Eighth Embodiment
An eighth embodiment of the present invention describes a NAND type flash memory having such a structure that the element isolation characteristics of a transistor constituting the peripheral circuit of a memory cell array is improved and that the cut-off characteristics of selection gate transistors is improved and also describes a method of manufacturing the same.
In the eighth embodiment, after the formation of the channel regions of a memory cell and selection gate transistors and the formation of element isolation regions, a mask is formed to pattern the channel regions of the selection gate transistors and to pattern the element isolation region of a transistor constituting a peripheral circuit, and then an impurity is ion-implanted through a part of gate electrodes to a depth near to the element isolation regions and to a depth near to the gate insulation film of an activation region.
In this embodiment, a high breakdown-voltage transistor formed on a semiconductor substrate is exemplified as the transistor of the peripheral circuit with reference to
First, as shown in
Next, as shown in
Then, a P-type impurity (for example, boron (B)), is ion implanted to the depth of the element isolation region and to the depth near to the gate insulation film of the activation region, and a higher impurity concentration region 61, which prevents inversion just under the element isolation region of the high breakdown-voltage transistor, and the channel regions 54 of the selection gate transistors, which have a higher impurity concentration than that of the memory cell, are formed. At this time, a region 62, which has the same impurity concentration as that of the inversion preventing high impurity concentration region 61, is also formed in the activation region of the selection gate transistors to a depth near to the element isolation region.
Next, as shown in
The concentration distribution of impurity in the channel region of the memory cell along the line D--D in
That is, after the gate insulation film, a part of the gate electrodes, and the element isolation regions are formed, the impurity is ion-implanted in the channel regions of the selection gate transistors similarly to the fifth embodiment of the present invention. Thus, the impurity is diffused in a small amount because it is not affected by the thermal process that is performed when the gate insulation film and the element isolation regions are formed.
Accordingly, the concentration distribution of impurity in the channel regions of the selection gate transistors in the substrate depth direction shown in
Further, since the impurity is additionally ion-implanted in the selection gate transistors through a part of the gate electrodes after the element isolation regions is formed, the controllability of the impurity distribution can be improved.
Further, in this embodiment, the impurity, which is doped just under the element isolation region of the high breakdown-voltage transistor, is also doped in the activation regions of the selection gate transistors. Thus, an impurity distribution, which is similar to that in the element isolation region of the high breakdown-voltage transistor, is formed in the depth of the element isolation regions of the selection gate transistors as shown in FIG. 51.
As described above, the cut-off characteristics of the selection gate transistors are improved by of the additional ion-implantation of the p-type impurity in the channel regions of the selection gate transistors. This improvement is achieved by an increase in the threshold voltage of the selection gate transistors, which is caused by an increase in the impurity concentration in the well/channel region 3, and by the improvement of the short channel effect of the selection gate transistors due to a decrease in the pn junction depth.
Further, the selection gate transistors can be controlled independently of the memory cells in a range in which the threshold voltage of the selection gate transistors can be set higher than that of the memory cell. As a result, the impurity concentration of the well/channel region 3 can be reduced as well as the impurity concentration of the channel regions of the memory cells can be reduced, thereby resistance to the stress per wiring at the time of non-selection can be improved.
Furthermore, a photolithography step can be omitted, and thus a manufacturing cost can be reduced because the additional ion implantation is performed using the mask used when the impurity is ion-implanted in the inversion preventing high impurity concentration region in the element isolation region of the transistor that constitutes the peripheral circuit.
Thereafter, a NAND type flash memory is completed by performing the same steps as those described in the fifth embodiment of the present invention.
Note that while the element isolation regions are formed after the well/channel region 3 and the gate insulation film 4 are formed, the well/channel region 3 and the gate insulation film 4 may be formed after the element isolation regions are formed.
Further, in this embodiment, the source/drain diffusion layers of the memory cell and the selection gate transistors may be arranged as an LDD structure which is achieved by forming sidewalls (not shown) on the gate electrodes of the memory cells and selection gate transistors using a known method, and by ion-implanting a high concentration n-type impurity therein.
Ninth Embodiment
The above respective embodiments exemplify that the impurity is additionally ion-implanted in the selection gate transistors after the impurity is ion-implanted to form the well/channel region 3 of the memory cell unit and after the gate insulation film is formed.
In a ninth embodiment, there is described a structure of selection gate transistors in a NAND type flash memory having a two-layer gate structure and a method of manufacturing the same with reference to
First, a buffer oxide film 2 is formed on the surface of a p-type silicon substrate 1 as shown in FIG. 53. Then, a resist (not shown) is coated thereon, the resultant resist layer is patterned to form wells and channels using photolithography, and a well/channel region is formed similarly to the fifth embodiment of the present invention.
Thereafter, as shown in
Thereafter, similarly to the fifth embodiment, element isolation regions are formed, gate electrodes are formed, and source/drain diffusion layers 66, and the like of the selection gate transistors are formed, as shown in FIG. 55.
In
Generally, as the impurity distribution in the well/channel region 3 is provided as a result of multiple ion implantations and subsequent impurity diffusions through a thermal process, the final impurity distribution thereof is a total combination of the multiple distributions.
In this embodiment, since the impurity is ion-implanted in the channel regions of the selection gate transistors simultaneously with the ion-implantation of the impurity in the memory cells, the selection gate transistors and the memory cells are subjected to the same thermal process. Thus, the impurity concentration of the channel regions of the selection gate transistors in the vicinity of the gate insulation film thereof and in the semiconductor substrate thereof is higher than that of the channel regions of the memory cells in the vicinity of the gate insulation film thereof and in the semiconductor substrate thereof. However, both the impurities of the selection gate transistors and the memory cells have the same distribution shape.
Further, the impurity concentration of the impurity that is additionally ion-implanted in the channel regions of the selection gate transistors is lower than that of the fifth to seventh embodiments, and the junction depth of the source/drain diffusion layers of the selection gate transistors becomes deeper. However, the shape of the source/drain diffusion layers of the selection gate transistors and the impurity distribution of the channel regions thereof are qualitatively similar to those described in the fifth to seventh embodiments.
As described above, the cut-off characteristics of the selection gate transistors are improved by the additional ion-implantation of the p-type impurity in the channel regions of the selection gate transistors. This improvement is achieved by an increase in the threshold voltage of the selection gate transistors, which is caused by an increase in the impurity concentration in the channel regions, and by the improvement of the short channel effect of the selection gate transistors due to a decrease in the pn junction depth.
Further, the selection gate transistor can be controlled independently of the memory cell in a range in which the threshold voltage of the selection gate transistors can be set higher than that of the memory cells. As a result, the impurity concentration of the well/channel region 3 can be reduced as well as the impurity concentration of the channel regions of the memory cells can be reduced, thereby resistance to the stress per wiring at that time of non-selection can be improved.
Thereafter, the NAND type flash memory is completed by performing the same steps as those described in the fifth embodiment of the present invention.
Note that the element isolation regions are formed after the impurity is ion-implanted in the well/channel region 3 of the memory cell unit and in the channel regions of the selection gate transistors as well as after the gate insulation film 4 is formed in this embodiment. However, the impurity may be ion-implanted in the well/channel region 3 of the memory cell unit and in the channel regions of the selection gate transistors after the formation of the element isolation regions.
Further, in this embodiment, the source/drain diffusion layers of the memory cells and those of the selection gate transistors may be arranged as an LDD structure by forming sidewalls (not shown) on the gate electrodes using a know method and by ion-implanting an n-type impurity having a higher impurity concentration.
As described above, in each of the embodiments, there can be provided the flash memory, which can excellently realize the various characteristics of the memory cell transistor such as data writing characteristics, data maintaining characteristics, resistance against read stress as well as the cut-off characteristics of the selection gate transistor, and the method of manufacturing the flash memory.
Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.
| Patent | Priority | Assignee | Title |
| 7061040, | Nov 14 2003 | United Microelectronics Corp. | Memory device |
| 7071511, | Sep 21 2004 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device having adjacent selection transistors connected together |
| 7348627, | Sep 26 2000 | Kioxia Corporation | Nonvolatile semiconductor memory device having element isolating region of trench type |
| 7416935, | Sep 21 2004 | Kabushiki Kaisha Toshiba | Method of manufacturing nonvolatile semiconductor memory device having adjacent selection transistors connected together |
| 7420241, | May 31 2005 | Kabushiki Kaisha Toshiba | Semiconductor memory device and method of manufacturing the same |
| 7476958, | Jul 01 2003 | Samsung Electronics Co., Ltd. | Semiconductor wafer having different impurity concentrations in respective regions |
| 7538380, | Sep 26 2000 | TOSHIBA MEMORY CORPORATION | Nonvolatile semiconductor memory device having element isolating region of trench type |
| 7573092, | Sep 26 2000 | TOSHIBA MEMORY CORPORATION | Nonvolatile semiconductor memory device having element isolating region of trench type |
| 7732872, | Oct 25 2007 | GLOBALFOUNDRIES Inc | Integration scheme for multiple metal gate work function structures |
| 7790547, | Dec 28 2005 | Dongbu Electronics Co., Ltd. | Non-volatile memory device and method for fabricating the same |
| 7859905, | Aug 18 2005 | Renesas Electronics Corporation | Semiconductor storage device and method of manufacturing the same |
| 7920424, | Mar 30 2006 | DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT | Scalable electrically eraseable and programmable memory (EEPROM) cell array |
| 7939406, | Sep 26 2000 | TOSHIBA MEMORY CORPORATION | Nonvolatile semiconductor memory device having element isolating region of trench type |
| 8053828, | Mar 13 2009 | Kioxia Corporation | Nonvolatile semiconductor memory device and manufacturing method thereof |
| 8072020, | May 29 2008 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device |
| 8093650, | Mar 30 2006 | DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT | Scalable electrically eraseable and programmable memory (EEPROM) cell array |
| 8139408, | Sep 05 2006 | DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT | Scalable electrically eraseable and programmable memory |
| 8159019, | Dec 25 2007 | Kioxia Corporation | Semiconductor memory device with stacked gate including charge storage layer and control gate and method of manufacturing the same |
| 8198159, | Mar 26 2004 | Kabushiki Kaisha Toshiba | Semiconductor memory device and method of manufacturing the same |
| 8394689, | Dec 25 2007 | Kioxia Corporation | Semiconductor memory device with stacked gate including charge storage layer and control gate and method of manufacturing the same |
| 8502321, | Sep 09 2010 | Kabushiki Kaisha Toshiba | Semiconductor device and manufacturing method thereof |
| 8735966, | Mar 13 2009 | Kioxia Corporation | Nonvolatile semiconductor memory device and manufacturing method thereof |
| 8750041, | Sep 05 2006 | DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT | Scalable electrically erasable and programmable memory |
| Patent | Priority | Assignee | Title |
| 4939690, | Dec 28 1987 | Kabushiki Kaisha Toshiba | Electrically erasable programmable read-only memory with NAND cell structure that suppresses memory cell threshold voltage variation |
| 5646516, | Aug 31 1994 | Renesas Electronics Corporation | Reference voltage generating circuit |
| JP10209405, | |||
| JP10214494, | |||
| JP11224909, | |||
| JP1167938, | |||
| JP200068487, |
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