A semiconductor device is configured to prevent destruction of elements and/or miss-operation of the circuit by parasitic effects produced by parasitic transistors when a MOSFET of a bridge circuit is formed on a single chip. A schottky junction is formed by providing an anode electrode in an n well region where a source region, a drain region, and a p well region of a lateral MOSFET. A schottky barrier diode constituting a majority carrier device is connected in parallel with a PN junction capable of being forward-biased so that the PN junction is not forward-biased so that minority carriers are not generated, and thereby suppressing parasitic effects.
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7. A semiconductor device having a transistor, comprising:
a semiconductor substrate having a first semiconductor region of a second conductivity type on a first main surface of the semiconductor substrate;
a second semiconductor region of a first conductivity type formed within the first semiconductor region;
a drain region of the second conductivity type and a source region of the second conductivity type formed within the second semiconductor region;
a gate insulating film formed on the surface of the second semiconductor region and positioned between the drain region and the source region;
a gate electrode formed on the gate insulating film;
a source electrode connected to the second semiconductor region and the source region;
a drain electrode connected to the drain region; and
a schottky barrier diode having a cathode electrode connected to the drain electrode and an anode electrode connected to the source electrode,
wherein both the cathode and anode electrodes are on the first main surface of the semiconductor substrate, and
wherein both the anode and cathode electrodes are at the surface of the first semiconductor region, the anode electrode forming a schottky junction with the first semiconductor region and the cathode electrode forming an ohmic contact with the first semiconductor region.
1. A semiconductor device having a transistor comprising:
a semiconductor substrate of a first conductivity type;
at least one first semiconductor region of a second conductivity type formed on a first main surface of the semiconductor substrate;
a second semiconductor region of the first conductivity type formed within the first semiconductor region;
a drain region of the second conductivity type and a source region of the second conductivity type formed within the second semiconductor region;
a gate insulating film formed on the surface of the second semiconductor region and positioned between the drain region and the source region;
a gate electrode formed on the gate insulating film;
a source electrode connected to the second semiconductor region and the source region;
a drain electrode connected to the drain region; and
a schottky barrier diode having a cathode electrode connected to the drain electrode and an anode electrode connected to the source electrode,
wherein both the cathode and anode electrodes are on the first main surface of the semiconductor substrate, and
wherein both the anode and cathode electrodes are at the surface of the first semiconductor region, the anode electrode forming a schottky junction with the first semiconductor region, and the cathode electrode forming an ohmic contact with the first semiconductor region.
2. The semiconductor device according to
3. The semiconductor device according to
4. The semiconductor device according to
5. The semiconductor device according to
6. The semiconductor device according to
8. The semiconductor device according to
9. The semiconductor device according to
10. The semiconductor device according to
11. The semiconductor device according to
12. The semiconductor device according to
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In such a construction, since the p well region and n well region are both separated from the substrate by a PN junction, there is a high degree of freedom of design in regard to source potential and drain potential, and the construction is applicable to intelligent switching devices, in particular to applications having MOSFETs with a plurality of output stages, where the source potentials and drain potentials thereof are different. It should be noted that, although interlayer insulating films are provided between electrodes of different potential, such as between the gate electrode 8 and the source electrode 10, they are not shown in the following drawings.
Sometimes (see for example Laid-open Japanese Patent Publication Number H. 10-284731) parasitic action of the body diode of a MOSFET is suppressed by providing an embedded n+ region on a p substrate, providing an n epitaxial layer on top of that region, forming a Schottky barrier diode in this portion, and connecting it parallel in the same region with the body diode of the MOSFET.
Also, parasitic action of the body diode may be suppressed (see for example U.S. Pat. No. 4,811,065) by forming a Schottky barrier diode on the surface of the substrate (drain) region of the MOSFET, and connecting it parallel on the same chip with the body diode of the MOSFET.
Referring to
In
Furthermore, with a MOSFET of this construction, it is also possible to connect the n well region 2 and drain region 5 by common wiring.
Next,
When such a parasitic effect is produced by parasitic transistors, not only can element destruction occur due to current concentration on reverse recovery of the PN junction of minority carriers generated by forward-biasing of the PN junction, but also there is the problem of latching up easily occurring due to various parasitic elements which exist in CMOS circuit for example.
The present invention relates to a semiconductor device where a power semiconductor element and its drive circuit and protection circuit are integrated on the same chip. More specifically, the present invention relates to an intelligent semiconductor device where a Schottky barrier diode is incorporated to suppress parasitic transistor action of the power semiconductor element.
One aspect of the present invention is a semiconductor device having a transistor comprising a semiconductor substrate of a first conductivity type, at least one first semiconductor region of a second conductivity type formed on a first main surface of the semiconductor substrate. A second semiconductor region of the first conductivity type is formed within the first semiconductor region. A drain region of the second conductivity type and a source region of the second conductivity type are formed within the second semiconductor region. A gate insulating film is formed on the surface of the second semiconductor region and positioned between the drain region and the source region. A gate electrode is formed on the gate insulating film. A source electrode is connected to the semiconductor region of the first conductivity type and the source region. A drain electrode is connected to the drain region. A Schottky barrier diode having a cathode electrode connected to the drain electrode and an anode electrode connected to the source electrode are provided on the semiconductor substrate.
The Schottky barrier diode comprises an anode electrode and cathode electrode at the surface of the first semiconductor region, the anode electrode forming a Schottky junction with the first semiconductor region, and the cathode electrode forming an ohmic contact with the first semiconductor region. The drain region can comprise a high-concentration drain region of comparatively high concentration and an offset region of comparatively low concentration covering the high-concentration drain region. The anode electrode can form the Schottky junction with the offset region.
The semiconductor can further have a contact region of the second conductivity type formed at the surface of the first semiconductor region, and the ohmic contact is formed at the contact region. The Schottky junction and the ohmic contact can be proximate to each other.
The source electrode can be comb-shaped having a base portion forming a source collector electrode section. The Schottky junction can be formed directly below the source collector electrode section. A guard ring region of the first conductivity type can be formed at the periphery of the Schottky junction.
According to another aspect of the invention, a semiconductor device has a transistor comprising a semiconductor substrate of a second conductivity type and a first semiconductor region of a first conductivity type formed on a first main surface of the semiconductor substrate. A drain region of the second conductivity type and a source region of the second conductivity type are formed within the first semiconductor region. A gate insulating film is formed on the surface of the first semiconductor region and positioned between the drain region and the source region. A gate electrode is formed on the gate insulating film. A source electrode is connected to the first semiconductor region and the source region. A drain electrode is connected to the drain region. A Schottky barrier diode having a cathode electrode connected to the drain electrode and an anode electrode connected to the source electrode is provided on the semiconductor substrate.
The semiconductor device can further includes a second semiconductor region of the second conductivity type formed within the first semiconductor region. The Schottky barrier diode comprises an anode electrode and cathode electrode formed at the surface of the second semiconductor region. The anode electrode forms a Schottky junction with the second semiconductor region and the cathode electrode forms an ohmic contact with the second semiconductor region. A contact region of the second conductivity type can be formed at the surface of the second semiconductor region. The ohmic contact is formed at the contact region. The Schottky junction and the ohmic contact can be proximate to each other. The source electrode can be comb-shaped having a base portion forming a source collector electrode section. The Schottky junction can be formed directly below the source collector electrode section constituting the base of the comb.
The drain region can comprise a high-concentration drain region of comparatively high concentration and an offset region of comparatively low concentration covering the high-concentration drain region. A guard ring region of the first conductivity type can be formed at the periphery of the Schottky junction.
According to another aspect of the invention, a semiconductor device has a semiconductor substrate of a first or second conductivity type, a first semiconductor region of the second conductivity type formed on a first main surface of a semiconductor substrate, and a second semiconductor region of the first conductivity type formed at the surface of the first semiconductor region. An offset region of the second conductivity type is formed in the second semiconductor region. An anode electrode and a cathode electrode are formed at the surface of the offset region. The cathode electrode forms an ohmic contact with the offset region and the anode electrode forms a Schottky junction with the offset region. A field oxide film is formed at the surface of the offset region positioned between the anode electrode and the cathode electrode.
The semiconductor device can further include a first electrode connected to the anode electrode and forms an ohmic contact with the second semiconductor region at the surface thereof. It can further include a second electrode connected to the cathode electrode and forms an ohmic contact with the second semiconductor region at the surface thereof, the second electrode being connected to the cathode electrode.
The total impurity dosage per unit area of the offset region can be set such that, when voltage is applied to the anode electrode and between the first electrode and the cathode electrode in the direction in which the Schottky junction directly below the anode electrode is reverse-biased, and the first PN junction between the second semiconductor region and the offset region is reverse-biased, the offset region positioned between the anode electrode and the cathode electrode is totally depleted at a voltage equal to or below the breakdown voltage of the Schottky junction. Moreover, the total impurity dosage per unit area of the second semiconductor region can be set such that, when voltage is applied to the cathode electrode and between the second electrode and the first electrode in the direction in which the first PN junction is reverse-biased, and the second PN junction between the second semiconductor region and the first semiconductor region is reverse-biased, the second semiconductor region directly below the region positioned between the anode electrode and the cathode electrode is totally depleted at a voltage below the breakdown voltage of the first PN junction or the second PN junction.
The semiconductor can be configured to suppress parasitic effects by forward biasing a PN junction capable of being biased in the forwards direction so that minority carriers are not generated, and by connecting a Schottky barrier diode, constituting a majority carrier device, in parallel with the PN junction. The Schottky barrier diode connected in parallel with the PN junction capable of being forward-biased keeps the forward voltage thereof below the threshold voltage of the PN junction and thereby prevents parasitic effects and prevent destruction of elements and/or miss-operation of the circuit by parasitic effects caused by parasitic transistors.
Also, with this construction of the embodiment, since it is not possible for the current flowing in the Schottky barrier diode to flow through the n well region 2 directly below the p well region 3, the voltage drop in the n well region directly below the p well region produced by this current prevents the pn junction of the p well region and n well region being forward-biased and is therefore advantageous in suppressing parasitic effects. It should be noted that, although, in this embodiment, the Schottky junction 16 was formed in a position sandwiched by the n+ contact region 12 and the p well region 3, it would alternatively be possible for the n+ contact region 12 to be formed in a position sandwiched by the Schottky junction 16 and the p well region 3. Or, if required, the n+ contact region 12 and the Schottky junction 16 can be arranged alternately. By thus forming the Schottky junction 16 in the n well region 2 rather than in the drain region (n offset region), the Schottky barrier diode can be formed in the MOSFET peripheral region, thereby facilitating wiring. Consequently, the forward voltage of the Schottky barrier diode can be kept to a satisfactory low level, thereby making it possible to prevent the occurrence of parasitic effects due to forward-biasing of the PN junction.
With the first embodiment, since the n well region is connected with the drain, the Schottky junction being formed on the n well region rather than the drain of a transverse type MOSFET, a Schottky junction of comparatively large area can easily be formed. Also, since the n well region is deeper and of lower concentration than the n offset region, the Schottky barrier diode voltage-withstanding ability can easily be made greater than the voltage-withstanding ability of the MOSFET, so that there is no possibility of the voltage-withstanding ability between the source and drain of the MOSFET being restricted by the voltage-withstanding ability of the Schottky barrier diode that is connected in parallel therewith.
Also, it is of course possible to ensure the desired area of the Schottky barrier diode by combining the arrangement construction of the Schottky junction of FIG. 2 and the arrangement construction of the Schottky junction of FIG. 4. With the second embodiment, the Schottky junction is formed directly below the wiring of the source current collector electrode, so that the Schottky barrier diode can be formed in an area-efficient manner.
Since the n offset region 6 is formed by the uppermost surface diffusion of the triple diffusion, it is difficult to achieve sufficiently deep diffusion. Consequently, in order to obtain sufficient voltage-withstanding ability and low forward resistance, it is desirable to employ the so-called RESURF conditions (total impurity dosage per unit area 1E12 cm2) for the concentration and depth of the n offset region 6. In this case, it is necessary for the cathode electrode 24 and p well region 3 to be in a withstand-voltage maintaining condition, i.e., reverse biased during reverse biasing of the Schottky junction. Furthermore, in order to prevent flow of punch-through current between the anode electrode 15 and p well region 3, it is desirable to make the potential of the p well electrode 28 and the potential of the anode electrode 15 the same potential. Consequently, in this embodiment, the p well electrode 28 and the anode electrode 15 are connected by wiring.
Furthermore, in the case of the p well region 3 also, since this is a diffusion region within the n well region 2, it is likewise difficult to achieve sufficiently deep diffusion. Consequently, in order to obtain a sufficiently large voltage-withstanding ability, it is desirable to employ so-called double RESURF conditions (total impurity dosage per unit area 2E12 cm2) for the concentration and depth of the p well region 3. In this case also, likewise, in order to achieve reverse biasing between the n well region 2 and the p well region 3, and prevent flow of punch-through current between the cathode electrode 24 and the n well region 2, it is desirable to make the n well electrode 13 and the cathode electrode 24 of the same potential. Consequently, in this embodiment, the cathode electrode 24 and the n well electrode 13 are connected by wiring.
In the case of the n well region 2, since this is not formed within an even deeper diffusion region, it is comparatively easy to achieve low concentration diffusion. However, when high voltage-withstanding ability is required, it is likewise effective to employ double RESURF conditions (total impurity dosage 2E12 cm2) for the concentration and depth of the n well region 2. Likewise, in this case, in order to prevent punch-through, and to reverse-bias the n well region 2 and the p type semiconductor substrate 1, it is effective to make the back face electrode 14 and the p well electrode 28 of the same potential. Also, this construction is useful in that, by forming these on the same substrate with a transverse type MOSFET and respectively connecting the drain electrode 11 and cathode electrode 24, as well as the source electrode 10 and the anode electrode 15 by short wirings, inductance is reduced to a minimum, making it possible to effectively suppress the action of parasitic diodes and parasitic transistors of the MOSFET. Also, by making the manufacturing conditions of the n well region, the p well region, and the n offset region, etc., common for the MOSFET and the Schottky barrier diode, the voltage-withstanding ability and ON resistance (forward voltage) of the MOSFET and the Schottky barrier diode can be simultaneously optimized. By making this construction a comb-shaped construction by adopting a striped configuration in the depth direction of the cross-sectional view and by repeating the construction between the two single-dotted chain lines in the figures as the pitch, the forward resistance can of course be reduced. This applies also to the other embodiments.
This construction can also be formed within the same n well region as the lateral MOSFET or can be formed in a different n well region. Forming this within the same n well region is advantageous in that the area occupied within the chip can be reduced. However, by forming in separate n well regions, it becomes possible to make the potentials of the n well regions different. This is therefore effective in suppressing parasitic effects other than of the MOSFET, such as, for example, suppression of parasitic effects when the input potential drops from the reference potential to below the threshold voltage of the PN junction or when it becomes higher than the power source voltage by more than the threshold voltage of the PN junction, by employing a Schottky diode of this construction in a parallel connection with or as a replacement for the input protection PN diode.
With the present invention, the inconveniences due to parasitic effects tending to be produced with an inductive (L) load by the complicated junction construction when a plurality of MOSFETs of different terminal potentials are integrated within a single semiconductor chip can be prevented, i.e., parasitic effects of parasitic transistors can be prevented, by insertion of a Schottky barrier diode between the source and drain or between the source and n well region of the MOSFETS. Thus, since a Schottky barrier diode is formed on the same semiconductor chip as the MOSFET, it can easily be accommodated in the package, making it possible to reduce the installation area. Also, since the forward-biased pn junction of the MOSFET can be bypassed by a Schottky barrier diode in the vicinity thereof, there is no possibility of current bypassing to the Schottky barrier diode being obstructed due to the inductance of the wiring.
Given the disclosure of the present invention, one versed in the art would appreciate that there may be other embodiments and modifications within the scope and spirit of the present invention. Accordingly, all modifications and equivalents attainable by one versed in the art from the present disclosure within the scope and spirit of the present invention are to be included as further embodiments of the present invention. The scope of the present invention accordingly is to be defined as set forth in the appended claims.
The disclosures of the priority applications, JP PA 2001-355798 and JP PA-2002-262230, in their entirety, including the drawings, claims, and the specification thereof, are incorporated herein by reference.
Yoshida, Kazuhiko, Kumagai, Naoki, Ikura, Yoshihiro, Jimbo, Shinichi, Fujihira, Tatsuhiko, Harada, Yuuichi
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