The present invention provides an electro-magnetic interference protection circuit for a clock buffer. The present invention not only uses a ferrite bead that is serially connected with the power source of the clock buffer to protect the clock buffer from electro-magnetic interference. The ferrite bead also connects in parallel with a capacitor to reduce the distortion of a clock signal out-putting by the clock buffer due to the ferrite bead, thereby making the communication devices work properly.
|
6. An electro-magnetic interference protection method for a clock buffer, comprising the steps of:
connecting a ferrite bead in serial with a power source of said clock buffer to protect said clock buffer from electro-magnetic interference; and
connecting a capacitor in parallel with said ferrite bead to reduce the distortion of a clock signal out-putting by said clock buffer due to said ferrite bead.
1. An electro-magnetic interference protection circuit for a clock buffer, comprising:
a clock buffer, for receiving a clock signal and buffer-outputting said clock signal;
a ferrite bead, wherein said ferrite bead is connected in serial with a power source of said clock buffer to protect said clock buffer from electro-magnetic interference; and
a capacitor, wherein said capacitor is connected in parallel with said ferrite bead to reduce the distortion of said clock signal due to said ferrite bead.
2. The electro-magnetic interference protection circuit for a clock buffer of
3. The electro-magnetic interference protection circuit for a clock buffer of
4. The electro-magnetic interference protection circuit for a clock buffer of
5. The electro-magnetic interference protection circuit for a clock buffer of
7. The electro-magnetic interference protection method for a clock buffer of
8. The electro-magnetic interference protection method for a clock buffer of
9. The electro-magnetic interference protection method for a clock buffer of
10. The electro-magnetic interference protection circuit for a clock buffer of
|
This application claims the priority benefit of Taiwan application serial no. 92115368, filed on Jun. 6, 2003.
1. Field of the Invention
This invention generally relates to an electro-magnetic interference protection circuit and a method, and more particularly toan electro-magnetic interference protection circuit and a method for a clock buffer.
2. Description of Related Art
As the technology advances, Internet becomes one of the most important resources for people to obtain knowledge and is a powerful tool for commercial transactions. Modem has been used in personal computers for Internet connection. Today, high speed Internet solutions such as ADSL products are widely used for better quality. In those communication devices, the transceiver ICs are driven by clock signals that are distributed from clock buffers. Hence, how to protect the clock buffers from electro-magnetic interference (“EMI”) is an important issue.
Conventionally, a ferrite bead is serially connected to the power source of the clock buffer for EMI protection. How ever, because of its inductor characteristic, the ferrite bead also affects the waveform of the clock signal.
An object of the present invention is to provide an electro-magnetic interference protection circuit and method for a clock buffer to protect the clock buffer from EMI and to keep the communication device work properly.
In accordance with the above objects and other advantages of the present invention, an electro-magnetic interference protection circuit for a clock buffer is provided. The electro-magnetic interference protection circuit comprises a clock buffer for receiving a clock signal and buffer-outputting the clock signal; a ferrite bead, the ferrite bead serially being connected to the power source of the clock buffer to protect the clock buffer from electro-magnetic interference (e.g., the power source); and a capacitor connected in parallel with the ferrite bead to reduce the distortion of the clock signal due to the ferrite bead.
In an embodiment of the present invention, the ferrite bead's impedance is at a maximum at the frequency of the electro-magnetic interference. For example, when the frequency of the electro-magnetic interference is 125 MHz, the ferrite bead's impedance is at a maximum at 125 MHz to protect the clock buffer from EMI.
In an embodiment of the present invention, the impedance of the capacitor is at a minimum at the frequency of the clock signal. For example, when the frequency of the clock signal is 25 MHz, the impedance of the capacitor is at a minimum at 25 MHz to reduce the distortion of a clock signal outputting by the clock buffer due to the ferrite bead.
The present invention provides an electro-magnetic interference protection method for a clock buffer. The method comprises the steps of: connecting a ferrite bead in serial with the power source of the clock buffer to protect the clock buffer from electro-magnetic interference (e.g., the power source); and connecting a capacitor in parallel with the ferrite bead to reduce the distortion of a clock signal outputting by the clock buffer due to the ferrite bead.
In an embodiment of the present invention, the ferrite bead's impedance is at a maximum at the frequency of the electro-magnetic interference. For example, when the frequency of the electro-magnetic interference is 125 MHz, the ferrite bead's impedance is at a maximum at 125 MHz to protect the clock buffer from EMI.
In an embodiment of the present invention, the impedance of the capacitor is at a minimum at the frequency of the clock signal. For example, when the frequency of the clock signal is 25 MHz, the impedance of the capacitor is at a minimum at 25 MHz to reduce the distortion of a clock signal outputting by the clock buffer due to the ferrite bead.
Accordingly, the present invention not only uses a ferrite bead to protect the clock buffer from electro-magnetic interference, but also connects a capacitor in parallel with the ferrite bead to reduce the distortion of a clock signal output by the clock buffer due to the ferrite bead, thereby making the communication devices work properly.
The above is a brief description of some deficiencies in the prior art and advantages of the present invention. Other features, advantages and embodiments of the invention will be apparent to those skilled in the art from the following description, accompanying drawings and appended claims.
The clock buffer 210 receives the clock signal clk-in and buffer-outputs the clock signal clk-out to drive the transceiver IC (not shown in the figures) in the communication device. Generally, the power source is the main source of the EMI. For example, in this embodiment, an EMI source has been found by experiment in the power source of the clock buffer 210.
A ferrite bead 220 is connected to the power source terminal Vcc to protect the clock buffer from EMI at 125 MHz.
To achieve the best result, the ferrite bead 20 having a maximum impedance at 125 MHz will be used. Referring to
MLB-201209-450B-N3). Because curve A has a maximum impedance at 125 MHz, the ferrite bead 220 corresponding to curve A can achieve the best result to protect the clock buffer 210 from EMI at 125 MHz.
Furthermore, to prevent the clock signal clk-out from distortion by the ferrite bead 220, the capacitor 230 is connected in parallel with the ferrite bead 220. To achieve the best result, the capacitor 230 having a minimum impedance at the frequency of the clock signal clk-out will be used. In this embodiment, the frequency of clk-out is 25 MHz. Hence, a 4.7 μF capacitor is used because its impedance is at a minimum at 25 MHz as showing in curve B of FIG.3. The resultant impedance characteristic curve of the ferrite bead 220 and the capacitor 230 is shown in curve C of FIG.3.
Accordingly, the present invention at least has the following advantages.
First, the clock buffer is protected from EMI.
Secondly, the communication device using the clock buffer can work properly.
Thirdly, the cost for protection from EMI is less because the present invention prevents the main EMI source (the power source) from interfering the clock buffer.
The above description provides a full and complete description of the preferred embodiments of the present invention. Various modifications, alternate construction, and equivalent may be made by those skilled in the art without changing the scope or spirit of the invention. Accordingly, the above description and illustrations should not be construed as limiting the scope of the invention which is defined by the following claims.
Chang, Chia-Cheng, Uang, Muh-Jin
Patent | Priority | Assignee | Title |
11023631, | Sep 25 2017 | Rezonent Corporation | Reduced-power dynamic data circuits with wide-band energy recovery |
11128281, | Sep 25 2017 | Rezonent Corporation | Reduced-power electronic circuits with wide-band energy recovery using non-interfering topologies |
11763055, | Sep 25 2017 | Rezonent Corporation | Reduced-power dynamic data circuits with wide-band energy recovery |
Patent | Priority | Assignee | Title |
5068631, | Aug 09 1990 | AT&T Bell Laboratories | Sub power plane to provide EMC filtering for VLSI devices |
6112118, | Mar 12 1996 | Implantable cardioverter defibrillator with slew rate limiting | |
6714092, | Nov 02 2000 | BEIJING XIAOMI MOBILE SOFTWARE CO , LTD | Supply noise filter for clock generator |
6781431, | Sep 19 2000 | Renesas Electronics Corporation | Clock generating circuit |
Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
Jul 01 2003 | CHANG, CHIA-CHENG | Wistron Corporation | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 013926 | /0832 | |
Jul 01 2003 | UANG, MUH-JIN | Wistron Corporation | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 013926 | /0832 | |
Sep 03 2003 | Wistron Corporation | (assignment on the face of the patent) | / |
Date | Maintenance Fee Events |
Sep 22 2008 | M1551: Payment of Maintenance Fee, 4th Year, Large Entity. |
Sep 24 2012 | M1552: Payment of Maintenance Fee, 8th Year, Large Entity. |
Jun 15 2016 | M1553: Payment of Maintenance Fee, 12th Year, Large Entity. |
Date | Maintenance Schedule |
Mar 22 2008 | 4 years fee payment window open |
Sep 22 2008 | 6 months grace period start (w surcharge) |
Mar 22 2009 | patent expiry (for year 4) |
Mar 22 2011 | 2 years to revive unintentionally abandoned end. (for year 4) |
Mar 22 2012 | 8 years fee payment window open |
Sep 22 2012 | 6 months grace period start (w surcharge) |
Mar 22 2013 | patent expiry (for year 8) |
Mar 22 2015 | 2 years to revive unintentionally abandoned end. (for year 8) |
Mar 22 2016 | 12 years fee payment window open |
Sep 22 2016 | 6 months grace period start (w surcharge) |
Mar 22 2017 | patent expiry (for year 12) |
Mar 22 2019 | 2 years to revive unintentionally abandoned end. (for year 12) |