decoding variable length codes having regular bit pattern prefixes enables faster decoding of variable length codes, especially in systems that provide bit or bit mask search capabilities. An embodiment of the present invention determines a code prefix type, and calculates a length of the code prefix. A first data structure may be provided to associate the maximal number of bits in a variable length code with the length of the code prefix, and to locate further decoding data in accordance with the prefix length and type. A bit stream may be read according to the maximal length obtained. An additional data structure may be provided to retrieve a decoded value and the actual length of a variable length code being decoded. This data structure may be indexed with the value of the bit combination read from the bit stream. In case the actual length of the variable length code is less than the maximal length, the excess bits may be returned to the bit stream.
|
1. In a system for decoding variable length codes in a bit stream, the variable length codes having prefixes of a regular bit pattern, a method comprising:
determining a bit pattern type of a code prefix, a bit pattern length, and a code prefix length;
obtaining, from a first data structure, a maximal code length and an offset into a second data structure according to the code prefix length and bit pattern type;
reading, from the bit stream, the number of bits immediately following the code prefix equal to the maximal code length; and
obtaining a decoded value and actual code length associated with the variable length code from an entry in the second data structure referenced by the offset.
19. A system for decoding variable length codes in a bit stream, the variable length codes having prefixes of a regular bit pattern, comprising:
logic to determine a bit pattern type of a code prefix, a bit pattern length, and a code prefix length;
logic to obtain, from a first data structure, a maximal code length and an offset into a second data structure according to the code prefix length and bit pattern type;
logic to read, from the bit stream, the number of bits immediately following the code prefix equal to the maximal code length; and
logic to obtain a decoded value and actual code length associated with the variable length code from an entry in the second data structure referenced by the offset.
10. An article comprising: a machine accessible medium having a plurality of machine readable instructions, wherein when the instructions are executed by a processor, the instructions provide for decoding variable length codes in a bit stream, the variable length codes having prefixes of a regular bit pattern, by
determining a bit pattern type of a code prefix, a bit pattern length, and a code prefix length;
obtaining, from a first data structure, a maximal code length and an offset into a second data structure according to the code prefix length and bit pattern type;
reading, from the bit stream, the number of bits immediately following the code prefix equal to the maximal code length; and
obtaining a decoded value and actual code length associated with the variable length code from an entry in the second data structure referenced by the offset.
2. The method of
3. The method of
4. The method of
5. The method of
6. The method of
7. The method of
8. The method of
9. The method of
11. The article of
12. The article of
13. The article of
14. The article of
15. The article of
16. The article of
17. The article of
18. The article of
20. The system of
21. The system of
22. The system of
23. The system of
24. The system of
25. The system of
26. The system of
27. The system of
|
A portion of the disclosure of this patent document contains material that is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent file or records, but otherwise reserves all copyright rights whatsoever.
1. Field
The present invention relates generally to decoding of variable-length prefix codes, e.g., Huffman codes, and, more specifically, to a new decoding scheme for codes whose prefixes are formed by a regular bit pattern.
2. Description
Entropy coding is a widely used data compression technique that many video and audio coding standards are based on. The theoretical basis of entropy coding states that a compression effect can be reached when the most frequently used data are coded with a fewer number of bits than the number of bits denoting the less frequently appearing data. This approach results in coded data streams composed of codes having different lengths.
There are a number of methods to form such variable length codes. One popular method uses a prefixed coding in which a code consists of a prefix that allows a decoding system to distinguish between different codes, and several significant bits representing a particular value (e.g., Huffman coding).
While most coding standards employ Huffman codes with prefixes composed of a series of ‘1’ or ‘0’ bits in their coding schemes, some standards (e.g., ISO/IEC 14496-2, Moving Pictures Experts Group (MPEG)-4 coding standard, Visual) allow for codes prefixed with a series of longer bit patterns. As a general rule, the number of bits that comprise a variable length code depends on the number of bits that comprise the prefix of the code.
Therefore, a need exists for the capability to provide high speed decoding of variable length codes prefixed with regular combinations of bits.
The features and advantages of the present invention will become apparent from the following detailed description of the present invention in which:
An embodiment of the present invention is a method of implementing a decoder for variable length codes that have prefixes composed of regular bit patterns. According to the disclosed method, the bit pattern length and type may be determined for a variable length code. The code may then be scanned for a selected bit pattern in order to estimate the code prefix length. The bit pattern type may be used to locate a table structure to be further indexed with the code prefix length. The table structure provides information on the maximal number of significant bits that follow the code prefix and correspond to the specific prefix length, along with information to locate a decoded value associated with a variable length code. If the bit pattern is one bit long, the bit immediately following the code prefix may be ignored. The number of bits (that is equal to the maximal number obtained) may be read from a bit stream. The value of the bit combination read may be used to index the table structure that provides a decoded value and the actual number of significant bits the decoded variable length code contains. If the actual number of bits is less than the maximal number, then the bit steam may be adjusted in a way that allows the excess bits to be accessed during the decoding of the next variable length code. The disclosed method requires less memory than direct lookup decoding methods and is efficient for systems that support bit scan operations. Additionally, performance of the method exhibits less memory access overhead as compared to prior art methods using multiple lookup tables.
Reference in the specification to “one embodiment” or “an embodiment” of the present invention means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrase “in one embodiment” appearing in various places throughout the specification are not necessarily all referring to the same embodiment.
Variable length codes (VLCs) may have identical prefixes. In this case, the codes constitute a prefix code group, but at the same time the number of significant bits that follow the prefix may differ. The maximal number of significant bits that is possible for a code in such a group may be referred to as the maximal bit number 12. The number of bits that follow the prefix for each VLC may be called the actual bit number.
If a VLC prefix is composed of 1-bit patterns (i.e., the only possible values for these 1-bit patterns are ‘0’ and ‘1’), the bit 14 that immediately follows the prefix has no meaning to decoding (because the bit has a value that is always the inverse of the prefix bit pattern) and may be ignored. This allows embodiments of the present invention to reduce lookup storage memory requirements.
If the bit pattern length is greater than 1 bit as shown in block 102, the prefix length may be determined 104 by scanning a bit stream for a bit mask equal to the determined bit pattern at block 106. This operation may be most efficient when implemented in systems that provide hardware support for bit mask scan operations. The retrieved prefix length serves as an index to the first table structure (e.g., the prefix length table) to obtain, at block 108, the maximal number of significant bits and an offset into the second table structure (e.g., the 2-bit code table) containing a decoded value.
If the bit pattern length is equal to 1 bit as shown in block 110, the prefix length may be determined 112 by scanning the bit stream for the inverse bit pattern at block 114. One efficient implementation of this operation uses bit scan hardware support (e.g., a 32-bit Intel Architecture (IA-32) BSR instruction). The retrieved prefix length serves as an index to obtain the maximal number of significant bits and offset at block 116 as described above for the multi-bit case. The bit that immediately follows the code prefix (the one the bit stream was scanned for) may be ignored at block 118.
Next, the obtained maximal number of bits that follow the prefix or the ignored bit may be read out of the bit stream at block 120. The second table structure (e.g., the 2-code table) entry pointed to by the obtained offset may be indexed, and the value of the bits in the entry read out at block 122. As a result, the actual number of bits the VLC being decoded contains and the VLC's associated (decoded) value may be obtained at block 124. If the actual number of bits appears to be less than the maximal number of bits read out, the bit stream may be adjusted at block 126 in a way that allows the excess bits to be processed upon the decoding of the next variable length code. In one embodiment, returning the excess bits may be accomplished by adjusting a bit stream pointer in a way that allows the bits of the bit stream to be further processed on decoding of a next variable length code.
For an exemplary embodiment of the present invention implemented in the C and Assembler programming languages, refer to Appendix A. Timing information for performance of the disclosed method is listed in Appendix B.
The techniques described herein are not limited to any particular hardware or software configuration; they may find applicability in any computing or processing environment. The techniques may be implemented in logic embodied in hardware, software, or firmware components, or a combination of the above. The techniques may be implemented in programs executing on programmable machines such as mobile or stationary computers, personal digital assistants, set top boxes, cellular telephones and pagers, and other electronic devices, that each include a processor, a storage medium readable by the processor (including volatile and non-volatile memory and/or storage elements), at least one input device, and one or more output devices. Program code is applied to the data entered using the input device to perform the functions described and to generate output information. The output information may be applied to one or more output devices. One of ordinary skill in the art may appreciate that the invention can be practiced with various computer system configurations, including multiprocessor systems, minicomputers, mainframe computers, and the like. The invention can also be practiced in distributed computing environments where tasks may be performed by remote processing devices that are linked through a communications network.
Each program may be implemented in a high level procedural or object oriented programming language to communicate with a processing system. However, programs may be implemented in assembly or machine language, if desired. In any case, the language may be compiled or interpreted.
Program instructions may be used to cause a general-purpose or special-purpose processing system that is programmed with the instructions to perform the operations described herein. Alternatively, the operations may be performed by specific hardware components that contain hardwired logic for performing the operations, or by any combination of programmed computer components and custom hardware components. The methods described herein may be provided as a computer program product that may include a machine readable medium having stored thereon instructions that may be used to program a processing system or other electronic device to perform the methods. The term “machine readable medium” used herein shall include any medium that is capable of storing or encoding a sequence of instructions for execution by the machine and that cause the machine to perform any one of the methods described herein. The term “machine readable medium” shall accordingly include, but not be limited to, solid-state memories, optical and magnetic disks, and a carrier wave that encodes a data signal. Furthermore, it is common in the art to speak of software, in one form or another (e.g., program, procedure, process, application, module, logic, and so on) as taking an action or causing a result. Such expressions are merely a shorthand way of stating the execution of the software by a processing system cause the processor to perform an action of produce a result.
While this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications of the illustrative embodiments, as well as other embodiments of the invention, which are apparent to persons skilled in the art to which the inventions pertains are deemed to lie within the spirit and scope of the invention.
Zheltov, Sergey N., Bratanov, Stanislav V.
Patent | Priority | Assignee | Title |
7205915, | Jul 15 2003 | INTEL, ZAKRYTOE AKTSIONERNOE OBSCHESTVO | Method of decoding variable length prefix codes |
7333037, | Feb 14 2006 | AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LIMITED | Method and system for improved lookup table (LUT) mechanism for Huffman decoding |
7348902, | Jul 29 2003 | INTEL, ZAKRYTOE AKTISIONERNOE OBSCHESTVO | Method for efficient variable length decoding |
7994948, | Sep 04 2008 | Electronics and Telecommunications Research Institute | Table generation method for decoding variable-length codes |
8339406, | Jan 30 2004 | Nvidia Corporation | Variable-length coding data transfer interface |
8427494, | Jan 30 2004 | Nvidia Corporation | Variable-length coding data transfer interface |
8477852, | Jun 20 2007 | Nvidia Corporation | Uniform video decoding and display |
8502709, | Sep 17 2007 | Nvidia Corporation | Decoding variable length codes in media applications |
8598990, | Jun 30 2008 | Symbol Technologies, LLC | Delimited read command for efficient data access from radio frequency identification (RFID) tags |
8725504, | Jun 06 2007 | Nvidia Corporation | Inverse quantization in audio decoding |
8849051, | Sep 17 2007 | Nvidia Corporation | Decoding variable length codes in JPEG applications |
8934539, | Dec 03 2007 | Nvidia Corporation | Vector processor acceleration for media quantization |
9307267, | Dec 11 2008 | Nvidia Corporation | Techniques for scalable dynamic data encoding and decoding |
Patent | Priority | Assignee | Title |
3717851, | |||
4475174, | Sep 08 1981 | Nippon Telegraph & Telephone Corporation | Decoding apparatus for codes represented by code tree |
5404139, | Oct 04 1991 | Sony United Kingdom Limited | Serial data decoder |
5559831, | Dec 23 1991 | Intel Corporation | Circuitry for decoding huffman codes |
5754128, | Jul 27 1995 | QUARTERHILL INC ; WI-LAN INC | Variable-length code encoding and segmenting apparatus having a byte alignment unit |
5973626, | Mar 17 1998 | Cornell Research Foundation, Inc | Byte-based prefix encoding |
5990812, | Oct 27 1997 | FUNAI ELECTRIC CO , LTD | Universally programmable variable length decoder |
6008745, | Feb 17 1998 | Oracle America, Inc | Variable length decoding using lookup tables |
6219457, | May 26 1998 | SAMSUNG ELECTRONICS CO , LTD | Method and system for decoding data encoded in a variable length code word |
6285789, | Dec 03 1997 | HANGER SOLUTIONS, LLC | Variable length code decoder for MPEG |
6518895, | Nov 16 2001 | RAMOT AT TEL AVIV UNIVERSITY LTD | Approximate prefix coding for data compression |
6563441, | May 10 2002 | Seiko Epson Corporation | Automatic generation of program logic to decode variable-length codes |
6771196, | Dec 14 1999 | AVAGO TECHNOLOGIES GENERAL IP SINGAPORE PTE LTD | Programmable variable-length decoder |
Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
Mar 12 2002 | Intel Corporation | (assignment on the face of the patent) | / | |||
Apr 18 2002 | ZHELTOV, SERGEY N | Intel Corporation | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 012895 | /0636 | |
Apr 18 2002 | BRATANOV, STANISLAV V | Intel Corporation | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 012895 | /0636 |
Date | Maintenance Fee Events |
Sep 13 2005 | ASPN: Payor Number Assigned. |
Nov 06 2008 | M1551: Payment of Maintenance Fee, 4th Year, Large Entity. |
Nov 07 2012 | M1552: Payment of Maintenance Fee, 8th Year, Large Entity. |
Dec 16 2016 | REM: Maintenance Fee Reminder Mailed. |
May 10 2017 | EXP: Patent Expired for Failure to Pay Maintenance Fees. |
Date | Maintenance Schedule |
May 10 2008 | 4 years fee payment window open |
Nov 10 2008 | 6 months grace period start (w surcharge) |
May 10 2009 | patent expiry (for year 4) |
May 10 2011 | 2 years to revive unintentionally abandoned end. (for year 4) |
May 10 2012 | 8 years fee payment window open |
Nov 10 2012 | 6 months grace period start (w surcharge) |
May 10 2013 | patent expiry (for year 8) |
May 10 2015 | 2 years to revive unintentionally abandoned end. (for year 8) |
May 10 2016 | 12 years fee payment window open |
Nov 10 2016 | 6 months grace period start (w surcharge) |
May 10 2017 | patent expiry (for year 12) |
May 10 2019 | 2 years to revive unintentionally abandoned end. (for year 12) |