A method for forming a floating gate electrode within a split gate field effect transistor device provides for isotropically processing a blanket isotropically processable material layer having a patterned mask layer formed thereover to form a patterned isotropically processed material layer which encroaches beneath the patterned mask layer. The patterned isotropically processed material layer may then be employed as a mask for forming a floating gate electrode from a blanket floating gate electrode material layer. The method provides for forming adjacent floating gate electrodes with less than minimally photolithographically resolvable separation.
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1. A method for forming a floating gate electrode comprising:
providing a semiconductor substrate;
forming upon the semiconductor substrate a tunneling dielectric layer;
forming upon the tunneling dielectric layer a blanket floating gate electrode material layer;
forming upon the blanket floating gate electrode material layer a thermal oxidation stop layer;
forming upon the thermal oxidation stop layer a blanket silicon layer;
forming upon the blanket silicon layer a patterned mask layer;
thermally oxidizing the blanket silicon layer to form a patterned silicon oxide layer which encroaches beneath the patterned mask layer; and
etching the blanket floating gate electrode material layer to form a floating gate electrode while employing the patterned silicon oxide layer as an etch mask layer.
8. A method for forming a split gate field effect transistor device comprising:
providing a semiconductor substrate;
forming upon the semiconductor substrate a tunneling dielectric layer;
forming upon the tunneling dielectric layer a blanket floating gate electrode material layer;
forming upon the blanket floating gate electrode material layer a thermal oxidation stop layer;
forming upon the thermal oxidation stop layer a blanket silicon layer;
forming upon the blanket silicon layer a patterned mask layer;
thermally oxidizing the blanket silicon layer to form a patterned silicon oxide layer which encroaches beneath the patterned mask layer;
etching the blanket floating gate electrode material layer to form a floating gate electrode while employing the patterned silicon oxide layer as an etch mask layer;
forming upon the floating gate electrode an intergate electrode dielectric layer; and
forming upon the intergate electrode a control gate electrode.
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1. Field of the Invention
The present invention relates generally to methods for forming split gate field effect transistor device arrays. More particularly, the present invention related to methods for forming split gate field effect transistor device arrays with enhanced areal density.
2. Description of the Related Art
A split gate field effect transistor device employs a floating gate electrode formed over and separated from a semiconductor substrate by a tunneling dielectric layer. The floating gate electrode defines a floating gate electrode channel within the semiconductor substrate. A split gate field effect transistor device further comprises a control gate electrode partially overlapping the control gate electrode and separated therefrom by an intergate electrode dielectric layer. The control gate electrode defines a control gate electrode channel adjoining the floating gate electrode channel within the semiconductor substrate. A split gate field effect transistor device finally comprises a pair of source/drain regions separated by the aggregate of the floating gate electrode channel and the control gate electrode channel.
To operate a split gate field effect transistor device, pre-determined voltages are applied to the control gate electrode, the source region, the drain region and the semiconductor substrate such as to allow for charge injection from the semiconductor substrate in the floating gate electrode, thus providing for nonvolatile charge storage. An additional pre-determined series of voltages may be employed for discharging and reading the stored charge.
While split gate field effect transistor devices provide a particularly common and desirable semiconductor device structure for non-volatile data storage and retrieval, split gate field effect transistor devices are nonetheless not entirely without problems.
In that regard, since split gate field effect transistor devices are fabricated employing plural overlapping gate electrode layers, split gate field effect transistor devices are often difficult to fabricate with enhanced areal density.
It is thus desirable to provide methods for fabricating split gate field effect transistor devices with enhanced areal density. It is towards the foregoing object that the present invention is directed.
Various methods have been disclosed within the semiconductor product fabrication art for forming, with desirable properties, split gate field effect transistor devices. Included but not limiting among the methods are those disclosed within Da et al., in U.S. Pat. No. 6,239,245 (a method for forming a split gate field effect transistor device with a reduced bit-line pitch).
Desirable are additional methods for forming split gate field effect transistor device arrays with enhanced areal density.
It is towards the foregoing object that the present invention is directed.
A first object of the invention is to provide a method for forming a split gate field effect transistor device array.
A second object of the invention is to provide a method in accord with the first object of the invention, wherein the split gate field effect transistor device array is formed with enhanced areal density.
In accord with the objects of the invention, the invention provides a method for forming a floating gate electrode for use within a split gate field effect transistor device.
The method first provides for a semiconductor substrate. The method also provides for forming a tunneling dielectric layer upon the semiconductor substrate. The method further provides for forming a blanket floating gate electrode material layer upon the tunneling dielectric layer. The method still further provides for forming a blanket isotropically processable material layer over the blanket floating gate electrode material layer. The method still further provides for forming a patterned mask layer upon the blanket isotropically processable material layer. The method then provides for isotropically processing the blanket isotropically processable material layer to form a patterned isotropically processed material layer which encroaches beneath the patterned mask layer. Finally, the method provides for etching the blanket floating gate electrode material layer to form a floating gate electrode while employing the patterned isotropically processed material layer as an etch mask layer.
The present invention provides a method for forming a split gate field effect transistor device with enhanced areal density.
The invention realizes the foregoing object by employing as an etch mask when forming a floating gate electrode from a blanket floating gate electrode material layer a patterned isotropically processed material layer which encroaches beneath a patterned mask layer which is employed as a mask when forming the patterned isotropically processed material layer from a blanket isotropically processable material layer. Due to the encroachment of the patterned isotropically processed material layer beneath the mask, a gap between adjacent patterned isotropically processed material layers may be less than a linewidth of the patterned mask layer, which may otherwise be formed at a minimum photolithographically resolvable linewidth. Thus, a pair of floating gate electrodes may be formed with closer spacing and a pair of split gate field effect transistor devices incorporating the pair of floating gate electrodes may be formed with enhanced areal density.
The objects, features and advantages of the invention are understood within the context of the Description of the Preferred Embodiment, as set forth below. The Description of the Preferred Embodiment is understood within the context of the accompanying drawings, which form a material part of this disclosure, wherein:
The present invention provides a method for forming a split gate field effect transistor device with enhanced areal density.
The invention realizes the foregoing object by employing as an etch mask when forming a floating gate electrode from a blanket floating gate electrode material layer a patterned isotropically processed material layer which encroaches beneath a patterned mask layer which is employed as a mask when forming the patterned isotropically processed material layer from a blanket isotropically processable material layer. Due to the encroachment of the patterned isotropically processed material layer beneath the mask, a gap between adjacent patterned isotropically processed material layers may be less than a linewidth of the patterned mask layer, which may otherwise be formed at a minimum photolithographically resolvable linewidth. Thus, a pair of floating gate electrodes may be formed with closer spacing and a pair of split gate field effect transistor devices incorporating the pair of floating gate electrodes may be formed with enhanced areal density.
The invention provides a method for diminishing an end-to-end spacing of the series of floating gate electrodes 14a, 14a′, 14a″ and 14a′″ or the series of floating gate electrodes 14b, 14b′, 14b″ and 14b′ ″. Thus, the array of split gate field effect transistor devices as illustrated within the schematic plan-view diagram of
Within the invention, the semiconductor substrate 10 may be of either dopant polarity, several dopant concentrations and various crystallographic orientations. Typically, the semiconductor substrate 10 is a (100) silicon semiconductor substrate. Typically, the series of isolation regions 12a, 12b and 12c is formed of a silicon oxide material formed and planarized into a series of isolation trenches to form the series of isolation regions 12a, 12b and 12c as a series of shallow trench isolation regions. Typically, the series of tunneling dielectric layers 24a, 24b, 24c and 24d is each formed to a thickness of from about 30 to about 70 angstroms, and formed of a silicon oxide material while employing a thermal oxidation method.
Within the invention, in particular, the blanket isotropically processable material layer 30 is formed of an isotropically processable material which is isotropically processed within the context of further description below. The blanket isotropic processing stop layer 28 serves as a stop layer with respect to the isotropic processing of the blanket isotropically processable material layer 30. Although the present invention does not preclude alternative materials combinations, each of the blanket floating gate electrode material layer 26 and the blanket isotropically processable material layer 30 is formed of a polysilicon material, although the blanket isotropically processable material layer 30 may also be formed of an amorphous silicon material. The blanket floating gate electrode material layer 26, but not the blanket isotropically processable material layer 30, is formed of a doped polysilicon material (having a dopant concentration of from about 1E18 to about 1E20 dopant atoms per cubic centimeter). In addition, each of the blanket isotropic processing stop layer 28 and the blanket mask layer 32 is formed of a silicon nitride material. Typically, the blanket floating gate electrode material layer 26 is formed to a thickness of from about 500 to about 3500 angstroms, the blanket isotropic processing stop layer is formed to a thickness of from about 300 to about 2000 angstroms, the blanket isotropically processable material layer 30 is formed to a thickness of from about 300 to about 1500 angstroms and the blanket mask layer 32 is formed to a thickness of from about 200 to about 2000 angstroms.
The series of patterned mask layers 32a, 32b and 32c when formed of a silicon nitride material may be stripped while employing an aqueous phosphoric acid etchant at elevated temperature. The series of patterned isotropically processable material layers 30a, 30b and 30c when formed of a polysilicon material may be stripped while employing a nitric, hydrofluoric and acetic acid mixture at elevated temperature.
The blanket isotropic processing stop layer 28 may be patterned while employing a selective reactive ion etch method.
Typically, the blanket floating gate electrode material layer 26 is patterned to form the series of once patterned floating gate electrode material layers 26a, 26b, 26c and 26d while employing an anisotropic plasma etch method employing a chlorine containing etchant gas composition.
The series of patterned isotropic processing stop layers 28a, 28b, 28c and 28d when formed of a silicon nitride material may be stripped while employing a phosphoric acid etchant at elevated temperature. The blanket planarizing stop layer 36 is typically formed of a silicon nitride material, formed to a thickness of from about 1000 to about 5000 angstroms, while employing an otherwise generally conventional deposition method.
To effect the foregoing result, the once patterned floating gate electrode material layer 26b may be etched within an isotropic etchant, such as a nitric, hydrofluoric and acetic acid mixture.
The pair of patterned planarized aperture fill layers 38a and 38b is typically formed of a silicon oxide material and planarized while employing a chemical mechanical polish (CMP) planarizing method.
The pair of patterned photoresist layers 40a and 40b may be formed employing methods and photoresist materials as are otherwise generally conventional in the semiconductor product fabrication art. The patterned planarizing stop layer 36b when formed of a silicon nitride material may be stripped while employing a phosphoric acid etchant at elevated temperature. The remaining layers as described above may then be sequentially etched while employing an etchant gas composition comprising a fluorine containing etchant gas, followed by a chlorine containing etchant gas, and finally followed by a fluorine containing etchant gas. Finally, the source region 41 may be formed employing ion implant methods and dopant materials as are otherwise conventional in the semiconductor product fabrication art.
The pair of patterned photoresist layers 40a and 40b may be stripped while employing methods as are conventional in the semiconductor product fabrication art. The pair of dielectric spacer layers 42a and 42b may be formed of a silicon oxide material. The conductor contact plug 44 is typically formed of a doped polysilicon material and the sacrificial oxide layer is typically formed incident to thermal oxidation of the doped polysilicon material from which is formed the conductor contact plug 44.
The pair of patterned planarizing stop layers 36a and 36c may be stripped employing an aqueous phosphoric acid etchant, at elevated temperature. The pair of floating gate electrodes 26b″″ and 26b′″″ may be formed incident to etching within a chlorine containing plasma. The pair of twice patterned tunneling dielectric layers 24b′″ and 24b″″ may be formed and the sacrificial oxide layer 46 may be stripped, while employing a fluorine containing plasma etch method.
Within the invention, the blanket intergate electrode dielectric layer 47 is typically formed of a composite of a silicon oxide and silicon nitride dielectric material, formed to a thickness of from about 20 to about 200 angstroms. In addition, the pair of floating gate electrodes 48a and 48b is typically formed of a doped polysilicon material, formed to a thickness of from about 1500 to about 3500 angstroms. Finally, the pair of drain regions 49a and 49b is typically formed incident to ion implanting a dopant of an appropriate polarity to provide the pair of drain regions of dopant concentration from about 1E16 to about 1E18 dopant atoms per cubic centimeter.
The preferred embodiment of the invention is illustrative of the invention rather than limiting of the invention. Revisions and modifications may be made to methods, materials, structures and dimensions in accord with the preferred embodiment of the invention while still providing an embodiment of the invention, further in accord with the accompanying claims.
Chu, Wen-Ting, Lin, Chrong-Jung, Hsieh, Chia-Ta
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