A chromeless phase lithography mask (30) that does not require photoresist to manufacture has a quartz substrate (32) is etched by using a plasma (38) containing one of a nitrogen augmented hydro-fluorocarbon oxygen mixture and a nitrogen augmented fluorocarbon oxygen mixture. Various hydro-fluorocarbons or fluorocarbons may be used. The nitrogen addition results in etched openings in the quartz substrate that have substantially vertical sidewalls in a uniform manner across the substrate. Surface roughness is minimized and edges of the openings are well-defined with minimal rounding. The etch rate is rendered controllable by reducing bias power without degrading a desired vertical sidewall profile.
|
1. A method for etching quartz during manufacture of a semiconductor mask comprising:
providing a quartz mask, the quartz mask comprising a quartz substrate, a cr layer overlying the quartz substrate, and a CrOxNy layer overlying the cr layer, the cr layer and CrOxNy layer forming a pattern by having openings formed therein for being transferred into the quartz substrate; and
etching the quartz mask in one of a nitrogen (N2), hydro-fluorocarbon (CxHyFz), and oxygen (O2) based plasma and a nitrogen, fluorocarbon (CxFz), and oxygen based plasma to transfer the pattern into the quartz substrate, where x, y and z are integers.
20. A method for manufacturing a semiconductor mask comprising:
providing a quartz mask, the quartz mask comprising a quartz substrate, a cr layer overlying the quartz substrate, and a CrOxNy layer overlying the cr layer, the cr layer and CrOxNy layer comprising a pattern for being transferred into the underlying quartz substrate, where x and y are integers; and
etching the quartz substrate in a plasma containing a range of nitrogen (N2) of substantially fifty percent or greater to transfer the pattern into the underlying quartz substrate, where the pattern forms openings in the quartz substrate having sidewall profiles on an order of substantially five degrees or less from a vertical reference.
2. The method of
3. The method of
4. The method of
6. The method of
7. The method of
8. The method of
10. The method of
11. The method of
12. The method of
13. The method of
14. The method of
15. The method of
16. The method of
17. The method of
18. The method of
19. The method of
|
This invention relates generally to integrated circuits, and more specifically, to the manufacture of masks used to manufacture semiconductors.
Phase shift mask (PSM) lithography is a known lithography technique for forming features on an integrated circuit. Photolithography requires sufficient resolution, contrast and depth of focus to form feature details having a minimum feature resolution. PSM requires etching of an underlying quartz mask plate and/or specifically deposited dielectric films to a depth that results in phase shifting of the light by a predetermined amount, typically one hundred eighty degrees.
To achieve lower cost, a technique known as chromeless phase lithography (CPL) has been proposed in the literature. CPL requires fewer electron beam lithography steps, thus reducing processing costs. Quartz etching for PSM manufacturing has typically been done using fluorocarbon oxygen plasma sources. The current processes that have been developed for PSM when applied to CPL have several shortcomings. These shortcomings include a fast quartz layer etch rate that makes it difficult to precisely control etching depth in the quartz layer. An incorrect depth in the quartz layer will result in incorrect shifting and ultimately reduce the feature contrast during subsequent semiconductor wafer fabrication. A second shortcoming with PSM based quartz etching applied to CPL includes non-uniformity of etching. In other words, across the mask etch depths and profiles vary. This variation also negatively affects feature contrast. A third shortcoming with PSM based quartz etching applied to CPL includes the fact that trench sidewalls become more non-vertical and slope angles vary more. A fourth shortcoming with PSM based quartz etching applied to CPL includes the fact that a chrome/chrome oxynitride stack is exposed and will be sputtered and therefore roughened. The sputtering also creates a second undesired effect. Due to sputtering, feature edges of a CPL mask become significantly rounded. Significant rounding results in a loss of lithography contrast.
The present invention is illustrated by way of example and not limitation in the accompanying figures, in which like references indicate similar elements.
Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve the understanding of the embodiments of the present invention.
Illustrated in
Illustrated in
Illustrated in
Adding nitrogen (N2) to the etching gas mixture of O2 and C2F6 and appropriately adjusting processing conditions considerably improves the quartz etching process for mask fabrication. One of the process conditions to be adjusted is the RF (radio frequency) bias power of the platen that CPL mask 30 is supported by in a plasma chamber. For example, a reduction of twenty-five percent may significantly improve the sidewall angle integrity and uniformity and decrease the etch rate. Other percentages of power reduction may be used for comparable favorable results. We have discovered that by using nitrogen in the plasma to etch the CPL mask 30, the plasma becomes less electro-negative and as a result more radial uniformity results. Further, the nitrogen is used to displace the hydro-fluorocarbon or hydrocarbon polymerization precursor. The decrease in polymer thickness on the sidewalls of the openings allows the sidewalls to be etched to a greater degree further resulting in a more vertical sidewall. For example, a use of approximately eighty percent nitrogen in the plasma 38 is known to have a beneficial effect of approximately four degrees more toward a vertical sidewall representing approximately a fifty percent improvement from a nitrogen-free plasma. By decreasing the power source the ion energies decrease resulting in a lower sputter etch yield and therefore a lower etch rate. Additionally, the mass of the major ion from nitrogen is less than the mass of the expected plasma components of the C2F6 plasma, such as CF3+. Therefore, there is reduced roughness on the surface of the CPL mask 30 because there is reduced sputtering. The etch rate is controlled by the balanced transport of etchants through a polymer layer (a reaction-diffusion layer) at the bottom of the openings, the thickness of which is controlled typically by ion energy. Sidewall profile control of each opening is effected by the deposition of a passivant on the sidewall that protects the sidewall from etchant penetration. An example of the passivant is CF2 and CF3 radicals that are produced by breakdown of the primary fluorocarbon or hydro-flurocarbon gases in the plasma. Nitrogen is special in this case as other polymer displacement candidates are either more massive than nitrogen or have a higher ionization potential rendering the population of the ion low and not a participant in the phenomena occurring in the opening.
Illustrated in
Due to the uniformity improvements of plasma 38 as discussed above, the depths D1, D2 and D3 are substantially the same value. Note also the improved sidewall angles of the openings 40, 42 and 44 as a result of the interaction discussed above. The sidewalls are substantially vertical from a lower surface of each opening to an upper surface of the chrome layer 34. Note also that the upper edges of each opening are sufficiently defined and not degraded as was the result in
Illustrated in
By now it should be appreciated that there has been provided a method for etching a quartz mask with improved resulting features. The use of nitrogen with either a hydro-fluorocarbon gas or a fluorocarbon gas and oxygen may be implemented without modifying conventional processing tools.
In the foregoing specification, the invention has been described with reference to specific embodiments. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. For example, various plasma chamber temperatures and pressures may be used to form the reactions described herein. Various etching depths may be implemented based upon the light wavelength and the widths of the openings may be scaled to any targeted process. Various types of power supplies may be used. The power supply sources may be implemented, in one form, by a power supply operating at predetermined frequencies, such as in the RF range, ultra-high frequency range, microwave range and others. Also, the power supplies may be inductively coupled or capacitively coupled to the housing containing the nitrogen-containing plasma. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present invention.
In one form there has been provided a method for etching quartz in the manufacture of a phase shift mask. A quartz mask is provided, the quartz mask including a quartz substrate, a Cr layer overlying the quartz substrate, and a CrOxNy layer overlying the Cr layer. The Cr layer and CrOxNy layer includes a pattern for being transferred into the underlying quartz substrate. The quartz mask is etched in one of a nitrogen (N2), hydro-fluorocarbon (CxHyFz), and oxygen (O2) based plasma and a nitrogen, fluorocarbon (CxFz), and oxygen based plasma to transfer the pattern into the underlying quartz substrate. The values x, y and z are integers. In one form the CxFz includes at least one of the following mixtures selected from the group C2F6, C3F6, C4F6, C-C4F8, C5F8, and the CxHyFz includes one of the following mixtures selected from the group consisting of CHF3, CH3F and CH2F2. The quartz mask is a phase shift mask. The etching of the pattern into the underlying quartz substrate includes etching the quartz substrate to a depth that phase shifts light of a prescribed wavelength λ by 180 degrees relative to non-etched portions of the quartz substrate. The depth is substantially equal to the quantity lambda divided by the quantity of two times (n−1), that is, λ/(2(n−1), where n is a reflective index of the quartz substrate at the wavelength λ. In one form the quartz mask is a resist-less quartz mask and a chromeless phase lithography mask. The plasma is a substantially uniform plasma in response to presence of the nitrogen. In one form, the percentage of N2 is on the order of greater than or equal to 50%, the percentage of CxHyFz or CxFz is on the order of less than between thirty-five to forty-five percent (35%–45%), and the percentage of O2 is on the order of less than between five to fifteen percent (5%–15%). The plasma is rendered more uniform with an increase in nitrogen and a corresponding decrease in CxHyFz. or CxFz. A corresponding plasma etch non-uniformity is less than 5%. The nitrogen contributes to the uniform plasma by reducing a concentration of negative ions over regions of the quartz mask. The etch rate for etching the quartz mask is controlled in response to a change in an effective bias power coupled to the plasma. Decreasing the effective bias power coupled to the plasma decreases an etch rate of the quartz substrate etching. The nitrogen portion of the plasma improves upon a sidewall profile of the patterned features by making the sidewall more vertical rather than angled or slanted. Therefore the nitrogen portion of the plasma improves upon a sidewall profile of the patterned features. The pattern that is transferred into the underlying quartz substrate includes transferring the pattern to a substantially uniform depth across the quartz substrate. The nitrogen portion of the plasma promotes more vertical patterned feature sidewalls by inhibiting excessive polymerization on the sidewalls of the patterned features. A resultant vertical profile of the patterned feature sidewalls is on the order of less than five degrees (5°) from vertical. Etching the Cr and CrOxNy layers occurs at an etch rate that is sufficient to retain an integrity of the pattern being transferred to the underlying quartz mask. Less faceting or removal of material occurs at corners of the Cr layer than with a plasma other than one of a nitrogen (N2), hydro-fluorocarbon (CxHyFz), and oxygen (O2) based plasma and a nitrogen (N2), fluorocarbon (CxFz), and oxygen (O2) based plasma. In another form there is herein provided a processing chamber for etching quartz in the manufacture of a phase shift mask having a housing and means for supporting a quartz mask in said housing. The quartz mask includes a quartz substrate, a Cr layer overlying the quartz substrate, and a CrOxNy layer overlying the Cr layer. The Cr layer and CrOxNy layer include a pattern for being transferred into the underlying quartz substrate. One of a nitrogen (N2), hydro-fluorocarbon (CxHyFz), and oxygen (O2) based plasma and a nitrogen (N2), fluorocarbon (CxFz), and oxygen (O2) based plasma are generated in the housing, wherein responsive to generating the plasma, the plasma transfers the pattern into the underlying quartz substrate, where x, y and z are integers.
Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential feature or element of any or all the claims. As used herein, the terms “comprises,” “comprising,” or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.
Rauf, Shahid, Ventzek, Peter L. G., Wu, Wei E.
Patent | Priority | Assignee | Title |
8535551, | Sep 28 2007 | Zeon Corporation | Plasma etching method |
8536061, | Aug 05 2010 | Kioxia Corporation | Semiconductor device manufacturing method |
Patent | Priority | Assignee | Title |
4957834, | Dec 22 1987 | Mitsubishi Denki Kabushiki Kaisha | Method for manufacturing photomask |
5691090, | Nov 21 1992 | Renesas Electronics Corporation | Phase shift mask and manufacturing method thereof and exposure method using phase shift mask |
6503664, | Feb 22 1994 | GLOBALFOUNDRIES Inc | Thin film materials for the preparation of attenuating phase shift masks |
6524755, | Sep 07 2000 | Gray Scale Technologies, Inc. | Phase-shift masks and methods of fabrication |
6703169, | Jul 23 2001 | Applied Materials, Inc. | Method of preparing optically imaged high performance photomasks |
EP668539, |
Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
Jan 27 2004 | WU, WEI E | Motorola, Inc | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 014942 | /0336 | |
Jan 28 2004 | Freescale Semiconductor, Inc. | (assignment on the face of the patent) | / | |||
Jan 28 2004 | VENTZEK, PETER L G | Motorola, Inc | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 014942 | /0336 | |
Jan 28 2004 | RAUF, SHAHID | Motorola, Inc | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 014942 | /0336 | |
Apr 04 2004 | Motorola, Inc | Freescale Semiconductor, Inc | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 015360 | /0718 | |
Dec 01 2006 | FREESCALE ACQUISITION CORPORATION | CITIBANK, N A AS COLLATERAL AGENT | SECURITY AGREEMENT | 018855 | /0129 | |
Dec 01 2006 | FREESCALE HOLDINGS BERMUDA III, LTD | CITIBANK, N A AS COLLATERAL AGENT | SECURITY AGREEMENT | 018855 | /0129 | |
Dec 01 2006 | FREESCALE ACQUISITION HOLDINGS CORP | CITIBANK, N A AS COLLATERAL AGENT | SECURITY AGREEMENT | 018855 | /0129 | |
Dec 01 2006 | Freescale Semiconductor, Inc | CITIBANK, N A AS COLLATERAL AGENT | SECURITY AGREEMENT | 018855 | /0129 | |
Apr 13 2010 | Freescale Semiconductor, Inc | CITIBANK, N A , AS COLLATERAL AGENT | SECURITY AGREEMENT | 024397 | /0001 | |
May 21 2013 | Freescale Semiconductor, Inc | CITIBANK, N A , AS NOTES COLLATERAL AGENT | SECURITY AGREEMENT | 030633 | /0424 | |
Nov 01 2013 | Freescale Semiconductor, Inc | CITIBANK, N A , AS NOTES COLLATERAL AGENT | SECURITY AGREEMENT | 031591 | /0266 | |
Dec 07 2015 | CITIBANK, N A | MORGAN STANLEY SENIOR FUNDING, INC | CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292 ASSIGNOR S HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS | 041703 | /0536 | |
Dec 07 2015 | CITIBANK, N A | MORGAN STANLEY SENIOR FUNDING, INC | CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517 ASSIGNOR S HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS | 053547 | /0421 | |
Dec 07 2015 | CITIBANK, N A | MORGAN STANLEY SENIOR FUNDING, INC | CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517 ASSIGNOR S HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS | 053547 | /0421 | |
Dec 07 2015 | CITIBANK, N A , AS COLLATERAL AGENT | Freescale Semiconductor, Inc | PATENT RELEASE | 037354 | /0225 | |
Dec 07 2015 | CITIBANK, N A | MORGAN STANLEY SENIOR FUNDING, INC | ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS | 037486 | /0517 | |
May 25 2016 | Freescale Semiconductor, Inc | MORGAN STANLEY SENIOR FUNDING, INC | SUPPLEMENT TO THE SECURITY AGREEMENT | 039138 | /0001 | |
Jun 22 2016 | MORGAN STANLEY SENIOR FUNDING, INC | NXP B V | CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001 ASSIGNOR S HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST | 052915 | /0001 | |
Jun 22 2016 | MORGAN STANLEY SENIOR FUNDING, INC | NXP B V | CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001 ASSIGNOR S HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST | 052915 | /0001 | |
Jun 22 2016 | MORGAN STANLEY SENIOR FUNDING, INC | NXP B V | RELEASE BY SECURED PARTY SEE DOCUMENT FOR DETAILS | 040928 | /0001 | |
Sep 12 2016 | MORGAN STANLEY SENIOR FUNDING, INC | NXP, B V , F K A FREESCALE SEMICONDUCTOR, INC | RELEASE BY SECURED PARTY SEE DOCUMENT FOR DETAILS | 040925 | /0001 | |
Sep 12 2016 | MORGAN STANLEY SENIOR FUNDING, INC | NXP, B V F K A FREESCALE SEMICONDUCTOR, INC | CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001 ASSIGNOR S HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST | 052917 | /0001 | |
Sep 12 2016 | MORGAN STANLEY SENIOR FUNDING, INC | NXP, B V F K A FREESCALE SEMICONDUCTOR, INC | CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001 ASSIGNOR S HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST | 052917 | /0001 | |
Nov 07 2016 | Freescale Semiconductor Inc | NXP USA, INC | CHANGE OF NAME SEE DOCUMENT FOR DETAILS | 040652 | /0180 | |
Nov 07 2016 | Freescale Semiconductor Inc | NXP USA, INC | CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE LISTED CHANGE OF NAME SHOULD BE MERGER AND CHANGE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0180 ASSIGNOR S HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME | 041354 | /0148 | |
Feb 17 2019 | MORGAN STANLEY SENIOR FUNDING, INC | SHENZHEN XINGUODU TECHNOLOGY CO , LTD | CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536 ASSIGNOR S HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS | 048734 | /0001 | |
Feb 17 2019 | MORGAN STANLEY SENIOR FUNDING, INC | SHENZHEN XINGUODU TECHNOLOGY CO , LTD | CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536 ASSIGNOR S HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS | 048734 | /0001 | |
Sep 03 2019 | MORGAN STANLEY SENIOR FUNDING, INC | NXP B V | RELEASE BY SECURED PARTY SEE DOCUMENT FOR DETAILS | 050744 | /0097 |
Date | Maintenance Fee Events |
Mar 26 2009 | M1551: Payment of Maintenance Fee, 4th Year, Large Entity. |
Mar 14 2013 | M1552: Payment of Maintenance Fee, 8th Year, Large Entity. |
Mar 20 2017 | M1553: Payment of Maintenance Fee, 12th Year, Large Entity. |
Date | Maintenance Schedule |
Nov 29 2008 | 4 years fee payment window open |
May 29 2009 | 6 months grace period start (w surcharge) |
Nov 29 2009 | patent expiry (for year 4) |
Nov 29 2011 | 2 years to revive unintentionally abandoned end. (for year 4) |
Nov 29 2012 | 8 years fee payment window open |
May 29 2013 | 6 months grace period start (w surcharge) |
Nov 29 2013 | patent expiry (for year 8) |
Nov 29 2015 | 2 years to revive unintentionally abandoned end. (for year 8) |
Nov 29 2016 | 12 years fee payment window open |
May 29 2017 | 6 months grace period start (w surcharge) |
Nov 29 2017 | patent expiry (for year 12) |
Nov 29 2019 | 2 years to revive unintentionally abandoned end. (for year 12) |