A method is described that involves driving a first current through a line and a termination resistance so that a logical value on the line changes from a first logical value to a second logical value. The method also includes holding the second logical value on the line by driving a second current through the line and the termination resistance where the second current less than the first current. An apparatus is described that includes a driver that drives a first current through a line and a termination resistance so that a logical value on the line changes from a first logical value to a second logical value. The driver holds the second logical value on the line by driving a second current through the line and the termination resistance. The second current is less than said first current.
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1. A method comprising:
a) driving a first current through a line and a termination resistance so that a logical value on said line changes from a first logical value to a second logical value, said first current sustained for a width of a first bit that is propagated on said line; and,
b) holding said second logical value on said line by driving a second current through said line and said termination resistance, said second current less than said first current, said second current sustained for a width of a second bit that is propagated on said line.
10. An apparatus to drive a logic level with multiple current strengths, comprising:
a plurality of drivers each having a enable/disable input, each said enable/disable input coupled to an output of a multiplxer, said mutliplexer having a first group of inputs and a second group of inputs, said first group of multiplexer inputs to provide an indication of a first number of said drivers to be enabled while driving a logic level with a first current strength, said second group of multiplexer inputs to provide an indication of a second number of said drivers to be enabled while driving a logic level with a second current strength.
18. An apparatus, comprising:
a ddr memory comprising address lines that are coupled to a plurality of drivers, each of said drivers having an enable/disable input, each said enable/disable input coupled to an output of a multiplexer, said mutliplexer having a first group of inputs and a second group of inputs, said first group of multiplexer inputs to provide an indication of a first number of said drivers to be enabled while driving a logic level with a first current strength, said second group of multiplexer inputs to provide an indication of a second number of said drivers to be enabled while driving a logic level with a second current strength.
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The present patent application is a Continuation of application Ser. No. 09/968,259, filed Sep. 28, 2001 now U.S. Pat. No. 6,633,178.
The field of invention relates to electrical circuitry in general; and, more specifically, to an apparatus and method for a power efficient line driver.
As semiconductor manufacturing techniques continue to advance, the speed of operation of semiconductor chips continues to increase. As such, the frequencies involved with the driver's 103 signaling of information to receiver 104 are continue to rise as circuitry 101, circuitry 102 and line 105 are implemented with more sophisticated semiconductor manufacturing technology. Complications arise as signaling frequencies increase, however.
Specifically, as signaling frequency increases, the likelihood increases that imperfections in the shape of the signaling waveform driven onto line 105 by driver 103 (e.g., as caused by back and forth “reflections” of the waveform between the receiver 104 and driver 103) will disturb the reliable reception of data at the receiver 104. An exemplary ideal signaling waveform 112 (i.e., without imperfections) that shows the transition from a logical low to a logical high between times T1 and T2 is shown in
Part of the design challenge in designing circuitry 101, circuitry 102 and line 105, therefore, is reducing the aforementioned likelihood. One technique is to “terminate” line 105 with a termination load 106. Termination load 106 is typically designed to have a resistance R that is proximate to the characteristic impedance of line 105. As R approaches the characteristic impedance of line 105, the strength of the reflections between receiver 104 and driver 103 are reduced which, in turn, corresponds to less disturbance in the shape of the signaling waveform 112.
A problem with traditional resistive termination load techniques (such as that described above), however, is the power dissipation that results. Specifically, when a current flows through a resistor, power is dissipated by the resistor according to the relationship P=I2R=V2/R (where I is the current that flows through the resistor, R is the resistance of the resistor, and V is the voltage across the resistor).
Thus, referring to the exemplary waveform 112 of
The present invention is illustrated by way of example, and not limitation, in the Figures of the accompanying drawings in which:
Recall from the discussion in the background that the power consumed by a resistive termination load may be a matter of concern as high power consumption may cause reliability problems as well as reduced battery life (for those applications that are battery operated). From the embodiment discussed with respect to
Note that, in light of the relationships expressed just above, as the voltage span of the waveform 112 increases (i.e., as VOH−VOLincreases), the power consumed by termination load 106 increases. To first order, this makes sense as termination loads that receive high voltage signals would be expected to dissipate larger amounts of power. Waveforms having relatively large voltage spans result from simplistically designed drivers.
Commonly, the largest voltage difference that exists within a semiconductor chip is the difference between the positive supply voltage (e.g., +3.3 v, +2.5 v, or +1.8 v according to present semiconductor technologies) and a ground reference (typically 0.0 v) or a negative supply voltage. A suitable example of a simplistically designed driver, is a driver that is designed to develop a waveform having only a pair of levels that reside at either of these two extremes (e.g., the positive supply voltage for the logic high level VOH and the ground reference for the logic low level VOL).
In a sense, this exemplary “simple” driver may be viewed as designed to “short” the line 105 to the positive supply voltage for a logic high level and designed to “short” the line 105 to the ground reference for a logic low level. As such, the termination load 106 dissipates a maximum amount of power as (VOH−Vterm)2/R is a maximum when VOH is equal to the supply voltage and (Vterm−VOL)2/R is a maximum when VOL is equal to the ground reference voltage. Regardless, for simplistic prior art drivers as described above (or for other simplistic drivers that differ in operation from that described above), this maximum power is dissipated over all time regardless of the logical information being transported on the line 105.
A more sophisticated driver, however, will generate a more complicated waveform aimed at reducing power dissipation while reliably delivering information. Examples of such waveforms are observed in
The large voltage swing from VOL to VOHassociated with the logical transition results from the use of a sufficiently large current to overcome the capacitive loading of the signal line 104 (and perhaps the input of the receiver 104). That is, in order to maintain high operational speeds, a sufficiently large current is used to implement a change in the value of the logical information on the signal line 105.
However as a logical value on the signal line 105 can be reliably maintained with less current than the amount of current needed to quickly change a logical value on the signal line 105, according to the design of a more sophisticated driver that generates the waveform 212a of
That is, a logical high level is maintained because, even though the waveform voltage 212a has been lowered, the lowered level of VOHE still remains above that at which high logical levels are recognized by the receiver 104 (e.g., Vterm). Power dissipation is reduced in the termination load 106 (as compared to the prior art approach observed in
Thus, waveform 212a of
In an embodiment, as alluded to just above, in order to develop the more sophisticated waveform 212a shown in
As such, the driver 103 may be viewed as being designed to drive either of a pair of output currents while it is providing a stable logical high voltage on line 105: a first, larger current of (VOH−Vterm)/R (between times T2a and T3a) and a second, smaller current of (VOHE−Vterm)/R (after time T4a). Other currents may exist during the transitory periods that exist between times T1a and T2a and between times T3a and T4a.
Note that, with respect to
However, the higher the output current Io supplied by the driver 103, the easier it becomes to rapidly change the voltage on line 105. In a sense, stronger currents are able to overcome the detrimental effects of the shunt capacitance (or series inductance). In order to generate a waveform such as (or similar to) the waveform 212a observed in
For example, the driver 103 may be designed to provide an output current of Io=(VOH−Vterm)/R or higher during a first transitory period that exists between times T1a and T2a in order to rapidly increase the line voltage as observed in
A “high” driver output current of Io=(VOH−Vterm)/R may then be maintained for an extended period of time (e.g., up to time T3a as seen in
Thus, the driver 103 may be viewed as designed to employ: 1) “high” output current over a first time period (e.g., from time T1a to time T3a) in order to change the line's logical value; and, 2) “low” output current after the first time period has expired (e.g., after time T3a and beyond) in order to maintain the line's logical level, at a reduced power, after it has been changed.
Using a higher current in order to implement a change in logical value allows the logical value to be changed quickly (which corresponds to high speed signaling) while using a lower current to maintain the logic level corresponds to reduced power dissipation in the termination load 106. Hence, power is conserved without reducing performance.
Note that the exemplary waveform of
Here, the increase of the logical low voltage level from VOL to VOLE has the effect of maintaining a logical low level while reducing power dissipation in the termination load 106. That is, a logical low level is maintained because, even though the waveform voltage 212b has been raised, the higher level of VOLE still remains below that at which low logical levels are recognized by the receiver 104 (e.g., Vterm). Power dissipation will also be reduced in the termination load 106 (as compared to the prior art approach observed in
In order to generate a waveform such as (or similar to) the waveform 212b observed in
As the waveform stabilizes (i.e., as the end of the first transitory period at time T2b is approached), the driver's output current approaches (or maintains) a value of Io=(Vterm−VOL)/R. A “high” driver output current of Io=(Vterm−VOL)/R may then be maintained for an extended period of time (e.g., up to time T3b as seen in
Note that the manner of controlling the time period over which “high” output current is employed (e.g., the amount of time between time T1a and T3a in
In other embodiments, the driver 103 may be designed to control this time period in a digital fashion (e.g., by triggering the “switchover” from high output current to low output current upon the edge of a clock cycle). An example of a driver that controls this time period in a digital fashion is described in more detail below. Regardless if an analog or digital approach is employed, the length of the “high” current time period should be sufficient to ensure that the logic value will be changed with sufficient rapidity for the particular application.
The second bit (a “0”) is formed with: 1) a “high” current time period that extends from T5c to T7c; and 2) a “low” current time period that extends from T7c to T9c. The third bit (a “1”) then begins to be formed with a “high” current time period that starts at time T9c. Note again that the receiver 104 will recognize the second bit after the waveform 112c falls below Vterm (which occurs just after time T5c) and until the waveform 112c rises above Vterm (which occurs just after time T9c).
If the logic value needs to change 302, the logic value is changed by driving 303 the line with high current. This may be viewed, for example, as corresponding to the high current region that extends from T5c to T7c (for the second bit of
Note that, if the logic value does not need to change 302, the logic value remains held by driving 301 the line with a low current. Although this aspect does not appear in the waveform 112c of
That is, the first bit maintains a voltage level of VOH throughout its width. Upon the expiration of the first bit (which is observed at the second rising edge of the clock signal 410), the second bit maintains a logical “1” value by being driven with a low current (such that the waveform 412 drops to a lower voltage level of VOHE). Upon the expiration of the second bit (which is observed at the third rising edge of the clock signal 410), the third bit is switched to a logical “0” value and, as such, is driven with a high current (such that the waveform 412 drops to a voltage level of VOL).
Again, as a high current is used for a complete bit width, the third bit maintains a voltage level of VOLthroughout its width. Upon the expiration of the third bit (which is observed at the fourth rising edge of the clock signal 410), the fourth bit is switched to a logical “0” value and, as such, is driven with a high current (such that the waveform 412 rises to a voltage level of VOH). Again, as a high current is used for a complete bit width, the fourth bit maintains a voltage level of VOH throughout its width.
The sequence described above corresponds to the methodology outlined in
Specifically, less sub-driver circuits are disabled if a large output current is desired at output 405 and more sub-driver circuits are disabled if a small output current is desired. For example, if a large output current is desired so that an output voltage of VOHis formed at output 405 (such as the period of time over which the first “1” is formed in the 1101 pattern observed in
Then, if a smaller output current is desired so that an output voltage of VOHEis formed at output 405 (such as the period of time over which the second “1” is formed in the 1101 pattern observed in
As seen in the embodiment of
As such, a sub-driver circuit may be completely disabled (such that it acts as a high impedance circuit element from the perspective of node 405) if both its PMOS driving transistor and its NMOS driving transistor are kept off. As the output of NAND gate 414 can be fixed at a logic “0” if its input signal line 4201 is a logic “I”; and as, the output of NOR gate 415 can be fixed at a logic “1” if its input signal line 4211 is a logic “0”, sub-driver circuit 401, can be disabled by applying a “1” at signal line 4201 and a “0” at signal line 4211. The rest of the sub-driver circuits 4012 through 401n can be similarly disabled.
If a sub-driver circuit is not disabled (e.g., if, for sub-driver circuit 4011, a “0” is applied at signal line 4201 and a “1” is applied at signal line 4211) it behaves as an inverting driver. Because the inverted data input 430 As such, a “0” applied at the inverted data input 430 will produce a “1” at the data output 405; and, a “1” applied at the inverted data input 430 will produce a “0” at the data output 405.
Together, the PMOS and NMOS enable/disable circuits 416 and 417 provide the appropriate enabling/disabling signals for the sub-driver circuits 4011 through 401n. That is, PMOS enable/disable circuit 416 provides a separate enabling/disabling signal for each of the PMOS transistors within then sub-driver circuits 4011 through 401n; and, the NMOS enable/disable circuit 417 provides a separate enabling/disabling signal for each of the NMOS transistors within the sub-driver circuits 4011 through 401n As such, the PMOS enable/disable circuit 416 may be said to provide a PMOS disable/enable bus 420 and the NMOS disable/enable circuit 417 may be said to provide an NMOS disable/enable bus 421.
The specific number of sub-driver circuits that are disabled at any time depends on the output words provided on the disable/enable buses 420, 421. The words may be envisioned in the embodiment of
Because a change in the value of the word presented on the buses 420, 421 corresponds to a change in the number of disabled drivers, the output current can be made to change (e.g., wherein a large output current provided with more enabled sub-driver circuits is reduced to a small output current by changing to less enabled sub-driver circuits) by changing the output word values provided by the disabling/enabling circuits 416 and 420. Using the PMOS disable/enable circuit 416 as a basis of discussion, in an embodiment, multiplexer 418 is configured to receive a “high current” output word (e.g., a word that enables a sufficient number of sub-drivers to form a VOHoutput voltage) from register 419 and a “low current” output word (e.g., a word that enables a sufficient number of sub-drivers to form a VOHEoutput voltage) from the PMOS disable/enable circuit 431 input.
As such, referring to
The approach of
For example,
As seen in
It is important to point out that the Vterm, VOH, VOHE, VOL and VOLE voltage levels (as well as the high and low currents and the termination resistance) may vary from embodiment to embodiment as those of ordinary skill will be able to determine appropriate values for their particular application. Specifically, as just one possible alternate approach, the VOH and VOL voltage levels may be different than the power and ground voltage supply rails (e.g., such as VOH being at a voltage level that is less than a positive supply voltage and VOL being at a voltage level that is greater than the ground supply voltage).
Note also that embodiments of the present description may be implemented not only within a semiconductor chip but also within machine readable media. For example, the designs discussed above may be stored upon and/or embedded within machine readable media associated with a design tool used for designing semiconductor devices. Examples include a netlist formatted in the VHSIC Hardware Description Language (VHDL) language, Verilog language or SPICE language. Some netlist examples include: a behavioral level netlist, a register transfer level (RTL) netlist, a gate level netlist and a transistor level netlist. Machine readable media also include media having layout information such as a GDS-II file. Furthermore, netlist files or other machine readable media for semiconductor chip design may be used in a simulation environment to perform the methods of the teachings described above.
Thus, it is also to be understood that embodiments of this invention may be used as or to support a software program executed upon some form of processing core (such as the CPU of a computer) or otherwise implemented or realized upon or within a machine readable medium. A machine readable medium includes any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, a machine readable medium includes read only memory (ROM); random access memory (RAM); magnetic disk storage media; optical storage media; flash memory devices; electrical, optical, acoustical or other form of propagated signals (e.g., carrier waves, infrared signals, digital signals, etc.); etc.
In the foregoing specification, the invention has been described with reference to specific exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.
Wilcox, Jeffrey R., Yuffe, Marcelo, Yosef, Noam
Patent | Priority | Assignee | Title |
7099416, | Feb 06 2002 | AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LIMITED | Single ended termination of clock for dual link DVI receiver |
7446571, | Nov 28 2001 | Rohm Co., Ltd. | Data transmission system and cable |
7724035, | Nov 28 2001 | Rohm Co., Ltd. | Data transmission system and cable |
8581756, | Sep 27 2012 | Cirrus Logic, Inc.; Cirrus Logic, INC | Signal-characteristic determined digital-to-analog converter (DAC) filter stage configuration |
Patent | Priority | Assignee | Title |
4584492, | Aug 06 1984 | Intel Corporation | Temperature and process stable MOS input buffer |
4857779, | Jun 24 1987 | U S PHILIPS CORP , 100 EAST 42ND STREET, NEW YORK, NY 10017, A CORP OF DE | Circuit arrangement for reducing noise |
4975598, | Dec 21 1988 | Intel Corporation | Temperature, voltage, and process compensated output driver |
5438278, | Sep 28 1993 | Lattice Semiconductor Corporation | High speed CMOS output buffer circuit minimizes propagation delay and crowbar current |
5528166, | Mar 14 1995 | Intel Corporation | Pulse controlled impedance compensated output buffer |
5546016, | Jul 03 1995 | Intel Corporation | MOS termination for low power signaling |
5760657, | Sep 30 1996 | Intel Corporation | Method and apparatus employing a process dependent impedance that compensates for manufacturing variations in a voltage controlled oscillator |
5896983, | Jul 17 1995 | Airtite Industries | Package dispenser for one or more condoms |
5898321, | Mar 24 1997 | Intel Corporation | Method and apparatus for slew rate and impedance compensating buffer circuits |
5926049, | Apr 11 1997 | Intel Corporation | Low power CMOS line driver with dynamic biasing |
6025792, | Jan 23 1998 | Intel Corporation | Analog compensation circuitry for integrated circuit input/output circuitry |
6031385, | Mar 24 1997 | Intel Corporation | Method and apparatus for testing compensated buffer circuits |
6072342, | Aug 11 1997 | Intel Corporation | Timed one-shot active termination device |
6075379, | Jan 22 1998 | Intel Corporation | Slew rate control circuit |
6084426, | Dec 24 1997 | Intel Corporation | Compensated input receiver with controlled switch-point |
6127840, | Mar 17 1998 | International Business Machines Corporation | Dynamic line termination clamping circuit |
6144218, | Jan 23 1998 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | High speed analog compensated input buffer |
6150862, | Oct 15 1998 | Intel Corporation | Stable delay buffer |
6166563, | Apr 26 1999 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Method and apparatus for dual mode output buffer impedance compensation |
6172546, | Dec 31 1997 | Intel Corporation | Method and apparatus to monitor a characteristic associated with an electronic device |
6175928, | Dec 31 1997 | Intel Corporation | Reducing timing variance of signals from an electronic device |
6184737, | Aug 29 1996 | SOCIONEXT INC | Signal transmission with reduced ringing of signals |
6198307, | Oct 26 1998 | Rambus Inc. | Output driver circuit with well-controlled output impedance |
6265893, | Sep 29 1998 | Intel Corporation | Signal line drivers |
6288563, | Dec 31 1998 | Intel Corporation | Slew rate control |
6289447, | Mar 24 1997 | Intel Corporation | Topology dependent compensation to improve performance of self-compensated components including processors based on physical relationship with other system components |
6298450, | Dec 31 1997 | Intel Corporation | Detecting states of signals |
6300798, | Oct 15 1999 | Intel Corporation | Method and apparatus for controlling compensated buffers |
6317369, | Nov 05 1999 | Renesas Electronics Corporation | Semiconductor device allowing higher speed data transmission to and from external unit |
6323647, | Sep 16 1999 | Agilent Technologies, Inc | Motor driven tuning and matching of RF coils in an NMR probe |
6347850, | Dec 23 1999 | Intel Corporation | Programmable buffer circuit |
6351136, | Dec 08 1999 | Intel Corporation | Passive voltage limiter |
6366129, | Nov 10 1998 | Intel Corporation | Method and apparatus for buffering an input-output node of an integrated circuit |
6366867, | Jun 22 1999 | Intel Corporation | Method and apparatus for providing controllable compensation factors to a compensated driver circuit which may be used to perform testing of the structural integrity of the compensated driver circuit |
6378010, | Aug 10 1999 | HEWLETT-PACKARD DEVELOPMENT COMPANY, L P | System and method for processing compressed audio data |
6380758, | Sep 29 2000 | Intel Corporation | Impedance control for wide range loaded signals using distributed methodology |
6396305, | Mar 29 2001 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Digital leakage compensation circuit |
6445316, | Sep 29 2000 | Intel Corporation | Universal impedance control for wide range loaded signals |
6456016, | Jul 30 2001 | Intel Corporation | Compensating organic light emitting device displays |
6459737, | May 07 1999 | Intel Corporation | Method and apparatus for avoiding redundant data retrieval during video decoding |
6480438, | Jun 12 2001 | OVONYX MEMORY TECHNOLOGY, LLC | Providing equal cell programming conditions across a large and high density array of phase-change memory cells |
6483354, | Aug 24 2001 | AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LIMITED | PCI-X driver control |
6493394, | Oct 09 1996 | Fujitsu Limited | SIGNAL TRANSMISSION SYSTEM FOR TRANSMITTING SIGNALS BETWEEN LSI CHIPS, RECEIVER CIRCUIT FOR USE IN THE SIGNAL TRANSMISSION SYSTEM, AND SEMICONDUCTOR MEMORY DEVICE APPLYING THE SIGNAL TRANSMISSION SYSTEM |
6509780, | Sep 10 2001 | Intel Corp | Circuit compensation technique |
6525683, | Sep 19 2001 | Intel Corporation | Nonlinearly converting a signal to compensate for non-uniformities and degradations in a display |
6693450, | Sep 29 2000 | Intel Corporation | Dynamic swing voltage adjustment |
DE19942688, |
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