A sequence state matrix has a plurality of time slots for storing a plurality of memory device signals. The memory device signals are loaded into the matrix by a sequencer load unit, which loads the memory device signals at locations in the matrix corresponding to the times that the signals will be coupled to a memory device. The sequencer load unit loads the signals into the matrix at a rate corresponding to a frequency of a system clock signal controlling the operation of the electronic system. A first in, first out (“FIFO”) buffer receives the memory device signals from the sequence state matrix at a rate corresponding to the frequency of the system clock signal. A command selector transfers the memory device signals from the FIFO buffer to the memory device at a rate corresponding to the frequency of a memory clock signal controlling the operation of the memory device.

PTO Wrapper PDF
Dossier Espace Google
Patent
   6983354
Priority
May 24 2002
Filed
May 24 2002
Issued
Jan 03 2006
Expiry
Jan 17 2023
Extension
238 days
Inventors
Jeddeloh, …
Assg.orig
Micron Tec…
Assg.curr
U S BANK …
Entity
Large
Referenced by
19
References
32
Maint.:
all paid
TECHNICAL FIELD
BACKGROUND OF THE IN…
SUMMARY OF THE INVEN…
BRIEF DESCRIPTION OF…
DETAILED DESCRIPTION…
13. A system for coupling memory device signals from an electronic system synchronized to a system clock signal to a memory device synchronized to a memory clock signal, the system comprising:
a sequence state matrix having a plurality of time slots for each of a plurality of the memory device signals, the sequence state matrix storing the memory device signals at respective locations corresponding to the times that the memory device signals will be coupled to the memory device;
a first in, first out (“FIFO”) buffer coupled to the sequence state matrix to receive the memory device signals from the matrix in the order that the memory device signals are stored in the sequence state matrix, the memory device signals being transferred from the sequence state matrix to the FIFO buffer responsive to a first clock signal;
a command selector coupled to the FIFO buffer to receive the memory device signals from the FIFO buffer and transfer the memory device signals to the memory device responsive to a second clock signal; and
a phasing unit coupled to the FIFO buffer and to the command selector, the phasing unit generating the first and second clock signals at respective frequencies in which the ratio between the frequency of the first clock signal and the frequency of the second clock signal corresponds to ratio between the frequency of the system clock signal and the frequency of the memory clock signal.
7. A system for coupling memory device signals, comprising:
a sequence state matrix having a plurality of time slots for each of a plurality of the memory device signals;
a sequencer load unit coupled to receive the memory device signals, the sequencer load unit coupled to the sequence state matrix to load the memory device signals into the sequence state matrix at locations in the matrix corresponding to the times that the memory device signals will be coupled to the memory device, the sequencer load unit loading the memory device signals into the sequence state matrix at a rate corresponding to a frequency of a system clock signal;
a first in, first out (“FIFO”) buffer coupled to the sequence state matrix to receive the memory device signals from the matrix at respective times corresponding to the locations into which the memory device signals were loaded, the FIFO buffer receiving the memory device signals from the matrix at a rate corresponding to the frequency of the system clock signal; and
a combinatorial unit coupled to the sequence state matrix and the sequencer load unit, the combinatorial unit determining the location of memory device signals stored in the sequence state matrix and coupling corresponding information to the sequencer load unit, the sequencer load unit determining the locations in the sequence state matrix in which to store the memory device signals based at least in part on the information received from the combinatorial unit.
1. A system for coupling memory device signals from an electronic system to a memory device, comprising:
a sequence state matrix having a plurality of time slots for each of a plurality of the memory device signals;
a sequencer load unit coupled to receive the memory device signals from the electronic system, the sequencer load unit coupled to the sequence state matrix to load the memory device signals into the sequence state matrix at locations in the matrix corresponding to the times that the memory device signals will be coupled to the memory device, the sequencer load unit loading the memory device signals into the sequence state matrix at a rate corresponding to a frequency of a system clock signal controlling the operation of the electronic system;
a first in, first out (“FIFO”) buffer coupled to the sequence state matrix to receive the memory device signals from the matrix at respective times corresponding to the locations into which the memory device signals were loaded, the FIFO buffer receiving the memory device signals from the matrix at a rate corresponding to the frequency of the system clock signal; and
a command selector coupled to the FIFO buffer to receive the memory device signals from the FIFO buffer and transfer the memory device signals to the memory device, the command selector transferring the memory device signals to the memory device at a rate corresponding to the frequency of a memory clock signal controlling the operation of the memory device.
31. A computer system, comprising:
a processing unit operable to perform computing functions;
a system controller coupled to the processing unit, the system controller operating in synchronism with a system clock signal;
at least one input device coupled to the processing unit through the system controller;
at least one output device coupled to the processing unit through the system controller;
at least one data storage devices coupled to the processing unit through the system controller;
a memory device operating in synchronism with a memory clock signal; and
a memory controller included in the system controller, the memory controller coupling memory device signals from the processing unit to the memory device, the memory controller comprising:
a sequence state matrix having a plurality of time slots for each of a plurality of the memory device signals received from the processing unit, the sequence state matrix storing the memory device signals at respective locations corresponding to the times that the memory device signals will be coupled to the memory device;
a first in, first out (“FIFO”) buffer coupled to the sequence state matrix to receive the memory device signals from the matrix in the order that the memory device signals are stored in the sequence state matrix, the memory device signals being transferred from the sequence state matrix to the FIFO buffer responsive to a first clock signal;
a command selector coupled to the FIFO buffer to receive the memory device signals from the FIFO buffer and transfer the memory device signals to the memory device responsive to a second clock signal; and
a phasing unit coupled to the FIFO buffer and to the command selector, the phasing unit generating the first and second clock signals at respective frequencies in which the ratio between the frequency of the first clock signal and the frequency of the second clock signal corresponds to ratio between the frequency of the system clock signal and the frequency of the memory clock signal.
17. A computer system, comprising:
a processing unit operable to perform computing functions;
a system controller coupled to the processing unit, the system controller operating in synchronism with a system clock signal;
at least one input device coupled to the processing unit through the system controller;
at least one output device coupled to the processing unit through the system controller;
at least one data storage devices coupled to the processing unit through the system controller;
a memory device operating in synchronism with a memory clock signal; and
a memory controller included in the system controller, the memory controller coupling memory device signals from the processing unit to the memory device, the memory controller comprising:
a sequence state matrix having a plurality of time slots for each of a plurality of the memory device signals;
a sequencer load unit coupled to receive the memory device signals from the processing unit, the sequencer load unit coupled to the sequence state matrix to load the memory device signals into the sequence state matrix at locations in the matrix corresponding to the times that the memory device signals will be coupled to the memory device; the sequencer load unit loading the memory device signals into the sequence state matrix at a rate corresponding to a frequency of the system clock signal;
a first in, first out (“FIFO”) buffer coupled to the sequence state matrix to receive the memory device signals from the matrix at respective times corresponding to the locations into which the memory device signals were loaded, the FIFO buffer receiving the memory device signals from the matrix at a rate corresponding to the frequency of the system clock signal; and
a command selector coupled to the FIFO buffer to receive the memory device signals from the FIFO buffer and transfer the memory device signals to the memory device, the command selector transferring the memory device signals to the memory device at a rate corresponding to the frequency of the memory clock signal.
24. A computer system, comprising:
a processing unit operable to perform computing functions;
a system controller coupled to the processing unit, the system controller operating in synchronism with a system clock signal;
at least one input device coupled to the processing unit through the system controller;
at least one output device coupled to the processing unit through the system controller;
at least one data storage devices coupled to the processing unit through the system controller;
a memory device operating in synchronism with a memory clock signal; and
a memory controller included in the system controller, the memory controller coupling memory device signals from the processing unit to the memory device, the memory controller comprising:
a sequence state matrix having a plurality of time slots for each of a plurality of the memory device signals;
a sequencer load unit coupled to receive the memory device signals from the processing unit, the sequencer load unit coupled to the sequence state matrix to load the memory device signals into the sequence state matrix at locations in the matrix corresponding to the times that the memory device signals will be coupled to the memory device, the sequencer load unit loading the memory device signals into the sequence state matrix at a rate corresponding to a frequency of the system clock signal;
a first in, first out (“FIFO”) buffer coupled to the sequence state matrix to receive the memory device signals from the matrix at respective times corresponding to the locations into which the memory device signals were loaded, the FIFO buffer receiving the memory device signals from the matrix at a rate corresponding to the frequency of the system clock signal, the memory device signals being transferred from the FWO buffer to the memory device at a rate corresponding to the frequency of the memory clock signal; and
a combinatorial unit coupled to the sequence state matrix and the sequencer load unit, the combinatorial unit determining the location of memory device signals stored in the sequence state matrix and coupling corresponding information to the sequencer load unit, the sequencer load unit determining the locations in the sequence state matrix in which to store the memory device signals based at least in part on the information received from the combinatorial unit.
2. The system of claim 1 wherein the memory device signals comprise command signals.
3. The system of claim 2 wherein the memory device signals further comprise address signals.
4. The system of claim 3 wherein the memory device signals further comprise data signals.
5. The system of claim 1, further comprising a combinatorial unit coupled to the sequence state matrix and the sequencer load unit, the combinatorial unit determining the location of memory device signals stored in the sequence state matrix and coupling corresponding information to the sequencer load unit, the sequencer load unit determining the locations in the sequence state matrix in which to store the memory device signals based at least in part on the information received from the combinatorial unit.
6. The system of claim 5, further comprising a phasing unit coupled to the FIFO buffer and the command selector, the phasing unit generating a first clock signal controlling the transfer of the memory device signals from the sequencer state matrix to the FIFO buffer and a second clock signal controlling the transfer of the memory device signals from the FIFO buffer to the memory device, the ratio between the frequency of the first clock signal and the frequency of the second clock signal corresponding to the ratio between the frequency of the system clock signal and the frequency of the memory clock signal.
8. The system of claim 7 wherein the memory device signals comprise command signals.
9. The system of claim 8 wherein the memory device signals further comprise address signals.
10. The system of claim 9 wherein the memory device signals further comprise data signals.
11. The system of claim 7, further comprising a command selector coupled to the FIFO buffer to transfer the memory device signals from the FIFO buffer.
12. The system of claim 11, further comprising a phasing unit coupled to the FIFO buffer and the command selector, the phasing unit generating a first clock signal controlling the transfer of the memory device signals from the sequencer state matrix to the FIFO buffer and a second clock signal controlling the transfer of the memory device signals from the FIFO buffer to the memory device, the ratio between the frequency of the first clock signal and the frequency of the second clock signal corresponding to the ratio between the frequency of the system clock signal and the frequency of the memory clock signal.
14. The system of claim 13 wherein the memory device signals comprise command signals.
15. The system of claim 14 wherein the memory device signals further comprise address signals.
16. The system of claim 15 wherein the memory device signals further comprise data signals.
18. The computer system of claim 17 wherein the memory device comprises a synchronous dynamic random access memory.
19. The computer system of claim 17 wherein the memory device signals comprise command signals.
20. The computer system of claim 19 wherein the memory device signals further comprise address signals.
21. The computer system of claim 20 wherein the memory device signals further comprise data signals.
22. The computer system of claim 17, further comprising a combinatorial unit coupled to the sequence state matrix and the sequencer load unit, the combinatorial unit determining the location of memory device signals stored in the sequence state matrix and coupling corresponding information to the sequencer load unit, the sequencer load unit determining the locations in the sequence state matrix in which to store the memory device signals based at least in part on the information received from the combinatorial unit.
23. The computer system of claim 22, further comprising a phasing unit coupled to the FIFO buffer and the command selector, the phasing unit generating a first clock signal controlling the transfer of the memory device signals from the sequencer state matrix to the FIFO buffer and a second clock signal controlling the transfer of the memory device signals from the FIFO buffer to the memory device, the ratio between the frequency of the first clock signal and the frequency of the second clock signal corresponding to the ratio between the frequency of the system clock signal and the frequency of the memory clock signal.
25. The computer system of claim 24 wherein the memory device comprises a synchronous dynamic random access memory.
26. The computer system of claim 24 wherein the memory device signals comprise command signals.
27. The computer system of claim 26 wherein the memory device signals further comprise address signals.
28. The computer system of claim 27 wherein the memory device signals further comprise data signals.
29. The computer system of claim 24, further comprising a command selector coupled to the FIFO buffer to transfer the memory device signals from the FIFO buffer to the memory device.
30. The computer system of claim 29, further comprising a phasing unit coupled to the FIFO buffer and the command selector, the phasing unit generating a first clock signal controlling the transfer of the memory device signals from the sequencer state matrix to the FIFO buffer and a second clock signal controlling the transfer of the memory device signals from the FIFO buffer to the memory device, the ratio between the frequency of the first clock signal and the frequency of the second clock signal corresponding to the ratio between the frequency of the system clock signal and the frequency of the memory clock signal.
32. The computer system of claim 31 wherein the memory device comprises a synchronous dynamic random access memory.
33. The computer system of claim 31 wherein the memory device signals comprise command signals.
34. The computer system of claim 33 wherein the memory device signals further comprise address signals.
35. The computer system of claim 34 wherein the memory device signals further comprise data signals.
TECHNICAL FIELD

This invention relates to memory devices, and more particularly to a system and method for interfacing a memory device to a system in which the system and memory device may operate at different clock speeds.

BACKGROUND OF THE INVENTION

Memory devices, such as dynamic random access memories (“DRAMs”) may operate either asynchronously or synchronously. When operating synchronously, the operation of the memory device is controlled by a clock signal, and the speed at which the memory device operates is thus determined by the frequency of the clock signal. The memory device may be interfaced with an electronic device, such as a computer system, that is also operated synchronously at a frequency determined by its own clock signal, known as the system clock signal. Generally, the frequency of the system clock signal is the same as the frequency of the memory clock signal. However, it is often possible for a memory device to operate at a higher speed than the speed corresponding to the frequency of the system clock signal. In such case, the memory clock signal may have a higher frequency than the frequency of the system clock signal.

If a memory device synchronized to a relatively high speed memory clock signal could be interfaced with a system synchronized to a relatively slow speed system clock signal, it might be possible to increase the speed at which data could be written to or read from the memory device. However, it can be difficult to interface a memory device operating according to a memory clock signal having one frequency with an electronic system operating according to a system clock having a different, usually slower, frequency. This difficulty stems from the fact that the different clock frequencies inherently prevents the memory device from operating in synchronism with the electronic system.

There is therefore a need for a system and method for allowing a memory device operating in synchronism with a memory clock signal to interface with an electronic system operating in synchronism with a system clock signal having a frequency that may be different from the frequency of the memory clock signal.

SUMMARY OF THE INVENTION

A sequencer is used to transfer memory device signals, such as command, addresses and data signals, from an electronic system operating at a system clock speed to a memory device operating at a higher memory clock speed. The sequencer, includes a sequencer state matrix into which the memory device signals are loaded in the order in which they will be applied to the memory device. The memory device signals are loaded into the sequence state matrix at the slower system clock speed. The memory device signals are then transferred from the sequence state matrix to a first in, first out buffer at the system clock speed, and are then transferred from the first in, first out buffer to the memory device at the higher memory clock speed.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a computer system according to one embodiment of the present invention.

FIG. 2 is a block diagram of a sequencer used in the computer system of FIG. 1.

FIGS. 3A–3C are matrix diagrams showing the operation of the sequencer of FIG. 2.
DETAILED DESCRIPTION OF THE INVENTION

A computer system 100 according to one embodiment of the invention is shown in FIG. 1. The computer system 100 includes a processor 104 for performing various computing functions, such as executing specific software to perform specific calculations or tasks. The processor 104 includes a processor bus 106 that normally includes an address bus, a control bus, and a data bus. In addition, the computer system 100 includes one or more input devices 108, such as a keyboard or a mouse, coupled to the processor 104 through a system controller 110 to allow an operator to interface with the computer system 100. Typically, the computer system 100 also includes one or more output devices 114 coupled to the processor 104 through the system controller 110, such output devices typically being a printer or a video terminal. One or more data storage devices 120 are also typically coupled to the processor 104 through the system controller 110 to allow the processor 104 to store data or retrieve data from internal or external storage media (not shown). Examples of typical storage devices 120 include hard and floppy disks, tape cassettes, and compact disk read-only memories (CD-ROMs). The processor 104 is also typically coupled to cache memory 124, which is usually static random access memory (“SRAM”).

The computer system 100 includes a system clock 126 that is coupled to the system controller 110 and may be coupled to other components in the computer system 100. The system clock 126 generates a system clock signal to which the operation of system controller 110 is synchronized.

The system controller 110 also includes a memory controller 130 for controlling access to a system memory 140, which may be a synchronous dynamic random access memory (“SDRAM”). The operation of the memory controller 130 is also synchronized to the system clock signal generated by the system clock 126. The memory controller 130 allows the processor 104 to write data to and read data from the system memory 140, and may also allow other devices (not shown) to write data to and read data from the system memory 140 in a direct memory operation, as is well known in the art. The memory controller 130 is coupled to the system memory 140 through a control bus 142, an address bus 144 and a data bus 146. The operation of the system memory 140 is synchronized to a memory clock signal generated by a memory clock 148. The frequency of the memory clock signal is preferably greater than the frequency of the system clock signal generated by the system clock 126 so that data can be written to and read from the system memory 140 at a faster rate. Significantly, the memory controller 130 includes a sequencer 150 that allows the system memory 140 operating at a speed controlled by the memory clock signal to interface with other components of the computer system 100 operating at a slower speed corresponding to the frequency of the system clock signal.

One embodiment of the sequencer 150 is shown in FIG. 2. The sequencer includes a large number of input registers 160 into which control, address and write data signals are clocked responsive to rising, falling or both rising and falling edge of the clock signal from the system clock 126 (FIG. 1). Also included are a large number of output registers 164 from which read data signals are clocked responsive to rising, falling or both rising and falling edge of the clock signal from the system clock 126. In general, an input register 160 is provided for each control signal and address bit coupled to the system memory 140, and an input register 160 and an output register 164 is provided for each data bit coupled to and from the system memory 140.

The memory device signals coupled through the input registers 160 are applied to a command parser 170, which analyzes the memory device signals and determines individual commands corresponding to combinations of the memory device command signals. The command parser 170 applies signals indicative of the individual commands to a sequencer load logic unit 176, which has an output bus coupled to a sequencer state matrix 180. The sequencer state matrix is essentially a set of first in, first out buffers operating in synchronism with each other, with a separate buffer being provided for each memory device signal. The load logic unit 176 examines the individual commands to determine the time slot in which each of the commands can be applied to the system memory 140. The commands are then loaded into the sequencer state matrix 180 at locations corresponding to the respective time slots. The time slots selected for being loaded with the commands thus correspond to the times at which the commands can be applied to the system memory 140 at the frequency of the memory clock signal generated by the memory clock 148.

It is important that the time slots at which the commands are applied to the system memory 140 not conflict with each other. For this reason, a combinatorial unit 184 examines the commands that have been loaded into the sequencer state matrix 180. The combinatorial unit 184 then provides information signals to the sequencer load logic unit 176 via path 188 indicative of the nature and location of all commands that have already been loaded into the sequencer state matrix 180. Using this information, the sequencer load logic unit 176 can determine locations in the matrix 180 where additional command can be loaded into the matrix 180 without causing a conflict when the commands are subsequently applied to the system memory 140.

The command parser 170, the sequencer load logic unit 176, the sequencer state matrix 180 and the combinatorial unit 184 are preferably respective logic circuits, the design of which will be apparent to one skilled in the art. The operation of all of these units is synchronized to the system clock signal generated by the system clock system clock 126, although, as previously mentioned, the time slots in the matrix 180 into which the commands and addresses are loaded correspond to the times at which the commands can be applied to the system memory 140 at the frequency of the memory clock signal generated by the memory clock 148.

Once the commands and addresses have been loaded into the sequencer state matrix 180, they are transferred to a first in, first out (FIFO) buffer 190 at a rate corresponding to the frequency of the system clock signal. However, the system clock signal from the system clock 126 is not used to load the commands and addresses into the buffer 190. Instead, the commands and addressed are loaded into the FIFO buffer 190 responsive to a first clock signal from a phasing unit 194. A second clock signal is generated by the phasing unit 194, which is applied to a command selector 200. The command selector 200 transfers the commands and addresses from the FIFO buffer in the same order that the buffer 190 was loaded at a rate determined by the second clock signal. The second clock signal has a frequency that corresponds to the memory clock signal from the memory clock 148. Thus, the frequency ratio between the first and second clock signals from the phasing unit 194 corresponds to the frequency ratio between the system clock signal and the memory clock signal. The phasing unit 194 thus compensates for the difference between the frequency of the system clock signal and the frequency of the memory clock signal.

The commands and addresses coupled from the FIFO buffer 190 by the command selector 200 are coupled to the system memory 140 through a set of output buffers 204, and the data are coupled to and from the system memory 140 through a set of output buffers 204 and input buffers 206.

The manner in which the commands are loaded into the sequencer state matrix 180 will now be explained with reference to FIGS. 3A–3C. With reference to FIG. 3A, for a memory clock signal frequency of 200 MHz, a precharge is loaded into the matrix 180 at time t0. During the next two time slots, t1 and t2, the system memory 140 is being precharged. Since the period of a 200 MHz clock signal is 5 ns, a total of 10 ns is therefore allocated for precharging the system memory 140. The RAS command as well as the row address that will be strobed into the system memory 140 by the RAS command are then loaded into the matrix 180 at time t3. After a delay of two more time slots, t4 and t5, or 10 ns, a column address and a CAS command that will strobe the column address into the system memory 140 are loaded into time slot t6 of the matrix 180. Finally, a time slot t10 is reserved in the matrix 180 to receive the read data. By reserving space in the matrix 180 to receive data, the sequencer load logic 176 avoids inserting a command in the matrix 180 that would be applied to the memory 140 at the same time read data is being output from the memory 140.

In contrast to a memory read at a clock frequency of 200 MHz, the sequencer state matrix 180 may be loaded for a memory read at 100 MHz as shown in FIG. 3B. The precharge command is again loaded into the time slot t0 of the matrix 180, but the RAS command and row address can be loaded into time slot t2 because the lower clock frequency provides a 10 ns precharge time with only a single clock period. In contrast, at a frequency of 200 MHz, it was necessary to load the RAS command and row address into time slot t3. Similarly, the CAS command and column address can be loaded into time slot t4 in contrast to being loaded at time slot t6 at 200 MHz, as shown in FIG. 3A. Finally, time slot t6 is reserved in the matrix 180 for the read data, in contrast to time slot t10 being reserved at 200 MHz, as shown in FIG. 3A.

FIG. 3C shows the manner in which memory commands are stored in the sequencer state matrix 180 in the event of a read from two columns of the same page. As in the example shown in FIG. 3B, the precharge command is loaded into time slot t0, and the RAS command and row address are loaded into time slot t2. Also, the CAS command and column address are again loaded into time slot t4, and time slot t6 is reserved for the data read from the addressed column. However, because a subsequent read is from the same page as the earlier read, the sequencer load logic unit 176 loads the CAS command and the column address for the subsequent read at time t5, and time slot t7 is reserved for the data read from the column addressed in time slot t5.

In each of the cases shown in FIGS. 3A–3C, the number of commands that must be loaded into the sequencer state matrix 180 each period of the system clock signal will depend on the number of commands transferred from the matrix 180 each period of the memory clock signal. For example, for a system clock signal frequency of 200 and a memory clock signal frequency of 400 MHz, the number of commands loaded into the matrix 180 for each period of the system clock signal must be twice the number of commands transferred from the matrix 180 for each period of the memory clock signal so that commands are transferred into and out of the matrix 180 at the same average rate.

From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention. Accordingly, the invention is not limited except as by the appended claims.

INVENTORS:

Jeddeloh, Joseph M.

THIS PATENT IS REFERENCED BY THESE PATENTS:
Patent Priority Assignee Title
10176861, Apr 21 2005 Innovations In Memory LLC RAIDed memory system management
10417159, Apr 21 2005 Innovations In Memory LLC Interconnection system
7636803, Sep 28 2006 ADVANCED SILICON TECHNOLOGIES, LLC Device and method for transferring data between devices
7681099, May 17 2007 Advanced Micro Devices, INC Techniques for integrated circuit clock signal manipulation to facilitate functional and speed test
7737752, May 17 2007 TAIWAN SEMICONDUCTOR MANUFACTURING CO , LTD Techniques for integrated circuit clock management
7921318, May 17 2007 GLOBALFOUNDRIES U S INC Techniques for integrated circuit clock management using pulse skipping
8014485, May 17 2007 Advanced Micro Devices, Inc.; Advanced Micro Devices, INC Techniques for integrated circuit clock management using multiple clock generators
8028186, Oct 23 2006 Innovations In Memory LLC Skew management in an interconnection system
8090973, Oct 23 2006 Innovations In Memory LLC Skew management in an interconnection system
8112655, Apr 21 2005 Innovations In Memory LLC Mesosynchronous data bus apparatus and method of data transmission
8195849, Sep 28 2006 ADVANCED SILICON TECHNOLOGIES, LLC Device and method for transferring data between devices
8452929, Apr 21 2005 Innovations In Memory LLC Method and system for storage of data in non-volatile media
8575972, Mar 23 2009 Advanced Micro Devices, Inc. Digital frequency synthesizer device and method thereof
8726064, Apr 21 2005 Innovations In Memory LLC Interconnection system
8806262, Oct 23 2006 VIOLIN SYSTEMS LLC Skew management in an interconnection system
9286198, Apr 21 2005 Innovations In Memory LLC Method and system for storage of data in non-volatile media
9384818, Apr 21 2005 Innovations In Memory LLC Memory power management
9582449, Apr 21 2005 Innovations In Memory LLC Interconnection system
9727263, Apr 21 2005 Innovations In Memory LLC Method and system for storage of data in a non-volatile media
THIS PATENT REFERENCES THESE PATENTS:
Patent Priority Assignee Title
4245303, Oct 25 1977 Digital Equipment Corporation Memory for data processing system with command and data buffering
5155809, May 17 1989 International Business Machines Corp. Uncoupling a central processing unit from its associated hardware for interaction with data handling apparatus alien to the operating system controlling said unit and hardware
5448715, Jul 29 1992 Hewlett-Packard Company Dual clock domain interface between CPU and memory bus
5471587, Sep 30 1992 Intel Corporation Fractional speed bus coupling
5487092, Dec 22 1994 International Business Machines Corporation System for high-speed synchronization across clock domains
5600824, Feb 04 1994 HEWLETT-PACKARD DEVELOPMENT COMPANY, L P Clock generating means for generating bus clock and chip clock synchronously having frequency ratio of N-1/N responsive to synchronization signal for inhibiting data transfer
5915107, Sep 26 1997 AMD TECHNOLOGIES HOLDINGS, INC ; GLOBALFOUNDRIES Inc Cross clock domain clocking for a system using two clock frequencies where one frequency is fractional multiple of the other
5923193, Dec 11 1996 Intel Corporation Method and apparatus for transferring signals between multiple clock timing domains
5923858, May 01 1997 Cirrus Logic, Inc.; Cirrus Logic, INC Method and apparatus to interface a peripheral device operating in an internal clock domain to a PCI bus operating in a PCI clock domain
6000022, Oct 10 1997 U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT Method and apparatus for coupling signals between two circuits operating in different clock domains
6006340, Mar 27 1998 Synopsys, Inc Communication interface between two finite state machines operating at different clock domains
6016549, Jun 14 1996 LENOVO SINGAPORE PTE LTD Peripheral unit having at least two sequencer circuits configured to control data transfers for power saving
6112307, Dec 30 1993 Intel Corporation Method and apparatus for translating signals between clock domains of different frequencies
6128749, Nov 03 1998 Intel Corporation Cross-clock domain data transfer method and apparatus
6134638, Aug 13 1997 CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC Memory controller supporting DRAM circuits with different operating speeds
6202119, Dec 19 1997 Round Rock Research, LLC Method and system for processing pipelined memory commands
6279077, May 22 1996 Texas Instruments Incorporated Bus interface buffer control in a microprocessor
6279090, Sep 03 1998 Round Rock Research, LLC Method and apparatus for resynchronizing a plurality of clock signals used in latching respective digital signals applied to a packetized memory device
6363076, Jan 27 1998 International Business Machines Corporation; IBM Corporation Phantom buffer for interfacing between buses of differing speeds
6370600, May 25 1999 AMD TECHNOLOGIES HOLDINGS, INC ; GLOBALFOUNDRIES Inc Staging buffer for translating clock domains when source clock frequency exceeds target clock frequency
6389529, Jun 25 1999 International Business Machines Corporation Method for alternate preferred time delivery of load data
6414903, Aug 21 2000 Round Rock Research, LLC Method and apparatus for crossing clock domain boundaries
6434684, Sep 03 1998 U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT Method and apparatus for coupling signals across different clock domains, and memory device and computer system using same
6449703, Jul 13 1998 Round Rock Research, LLC Pipelined memory controller
6526469, Nov 12 1999 International Business Machines Corporation Bus architecture employing varying width uni-directional command bus
6542569, Mar 05 1997 U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT Memory device command buffer apparatus and method and memory devices and computer systems using same
6546451, Sep 30 1999 Hewlett Packard Enterprise Development LP Method and apparatus for decoupling processor speed from memory subsystem speed in a node controller
6590901, Apr 01 1998 CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC Method and apparatus for providing a packet buffer random access memory
6594713, Sep 10 1999 Texas Instruments Incorporated Hub interface unit and application unit interfaces for expanded direct memory access processor
6622228, Jul 31 1998 Round Rock Research, LLC System and method of processing memory requests in a pipelined memory controller
6718449, Jul 09 2001 Sony Corporation; Sony Electronics Inc. System for data transfer between different clock domains, and for obtaining status of memory device during transfer
6775755, Sep 03 1998 Micron Technology, Inc. Method and apparatus for coupling signals across different clock domains, and memory device and computer system using same
ASSIGNMENT RECORDS    Assignment records on the USPTO
///////////
Executed onAssignorAssigneeConveyanceFrameReelDoc
May 10 2002JEDDELOH, JOSEPH M Micron Technology, IncASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS 0129490097 pdf
May 24 2002Micron Technology, Inc.(assignment on the face of the patent)
Apr 26 2016Micron Technology, IncMORGAN STANLEY SENIOR FUNDING, INC , AS COLLATERAL AGENTPATENT SECURITY AGREEMENT0389540001 pdf
Apr 26 2016Micron Technology, IncU S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENTCORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001 ASSIGNOR S HEREBY CONFIRMS THE SECURITY INTEREST 0430790001 pdf
Apr 26 2016Micron Technology, IncU S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENTSECURITY INTEREST SEE DOCUMENT FOR DETAILS 0386690001 pdf
Jun 29 2018U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENTMicron Technology, IncRELEASE BY SECURED PARTY SEE DOCUMENT FOR DETAILS 0472430001 pdf
Jul 03 2018MICRON SEMICONDUCTOR PRODUCTS, INC JPMORGAN CHASE BANK, N A , AS COLLATERAL AGENTSECURITY INTEREST SEE DOCUMENT FOR DETAILS 0475400001 pdf
Jul 03 2018Micron Technology, IncJPMORGAN CHASE BANK, N A , AS COLLATERAL AGENTSECURITY INTEREST SEE DOCUMENT FOR DETAILS 0475400001 pdf
Jul 31 2019JPMORGAN CHASE BANK, N A , AS COLLATERAL AGENTMicron Technology, IncRELEASE BY SECURED PARTY SEE DOCUMENT FOR DETAILS 0510280001 pdf
Jul 31 2019JPMORGAN CHASE BANK, N A , AS COLLATERAL AGENTMICRON SEMICONDUCTOR PRODUCTS, INC RELEASE BY SECURED PARTY SEE DOCUMENT FOR DETAILS 0510280001 pdf
Jul 31 2019MORGAN STANLEY SENIOR FUNDING, INC , AS COLLATERAL AGENTMicron Technology, IncRELEASE BY SECURED PARTY SEE DOCUMENT FOR DETAILS 0509370001 pdf
MAINTENANCE FEES AND DATES:    Maintenance records on the USPTO
Date Maintenance Fee Events
Oct 28 2005ASPN: Payor Number Assigned.
Jun 03 2009M1551: Payment of Maintenance Fee, 4th Year, Large Entity.
Mar 11 2013M1552: Payment of Maintenance Fee, 8th Year, Large Entity.
Jun 15 2017M1553: Payment of Maintenance Fee, 12th Year, Large Entity.


Date Maintenance Schedule
Jan 03 20094 years fee payment window open
Jul 03 20096 months grace period start (w surcharge)
Jan 03 2010patent expiry (for year 4)
Jan 03 20122 years to revive unintentionally abandoned end. (for year 4)
Jan 03 20138 years fee payment window open
Jul 03 20136 months grace period start (w surcharge)
Jan 03 2014patent expiry (for year 8)
Jan 03 20162 years to revive unintentionally abandoned end. (for year 8)
Jan 03 201712 years fee payment window open
Jul 03 20176 months grace period start (w surcharge)
Jan 03 2018patent expiry (for year 12)
Jan 03 20202 years to revive unintentionally abandoned end. (for year 12)