Power control and modulation of switched-mode power amplifiers with one or more stages

Abstract

This invention controls and modulates switched-mode <span class="c15 g0">powerspan> amplifiers to enable the production of signals that include <span class="c3 g0">amplitudespan> modulation (and possibly, but not necessarily, phase modulation), the average <span class="c15 g0">powerspan> of which may be controlled over a potentially wide range.

Description

CROSS-REFERENCE TO RELATED APPLICATION

This application is a Continuation of U.S. Patent application Ser. No. 10/431,976, entitled “POWER CONTROL AND MODULATION OF SWITCHED-MODE POWER AMPLIFIERS WITH ONE OR MORE STAGES” by Stephan V. Schell, Wendell B. Sander, Ronald A. Meck, and Robert J. Bayruns filed on May 7, 2003, now U.S. Pat. No. 6,844,776 which is a continuation of U.S. patent application Ser. No. 09/684,497, filed on Oct. 6, 2000 now U.S. Pat No. 6,734,724.

BACKGROUND

1. Field of the Invention

The present invention relates to power amplifiers, particularly switched-mode power amplifiers.

2. Description of Related Art

Switched-mode power amplifiers have demonstrated the capability of producing, with high power-added efficiency (PAE), phase-modulated signals that have very high signal quality—i.e., low root-mean-square (RMS) phase error relative to an ideal signal and little or no degradation in power spectral density (PSD). These power amplifiers have also been demonstrated to be highly tolerant of temperature variation, and are believed to be highly tolerant to fabrication-process variation, making them attractive for high-volume applications such as consumer electronics. Such power amplifiers include a switch connected to a resonant network; the output of the resonant network is connected in turn to a load (e.g., the antenna in a radio transmitter).

An early switched-mode amplifier is described in U.S. Pat. No. 3,900,823 to Sokal et al., incorporated herein by reference. Sokal et al. describes the problem (created by unavoidable feedthrough from amplifier input to amplifier output) of power control at low power levels and proposes solving the problem by controlling RF input drive magnitude to a final amplifier stage. In particular, the input drive magnitude of the final stage is controlled by using negative feedback techniques to control the DC power supply of one or more stages preceding the final stage. Various other known techniques use variation of amplifier power supply for linearization as described, for example, in the following patents, incorporated herein by reference: U.S. Pat. Nos. 5,091,919; 5,142,240, and 5,745,526.

Another type of switched-mode amplifier, that does not require the use of negative feedback as in Sokal, is described in U.S. patent application Ser. Nos. 09/247,095 and 09/247,097 of the present assignee, entitled HIGH-EFFICIENCY MODULATING RF AMPLIFIER and HIGH-EFFICIENCY AMPLIFIER OUTPUT LEVEL AND BURST CONTROL, respectively, filed Feb. 9, 1999 (WO0048306 and WO0048307) and U.S. patent application Ser. No. 09/637,269, entitled HIGH-EFFICIENCY MODULATING RF AMPLIFIER, filed Aug. 10, 2000, all incorporated herein by reference. In the latter switched-mode power amplifiers, the average power is determined by two signals: the switch supply signal and the switch control signal. The switch supply signal is the DC voltage available on one side of the switch; as this voltage increases, the peak voltage of the oscillatory signals developed within the resonant network and subsequently delivered to the load also increases. The switch control signal is typically a phase-modulated signal that controls the switch (i.e., determines whether the switch is on or off). This switch control signal should be strong enough to toggle the switch on and off but should not be excessively strong: unlike a linear amplifier in which the strength of the output signal is determined by the strength of the input signal, in a switched-mode power amplifier, if the switch control signal is too strong, the excess signal merely leaks through the switch and into the resonant network (i.e., feedthrough). When this occurs, a version of the switch control signal that is out-of-phase with respect to the desired signal adds to the desired signal within the resonant network, altering both the phase and the amplitude of the output signal in an undesirable way.

French Patent 2,768,574 also describes a switched-mode power amplifier arrangement. Referring to FIG. 1, in this arrangement, the power amplifier circuit comprises a DC-to-DC converter 20 and a power amplifier 30. The DC-to-DC converter 20 includes a pulse-width modulator 22, a commutator/rectifier 24 and a filter 26.

The pulse-width modulator 22 is coupled to receive a DC-to-DC command input signal from a signal input terminal 21, and is arranged to apply a pulse-width-modulated signal to the commutator/rectifier 24. The commutator/rectifier 24 is coupled to receive a DC-to-DC power supply input signal from a signal input terminal 25, and is also coupled to apply a switched signal to filter 26. The filter 26 in turn applies a filtered switched signal 28 in common to multiple stages of the power amplifier 30.

A circuit of the foregoing type is substantially limited by the frequency of the pulse-width modulator. In addition, common control of multiple power amplifier stages in the manner described may prove disadvantageous as described more fully hereinafter.

It is desirable to achieve more precise control of switched-mode-generated RF signals, including amplitude-modulated signals, such that the aforementioned benefits of switched-mode power amplifiers may be more fully realized.

SUMMARY OF THE INVENTION

This invention controls and modulates switched-mode power amplifiers to enable the production of signals that include amplitude modulation (and possibly, but not necessarily, phase modulation), the average power of which may be controlled over a potentially wide range.

In order to produce amplitude-modulated signals, the DC switch supply voltage is replaced by a time-varying switch supply signal that is related to the desired amplitude modulation. This switch supply signal can be either the desired amplitude modulation signal itself or a pre-distorted version thereof, where the pre-distortion is such that the output signal has the desired amplitude modulation. In the latter case, the pre-distortion corrects for amplitude non-linearity (so-called AM/AM distortion) in the switch and/or the resonant network.

The foregoing modification alone, however, may be insufficient to provide as much dynamic range in the output signal as may be desired. Also, the modification may not be sufficient to maintain dynamic range in the amplitude modulation while adjusting the average power of the output signal. Both of these problems are caused by the undesirable leakage signal described previously; its contribution to the output is largely independent of the level of the switch supply signal. That is, the switch supply signal may be reduced to zero volts (the minimum possible amplitude), yet the output signal will still be at a relatively high level; below some point, the amplitude modulation imparted through the switch supply signal is manifest less and less in the output signal.

Similarly, the severity of amplitude-dependent phase shift (so-called AM/PM distortion) increases as the switch supply signal decreases. This effect arises because the leakage of the switch control signal is out of phase relative to the desired signal. As the switch supply signal decreases, the desired signal decreases as well, whereas the leakage signal does not; since these two signals are out of phase, the phase of their sum is increasingly dominated by the phase of the leakage signal. This invention, in one aspect thereof, modifies the switched-mode power amplifier by adjusting the amplitude of the switch control signal to reduce the undesirable leakage effect. As a result, it becomes possible to produce output signals having average power anywhere within a wide range, or to greatly increase the dynamic range over which amplitude modulation may be produced at a given average power level, or both.

BRIEF DESCRIPTION OF THE DRAWING FIGURES

The present invention may be further understood from the following description in conjunction with the appended drawing figures. In the figures:

FIG. 1 is a block diagram of a known switched-mode power amplifier in a variable power supply voltage is applied in common to multiple stages;

FIG. 2 is a block diagram of a switched-mode power amplifier without amplitude modulation capability;

FIG. 3 is a diagram comparing AM/PM distortion in a switched-mode power amplifier without a countermeasure of the invention and with a countermeasure of the invention;

FIG. 4 is a waveform diagram of waveforms in the circuit of FIG. 2;

FIG. 5 is one possible circuit that may be used to control the application of power to one or more power amplifier stages;

FIG. 6 is another possible circuit that may be used to control the application of power to one or more power amplifier stages;

FIG. 7 is still another possible circuit that may be used to control the application of power to one or more power amplifier stages;

FIG. 8 is a block diagram of a generalized efficient power amplifier structure;

FIG. 9 is a block diagram of a switched-mode power amplifier having amplitude modulation capability;

FIG. 10 is a waveform diagram of waveforms in the circuit of FIG. 9;

FIG. 11 is another waveform diagram of waveforms in the circuit of FIG. 9;

FIG. 12 is a more detailed diagram of an exemplary embodiment of the switched-mode power amplifier of FIG. 9; and

FIG. 13 is a waveform diagram of waveforms in the circuit of FIG. 12.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring now to FIG. 2, a block diagram is shown of a switched-mode power amplifier. A switch 201 is coupled to a resonant network 205 and to power control logic 215, which is coupled in turn to a DC supply 203. The resonant network is coupled to a load 207. Control of the switch 201 is accomplished using a control signal 209, applied to an amplifier 211. The amplifier 211 produces a switch control signal 219, which is applied to the switch 201. As the switch 201 is opened and closed responsive to the control signal 209, the resonant network 205 shapes the switch voltage to produce a desired output signal 213.

In the amplifier of FIG. 2, the signals 209 and 219 are constant-amplitude (CA) signals (i.e., oscillatory signals having a constant peak amplitude) that may be phase-modulated. The amplitude of the switch control signal 219 is set by the power control logic 215. The power control logic 215 also controls a DC supply voltage 216 produced by the DC supply 203 and supplied to the switch 201. As the power control logic 215 causes the DC supply voltage 216 to increase, the peak voltage of the oscillatory signals developed within the resonant network 205 and subsequently delivered to the load 207 also increases. Similarly, as the power control logic 215 causes the DC supply voltage 216 to decrease, the peak voltage of the oscillatory signals developed within the resonant network 205 and subsequently delivered to the load 207 also decreases.

Further details of the amplifier chain of FIG. 2 in accordance with an exemplary embodiment of the invention are described in the foregoing copending U.S. patent applications. In addition, a bias control arrangement may be used to achieve optimal bias of the switch 201 under various conditions as described more fully in U.S. patent application Ser. No. 09/684,496, filed on even date herewith and incorporated herein by reference.

In accordance with one aspect of the invention, a signal 218 is used to control the amplitude of the switch control signal 219 in a coordinated manner with control of the DC supply voltage 216, thereby avoiding excess leakage of the switch control signal 219 through the switch 201 and into the resonant network 205.

More particularly, in any physical embodiment, a stray (unintended) capacitance 212 around the switch 201 is unavoidably present. This stray capacitance provides a leakage path for the switch control signal 219 to leak into the resonant network 205, where it mixes with the desired switch output signal. Since the switch control signal 219 is out-of-phase with the desired switch output signal, a large phase shift will occur at the switch output when the desired output signal magnitude is near to or smaller than that of the leakage signal. This effect is shown in FIG. 3, which depicts output phase and output magnitude as parametric functions of desired magnitude (i.e., as desired magnitude decreases, the curves of FIG. 3 are traced out in the counter-clockwise direction). In the illustrated case, signal leakage is assumed to be 35 dB below the maximum output signal (1.7%), at a relative phase shift of −170 degrees. If the switch control signal is not reduced (line A), then the amplifier output signal suffers severe AM-PM (and AM-AM) distortion when the desired output magnitude is less than 10% of the peak output magnitude.

This effect may be counteracted, for lower amplitude output signals (e.g., less than 10% of the peak output magnitude), by correspondingly reducing the switch control signal (e.g., to 10% of its original value). As FIG. 3 shows, this measure essentially removes the AM-PM and AM-AM distortion from the desired output signal (line B). In principle, this technique can be extended to arbitrarily low desired output signal magnitudes.

For illustration purposes, consider the need to produce a constant-amplitude RF signal in a time-slotted network, in which the output power may vary from slot to slot. In the amplifier of FIG. 2, this manner of operation may be achieved by holding the supply voltage 216 constant during a given time slot, and by holding the peak amplitude of the control signal constant during the time slot as illustrated in FIG. 4. As a result, the peak amplitude of the output signal 213 is constant during a given time slot. Note that when the supply voltage 216 is is at a low level, the control signal 219 is also at a correspondingly low level (e.g., time slot (N)). In this manner, the low-distortion characteristic of line B of FIG. 3 is achieved.

Various specific circuits that may be used within the power control logic 215 of FIG. 2 to control the application of power to the amplifier stages are shown in FIG. 5, FIG. 6, and FIG. 7, respectively.

Referring first to FIG. 5, a DC supply voltage V_SUPPLY is applied to the emitter of a PNP bipolar transistor Q in common-emitter configuration. The DC supply voltage may be unregulated or, alternatively, may have been regulated/conditioned to an appropriate DC level for a desired instantaneous output power using, for example, a switching power supply in combination with a linear regulator as described in greater detail in the aforementioned patent applications. The collector of the transistor Q is connected through a resistive divider network R1, R2 to ground. An operational amplifier 501 is connected to receive a power-setting command signal 523 on a negative input and to receive on its positive input a voltage developed at the junction of the resistors R1 and R2. The operational amplifier 501 produces an output signal that is applied to the base of the transistor Q. In operation, the transistor functions as a controlled resistance, under control of the operational amplifier 501, to deliver a precisely-controlled voltage to multiple amplifier stages, including, for example, a driver stage 503 (responsive to an RF signal 509 analogous to signal 209 of FIG. 2) and a final stage 505. In the case of the driver stage 503, the controlled voltage from the transistor Q is applied through a resistor R3 to account for the sizing of the driver amplifier relative to the final amplifier. The foregoing circuit realizes fast control and may be used in conjunction with or in lieu of separate DC regulation circuitry.

One or more additional driver stages may be provided as shown, for example, in FIG. 6. In FIG. 6, the supply voltage of an initial stage 607 is controlled less stringently. A number of discrete supply voltages (V₁, V₂, . . . , V_N) are applied to a switch 609, which is controlled to select a desired one of the discrete voltages. Control of the final stage 605 and the immediately preceding driver stage 603 may remain as previously described.

If a desired output signal has a large dynamic range, common control of the driver and final stages may prove insufficient. Referring to FIG. 7, separate control is provided for each of multiple amplifier stages. This arrangement may be extended to any arbitrary number of stages.

Referring again to FIG. 2, in the case of constant amplitude output signals, the amplifier as shown is effective to provide efficient amplification and power control. However, it does not provide for amplitude modulation.

Referring now to FIG. 8, a generalized efficient power amplifier structure is shown, enabling control of multiple stages to achieve complex control, including amplitude modulation, of an amplifier output signal. In FIG. 8, an RF input signal, RF_in, is applied to an amplifier chain including N stages. The amplifier chain produces an RF output signal, RF_out. Supply voltages for each of the stages are independently controlled. One or more control blocks receive a DC supply voltage and, responsive to control signals from a controller (not shown), produce separate power supply voltages for each of the N amplifier stages. In the example of FIG. 8, two control blocks are shown, a power/burst control block 801 and a modulation control block 803. However, the functions of the control blocks may be readily consolidated or sub-divided as will be apparent to one of ordinary skill in the art.

Optionally, independent bias signals may be supplied to each one of the stages. In one embodiment, possible values of the bias signal include a value that turns the stage off, e.g., places the active element of the stage in a high-impedance state. In addition, each stage may optionally include a controlled bypass element or network, shown in FIG. 8 as a resistor connecting the input and output terminals of a stage. Such a bypass may allow performance of an amplifier stage at low input signal levels to be more completely characterized and controlled. In particular, since circuit parasitics unavoidably create the effect of a bypass, by explicitly providing a bypass, it may be designed in such a manner as to dominate parasitic effects.

A particular case of the generalized amplifier structure of FIG. 8 will now be described in detail.

Referring to FIG. 9, an amplifier is shown that provides the advantages of the amplifier of FIG. 2 and additionally provides for amplitude modulation. In FIG. 9, there is provided a switch 901, a DC supply 903, a resonant network 905, a load 907, a control signal 909, a control signal amplifier 911, an output signal 913 and power control logic 915, corresponding generally to and given like designations as elements in FIG. 2. The control signal amplifier 911 is responsive to a drive control signal 918 to produce a switch control signal 919 In FIG. 9, however, there is additionally provided an amplitude modulator 917 responsive to an AM signal 923. Instead of the power control logic 915 controlling the control signal amplifier 911 directly (as in FIG. 2), the power control logic 915 is coupled to the amplitude modulator 917, which is responsive to the power control logic 915 to control the control signal amplifier 911. Under the control of the amplitude modulator 917, the control signal amplifier 911 produces a switch control signal 919 that is applied to the switch 901. The DC supply 903 is coupled to the amplitude modulator 917, which is responsive to the AM signal 923 to modify the supply voltage appropriately and apply a resulting switch supply signal 921 to the switch 901.

Two cases of operation of the amplifier of FIG. 9 may be distinguished. One case is shown in FIG. 10, in which amplitude modulation is achieved solely through variation of the switch supply signal 921, and power control is achieved jointly through variation of the DC supply 903 and variation of the switch control signal 919 (via signal 918). During a timeslot (N−1), the peak amplitude of the switch control signal 919 remains constant. During this time, the peak amplitude of the control signal 909 also remains constant. The switch supply signal 921, on the other hand, has impressed upon it amplitude modulation signal variations. As a result, the output signal 913 exhibits corresponding amplitude variations. During timeslot (N), the amplitudes of the control signal 909 and the switch control signal 919 are constant at a lower level, and a DC supply voltage 904 (not shown in FIG. 10) is also constant at a lower level, indicative of a lower desired output power level. Different amplitude modulation signal variations are impressed upon the switch supply signal 921 and are manifest in the amplitude of the output signal 913. During timeslot (N+1), the level of the control signal 909 and the switch control signal 919 are raised back up, as is the DC supply voltage 904, corresponding to a higher desired output power level. The constant peak amplitude of the switch control signal 919 is set higher for higher desired output power levels, and set lower for lower desired output power levels, so that the switch 901 is successfully turned on and off as needed while minimizing the undesirable leakage of the switch control signal 919 through the switch 901 and into the resonant network 905.

At lower power levels, to avoid excess leakage of the switch control signal 919 into the output signal 913, it may be necessary to achieve amplitude modulation of the output signal through coordinated variation of both the switch supply signal 921 and the switch control signal 919. This represents the second case of operation previously referred to, and is illustrated in FIG. 11. In particular, FIG. 11 shows examples of different relationships between amplitude modulation of the switch supply signal 921 and amplitude modulation of the switch control signal 919. Power control and amplitude modulation of both the switch supply signal 921 and the switch control signal 919 are applied as needed to extend the dynamic range of the output signal 913. In an exemplary embodiment, amplitude modulation of the switch control signal 919 is applied only when the AM signal 923 dips below a threshold that is power-level dependent.

Timeslot (N−1) illustrates the case in which the AM signal 923 is below the power-level-dependent threshold (indicated in dashed lines in the upper frame of the FIG. 11) for the duration of the timeslot. Hence, the switch control signal 919 is amplitude modulated along with the switch supply signal 921 throughout the duration of the timeslot. In timeslot (N), during both an initial portion of the timeslot and during a final portion of the timeslot, the AM signal 923 is assumed to be above the threshold. Hence, during these portions of the timeslot, the switch control signal 919 is not amplitude modulated. (In the middle frame of FIG. 11, the dashed lines indicate the nominal amplitude of the switch control signal 919 when the AM signal 923 is above the threshold.) During an intermediate portion of the timeslot, however, the AM signal 923 is assumed to be below the threshold. During this portion of the timeslot, the switch control signal 919 is amplitude modulated along with the switch supply signal 921. Finally, in timeslot (N+1), the AM signal 923 is assumed to be above the threshold throughout the duration of the timeslot. The amplitude (peak-to-peak) of the switch control signal 919 is therefore held constant throughout the duration of the timeslot. Note that the actual amplitude modulation is still solely impressed on the output signal 913 by switch supply signal 921. Variation of signal 918 and the resulting variation of signal 919 in concert with signal 921 is performed soley to reduce leakage. As such, the precision required of signal 918 is greatly reduced from that required of signal 921.

Referring now to FIG. 12, a more detailed diagram is shown of an amplifier in accordance with an exemplary embodiment of the invention, in which like elements are assigned like reference numerals as in FIG. 9. In the embodiment of FIG. 12, the control signal amplifier 1211 and the switch 1201 are provided as first and second amplifier stages, a “gain” stage and a “switch” stage, respectively. The gain stage 211 may be implemented in a variety of ways. One implementation is a conventional gain-controlled linear CCS (controlled current source) amplifier of widely-understood classes A, AB, B and C. An alternative implementation is a smaller-scale switch-mode stage of a type described in the aforementioned copending U.S. applications.

Within dashed line block 917 are shown further details of one embodiment of the amplitude modulator 917 of FIG. 9. In response to AM signal samples 1223 and to a signal 1232 from the power control logic 1215, the AM logic 1231 calculates appropriate supply levels for the first amplifier stage 1211 and the second amplifier stage 1201.

In the case of the first amplifier stage 1211, a DC supply voltage is supplied through a transistor 1235-1. Base drive to the transistor 1235-1 is controlled by the AM logic 1231 through a DAC (digital to analog converter) 1233-1. Hence the DAC 1233-1 sets the level of the switch control signal 1219 seen by the second amplifier stage 1201. Similarly, in the case of the second amplifier stage 1201, a DC supply voltage is supplied through a transistor 1235-2. Base drive to the transistor 1235-2 is controlled by the AM logic 1231 through a DAC 1233-2.

In an exemplary embodiment, the output of the DAC 1233-1 is given by the following rule:

$\begin{array}{cc}{\mathrm{DAC}}_1\left(t\right)=v\left(p\right),& \mathrm{for}a\left(t\right)\ge m\left(p\right)\\ =v\left(p\right)·\frac{a\left(t\right)}{m\left(p\right)},& \mathrm{for}a\left(t\right)<m\left(p\right)\end{array}$
where a(t) is the AM signal at time t, m(p) is a threshold dependent on the power level p, and v(p) is the nominal output voltage of DAC₁, for power level p.

Operation of the amplifier of FIG. 12 in accordance with the foregoing rule is illustrated in FIG. 13. As seen therein, as the signal a(t) (the amplitude of the AM signal at time t) fluctuates, for a first period of time, the signal exceeds the threshold m(p) for the current power level p. During this period, the voltage DAC₁(t) is set to the nominal level v(p). Thereafter, the signal a(t) dips below the threshold for a period of time. During this period of time, the voltage DAC₁ (t) is amplitude modulated in accordance with the fluctuations of the signal a(t). When the signal a(t) again rises above the threshold, the voltage DAC₁ (t) is again set to the nominal level.

Thus, there has been described an efficient amplifier for RF signals that provides for amplitude modulation over a wide dynamic range. The amplitude of the switch control signal is adjusted to reduce the undesirable leakage effect. As a result, it becomes possible to produce output signals having average power anywhere within a wide range, or to greatly increase the dynamic range over which amplitude modulation may be produced at a given average power level, or both.

It will be apparent to those of ordinary skill in the art that the present invention can be embodied in other specific forms without departing from the spirit or essential character thereof. The described embodiments are therefore intended to be in all respects illustrative and not restrictive. The scope of the invention is indicated by the appended claims, rather than the foregoing description, and all changes which come within the meaning and range of equivalents thereof are intended to be embraced therein.

Claims

1. A <span class="c12 g0">multistagespan> <span class="c1 g0">amplifierspan> apparatus, comprising:

a <span class="c0 g0">firstspan> <span class="c1 g0">amplifierspan> <span class="c2 g0">stagespan> having an <span class="c8 g0">inputspan> <span class="c10 g0">portspan> <span class="c11 g0">configuredspan> to receive an <span class="c8 g0">inputspan> <span class="c21 g0">signalspan>, a <span class="c15 g0">powerspan> <span class="c25 g0">supplyspan> <span class="c10 g0">portspan> <span class="c11 g0">configuredspan> to receive a <span class="c0 g0">firstspan> <span class="c25 g0">supplyspan> <span class="c26 g0">voltagespan> and an <span class="c4 g0">outputspan> <span class="c10 g0">portspan> <span class="c11 g0">configuredspan> to provide a switch <span class="c20 g0">controlspan> <span class="c21 g0">signalspan> having a <span class="c0 g0">firstspan> <span class="c6 g0">constantspan> <span class="c7 g0">peakspan> <span class="c3 g0">amplitudespan> during a <span class="c0 g0">firstspan> <span class="c9 g0">timespan> span;

circuitry operable to reduce the <span class="c7 g0">peakspan> <span class="c3 g0">amplitudespan> of said switch <span class="c20 g0">controlspan> <span class="c21 g0">signalspan> from said <span class="c0 g0">firstspan> <span class="c6 g0">constantspan> <span class="c7 g0">peakspan> <span class="c3 g0">amplitudespan> during the <span class="c0 g0">firstspan> <span class="c9 g0">timespan> span to a <span class="c5 g0">secondspan> <span class="c6 g0">constantspan> <span class="c7 g0">peakspan> <span class="c3 g0">amplitudespan> during a <span class="c5 g0">secondspan> <span class="c9 g0">timespan> span, if an <span class="c4 g0">outputspan> <span class="c15 g0">powerspan> of said <span class="c1 g0">amplifierspan> apparatus becomes less than an <span class="c4 g0">outputspan> <span class="c15 g0">powerspan> <span class="c16 g0">thresholdspan>;

and

a switch-mode <span class="c1 g0">amplifierspan> <span class="c2 g0">stagespan> coupled to said <span class="c0 g0">firstspan> <span class="c1 g0">amplifierspan> <span class="c2 g0">stagespan>, said switch-mode <span class="c1 g0">amplifierspan> <span class="c2 g0">stagespan> having a <span class="c15 g0">powerspan> <span class="c25 g0">supplyspan> <span class="c10 g0">portspan> <span class="c11 g0">configuredspan> to receive a <span class="c5 g0">secondspan> <span class="c25 g0">supplyspan> <span class="c26 g0">voltagespan>.

2. The <span class="c12 g0">multistagespan> <span class="c1 g0">amplifierspan> apparatus of claim 1, further comprising a third <span class="c1 g0">amplifierspan> <span class="c2 g0">stagespan> coupled to said <span class="c0 g0">firstspan> <span class="c1 g0">amplifierspan> <span class="c2 g0">stagespan>.

3. A <span class="c12 g0">multistagespan> <span class="c1 g0">amplifierspan> apparatus adapted to operate in a <span class="c9 g0">timespan>-slotted system, comprising:

a <span class="c0 g0">firstspan> <span class="c1 g0">amplifierspan> <span class="c2 g0">stagespan> having an <span class="c8 g0">inputspan> <span class="c10 g0">portspan> <span class="c11 g0">configuredspan> to receive an <span class="c8 g0">inputspan> <span class="c21 g0">signalspan>, a <span class="c0 g0">firstspan> <span class="c15 g0">powerspan> <span class="c25 g0">supplyspan> <span class="c10 g0">portspan> <span class="c11 g0">configuredspan> to receive a <span class="c0 g0">firstspan> <span class="c25 g0">supplyspan> <span class="c26 g0">voltagespan>, and an <span class="c4 g0">outputspan> <span class="c10 g0">portspan> <span class="c11 g0">configuredspan> to provide a switch <span class="c20 g0">controlspan> <span class="c21 g0">signalspan>; and

a switch-mode <span class="c1 g0">amplifierspan> <span class="c2 g0">stagespan> having an <span class="c8 g0">inputspan> <span class="c10 g0">portspan> <span class="c11 g0">configuredspan> to receive said switch <span class="c20 g0">controlspan> <span class="c21 g0">signalspan> and a <span class="c5 g0">secondspan> <span class="c15 g0">powerspan> <span class="c25 g0">supplyspan> <span class="c10 g0">portspan> <span class="c11 g0">configuredspan> to receive a <span class="c5 g0">secondspan> <span class="c25 g0">supplyspan> <span class="c26 g0">voltagespan>,

wherein a <span class="c7 g0">peakspan> <span class="c3 g0">amplitudespan> of said switch <span class="c20 g0">controlspan> <span class="c21 g0">signalspan> is set by said <span class="c0 g0">firstspan> <span class="c1 g0">amplifierspan> <span class="c2 g0">stagespan> to have a <span class="c0 g0">firstspan> <span class="c6 g0">constantspan> <span class="c7 g0">peakspan> <span class="c3 g0">amplitudespan> during at least a portion of a <span class="c0 g0">firstspan> <span class="c9 g0">timespan> slot, and is set to have a <span class="c5 g0">secondspan> <span class="c6 g0">constantspan> <span class="c7 g0">peakspan> <span class="c3 g0">amplitudespan> during at least a portion of a <span class="c5 g0">secondspan> <span class="c9 g0">timespan> slot.

4. The <span class="c12 g0">multistagespan> <span class="c1 g0">amplifierspan> apparatus of claim 3 wherein the <span class="c0 g0">firstspan> <span class="c25 g0">supplyspan> <span class="c26 g0">voltagespan> is independent of the <span class="c5 g0">secondspan> <span class="c25 g0">supplyspan> <span class="c26 g0">voltagespan>.

5. The <span class="c12 g0">multistagespan> <span class="c1 g0">amplifierspan> apparatus of claim 3, further comprising a third <span class="c1 g0">amplifierspan> <span class="c2 g0">stagespan> coupled to said <span class="c0 g0">firstspan> <span class="c1 g0">amplifierspan> <span class="c2 g0">stagespan>.

6. The <span class="c12 g0">multistagespan> <span class="c1 g0">amplifierspan> apparatus of claim 1, further comprising <span class="c3 g0">amplitudespan> modulator circuitry operable to apply <span class="c3 g0">amplitudespan> modulation to said <span class="c5 g0">secondspan> <span class="c25 g0">supplyspan> <span class="c26 g0">voltagespan>.

7. The <span class="c12 g0">multistagespan> <span class="c1 g0">amplifierspan> apparatus of claim 6 wherein said <span class="c3 g0">amplitudespan> modulator circuitry is further operable to apply <span class="c3 g0">amplitudespan> modulation to said switch <span class="c20 g0">controlspan> <span class="c21 g0">signalspan>.

8. The <span class="c12 g0">multistagespan> <span class="c1 g0">amplifierspan> apparatus of claim 1 wherein said <span class="c3 g0">amplitudespan> modulator circuitry is operable to apply <span class="c3 g0">amplitudespan> modulation to said switch <span class="c20 g0">controlspan> <span class="c21 g0">signalspan> when an <span class="c3 g0">amplitudespan> of said <span class="c8 g0">inputspan> <span class="c21 g0">signalspan> received at the <span class="c8 g0">inputspan> <span class="c10 g0">portspan> of said <span class="c0 g0">firstspan> <span class="c1 g0">amplifierspan> <span class="c2 g0">stagespan> falls below a predetermined <span class="c16 g0">thresholdspan>.

9. The <span class="c12 g0">multistagespan> <span class="c1 g0">amplifierspan> apparatus of claim 1 wherein the <span class="c0 g0">firstspan> <span class="c25 g0">supplyspan> <span class="c26 g0">voltagespan> is independent of the <span class="c5 g0">secondspan> <span class="c25 g0">supplyspan> <span class="c26 g0">voltagespan>.

10. The <span class="c12 g0">multistagespan> <span class="c1 g0">amplifierspan> apparatus of claim 1 wherein the <span class="c0 g0">firstspan> <span class="c25 g0">supplyspan> <span class="c26 g0">voltagespan> is related to the <span class="c5 g0">secondspan> <span class="c25 g0">supplyspan> <span class="c26 g0">voltagespan>.

11. The <span class="c12 g0">multistagespan> <span class="c1 g0">amplifierspan> apparatus of claim 3, further comprising <span class="c3 g0">amplitudespan> modulator circuitry operable to apply <span class="c3 g0">amplitudespan> modulation to said <span class="c5 g0">secondspan> <span class="c25 g0">supplyspan> <span class="c26 g0">voltagespan>.

12. The <span class="c12 g0">multistagespan> <span class="c1 g0">amplifierspan> apparatus of claim 11 wherein said <span class="c3 g0">amplitudespan> modulator circuitry is further operable to apply <span class="c3 g0">amplitudespan> modulation to said switch <span class="c20 g0">controlspan> <span class="c21 g0">signalspan>.

13. The <span class="c12 g0">multistagespan> <span class="c1 g0">amplifierspan> apparatus of claim 11 wherein said <span class="c3 g0">amplitudespan> modulator circuitry is operable to apply <span class="c3 g0">amplitudespan> modulation to said switch <span class="c20 g0">controlspan> <span class="c21 g0">signalspan> when an <span class="c3 g0">amplitudespan> of said <span class="c8 g0">inputspan> <span class="c21 g0">signalspan> received at the <span class="c8 g0">inputspan> <span class="c10 g0">portspan> of said <span class="c0 g0">firstspan> <span class="c1 g0">amplifierspan> <span class="c2 g0">stagespan> falls below a predetermined <span class="c16 g0">thresholdspan>.

14. The <span class="c12 g0">multistagespan> <span class="c1 g0">amplifierspan> apparatus of claim 3 wherein the <span class="c0 g0">firstspan> <span class="c25 g0">supplyspan> <span class="c26 g0">voltagespan> is related to the <span class="c5 g0">secondspan> <span class="c25 g0">supplyspan> <span class="c26 g0">voltagespan>.