A current summing type d/A converter having a configuration of two or more steps is provided. In a d/A converter block of the first step, by adding current segments, upper bits are d/A converted, and one of the current segments in the first step is further supplied to a d/A converter block in a second step to be shunt by the d/A converter block in the second step, so that lower bits are d/A converted. The output current in the first step and the output current in the second step are then added each other. According to the foregoing method, the d/A conversion may be performed without causing a differential linearity error.
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1. A d/A converter comprising: a first d/A converter block for converting upper bits of digital data having of a plurality of bits; and a second d/A converter block for converting lower bits of the digital data, said digital data being d/A converted in two steps using said first d/A converter block and said second d/A converter block,
wherein said first d/A converter block comprises two or more constant current sources, a first switch for adding respective output currents from a part of said two or more constant current sources, the number of the part corresponds to a value of the upper bits of said digital data, to output an added current, and a second switch for supplying a current from the remaining one constant current source of said two or more constant current sources to said second d/A converter block,
wherein said second d/A converter block comprises a current shunt for shunting the current supplied from said first d/A converter block at a shunt ratio corresponding to a value of the lower bits of said digital data and outputting a shunt current, and
wherein the current outputted from said first switch and the shunt current outputted from said current shunt are added each other, so that a current corresponding to said digital data is outputted.
5. A d/A converter comprising: a first d/A converter block for converting upper bits of digital data having of a plurality of bits; and a second d/A converter block for converting lower bits of the digital data, said digital data being d/A converted in two steps by said first d/A converter block and said second d/A converter block,
wherein said first d/A converter block comprises a first current shunt for shunting a constant current outputted from a reference current source at a shunt ratio corresponding to a value of the upper bits of said digital data to output a shunt current, and shunting a current outputted from said reference current source into a value corresponding to a weight of a Least significant bit among the upper bits of said digital data to supply a shunt current to said second d/A converter block,
wherein said second d/A converter block comprises a second current shunt for shunting the current supplied from said first d/A converter block at a shunt ratio corresponding to a value of the lower bits of said digital data to output a shunt current, and
wherein the current outputted from said first current shunt and the current outputted from said second current shunt are added each other, so that a current corresponding to said digital data is outputted.
3. A signal converter including at least one A/d converter according to
4. A signal converter including at least one d/A converter according to
6. The d/A converter according to
wherein said reference current source is any one of said two or more current sources, and
wherein the output current from said current segment type d/A converter block is added to the output current from said first current shunt and the output current from said second current shunt, so that a current corresponding to said extended digital data is outputted.
8. A signal converter including at least one A/d converter according to
9. A signal converter including at least one d/A converter according to
11. A signal converter including at least one A/d converter according to
12. A signal converter including at least one d/A converter according to
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1. Field of the Invention
The present invention relates to a current summing type D/A (digital to analog) converter, an A/D (analog to digital) converter using the D/A converter, and a signal converter including the D/A converter or the A/D converter.
2. Description of the Related Art
There exists a semiconductor integrated circuit, which incorporates a large number of D/A (digital to analog) converters to perform signal processing. To achieve high accurate performance has been strongly required particularly to the D/A converter, and the resolution of the D/A converter has been improved by increasing the number of bits in a digital signal.
In this signal converter, a digital-to-analog conversion is performed by a D/A converter 5 based on a current IREF outputted from a reference current source 1. More specifically, based on the current IREF, the D/A converter 5 outputs a current corresponding to a digital set point D9 to D0. In this signal converter, an ON/OFF control is also performed to the current outputted from the D/A converter using a current mirror CM11 provided with a switch SW101. Thus, a current provided to a laser diode (LD) 2 is ON/OFF controlled to thereby provide a laser output light to be switched. The current mirror CM11 is composed of transistors M101 and M102.
The laser light outputted from the laser diode 2 may be used as, for example, a recording signal for an optical disk such as DVD or CD. In this signal converter, the output current value is adjusted by changing the digital set point D9 to D0 of the D/A converter 5, allowing an optimum power output to be used as the recording signal for DVD and CD.
Apart of the laser light outputted therefrom is inputted to a photodiode (PD) 3. A voltage V101 is applied to the photo diode 3 shown in
In
The conventional D/A converter, however, has had two problems to be solved. One is a layout pattern, while the other is a change in characteristics due to manufacturing variability of the resistors.
The conventional D/A converter shown in
Japanese Unexamined Patent Publication (Kokai) No. S62-214728 (Patent Application No. S61-56850) discloses an attempt to eliminate the weight for the transistors by adding a correction current to a base current of the transistor. The current variation produced by a change in resistance value of the resistorR caused by the manufacturing variability, however, could not be prevented. The change in characteristics caused by the variation in the resistance value of the resistor R has been a significant issue in the D/A converter, especially in the high-resolution D/A converter with a large bit number.
A connection relation among the switches SW201 through SW211 shown in
Similarly, the current flowing through the transistor Q202 must be equal to the sum of the currents flowing through the transistors Q203 through Q211. When the variation by 1/256=0.4% of the resistance value of the resistor R2 is produced by the manufacturing variability, the current error will occurs in the output current by 1LSB.
An aspect of the current error affecting the characteristics in this case is shown in
In the signal converter for driving the laser diode shown in
While Patent Application No. S61-56850 describes an example of a binary type D/A converter using the R-2R resistor, Japanese Unexamined Patent Publication (Kokai) No. S59-186416 (Patent Application No. S58-60881) describes an example of a current summing type D/A converter utilizing a combination of a segment type D/A converter and the binary type D/A converter using the R-2R resistor.
The errors produced in the current flowing through the D/A converter by the R-2R resistor and the current flowing through the segment type D/A converter will cause the differential linearity error during the D/A conversion. In Patent Application No. S58-60881, the current values flowing through the two D/A converters are corrected using a compensation circuit. The method described in Patent Application No. S58-60881, however, has not been able to prevent the differential linearity error due to the current error generated between the respective segments.
Japanese Unexamined Patent Publication (Kokai) No. S55-034536 (Patent Application No. S53-106675) describes a method in which the D/A conversion is achieved by connecting two current segment type D/A converters composed of current sources via the current mirror. Even by the method, however, the generation of the differential linearity error due to the error of the current mirror has not been able to be reduced.
While the device shown in
According to this comparison type A/D converter, a reference voltage VAREF supplied from a voltage source V501 is converted into a current I501 using a differential amplifier 8A and a resistor R501, and the converted current is transmitted to a D/A converter 9 via a current mirror CM13. Using the current I501 as a reference current, the D/A conversion is then performed in the D/A converter 9 to generate a current I502. The current I502 is supplied to a resistor R502 via a current mirror CM14. The comparison voltage VREF is thus generated. This comparison voltage VREF is inputted to a comparator 8B along with an analog voltage VAIN inputted from an external source, and those are compared in the comparator 8B to perform the A/D conversion. A control logic 10 is driven by a Clock to search a digital result using a binary search, and outputs the result to digital output terminals D9 to D0. If the D/A converter 9 being used then has a step height in input/output characteristics as shown in
In a signal processing apparatus, which drives the laser diode with the current, there has been a problem that when the step height (differential linearity error) has been generated during the D/A conversion, the laser output has been unstable due to the oscillation in setting a laser intensity. In order to solve the problem, it is necessary to achieve the monotonically increasing characteristics not having the step height during the D/A conversion characteristics; namely, the differential linearity error is small.
Meanwhile, also in the comparison type A/D converter using the D/A converter, if there is the differential linearity error in the D/A conversion section, the error is generated during the digital conversion, so that a D/A converter having the small differential linearity error will be required.
It is an object of the present invention to provide a D/A converter having an excellent differential linearity, without adding a correction circuit even in a high-resolution D/A converter with an increased number of bits, and an A/D converter and a signal converter using the same.
According to the present invention, a D/A conversion is performed in two or more steps using two or more current output type D/A converters. For example, in a first step, upper bits are D/A converted using the current segment manner, while in a second step; lower bits are D/A converted by a shunt current. At the D/A conversion performed in the second step, there is employed a method in which one of the currents generated in the first step is selected, and by shunting a current using the selected current as a reference current, the D/A conversion is then performed, and the current generated in the second step and the current generated in the first step are added each other, thereby generating an output current corresponding to digital data. As a result of this, the D/A conversion having the excellent differential linearity may be performed.
More specifically, the D/A converter according to a first aspect of the present invention includes a first D/A converter block for converting the upper bits of the digital data having of a plurality of bits, and a second D/A converter block for converting the lower bits of the digital data, wherein the digital data is D/A converted in two steps using the first D/A converter block and the second D/A converter block. The first D/A converter block includes two or more constant current sources, a first switch for adding respective output currents from constant current sources each other, the number of which corresponds to a value of the upper bits of the digital data, among the two or more constant current sources to output an added current, and a second switch for supplying a current from the remaining one constant current source among the two or more constant current sources to the second D/A converter block. Moreover, the second D/A converter block includes current shunt means for shunting the current supplied from the first D/A converter block at a shunt ratio corresponding to a value of the lower bits of the digital data and outputting a shunt current. The D/A converter outputs a current corresponding to the digital data by adding the current outputted from the first switch and the current outputted from the current shunt means each other.
In addition, a D/A converter according to a second aspect of the present invention includes a first D/A converter block for converting upper bits of digital data including of a plurality of bits, and a second D/A converter block for converting lower bits of the digital data, wherein the digital data is D/A converted in two steps using the first D/A converter block and the second D/A converter block. The first D/A converter block includes the first current shunt means for shunting a constant current outputted from a reference current source at a shunt ratio corresponding to a value of the upper bits of the digital data to output a shunt current, and shunting the current outputted from the reference current source into a value corresponding to a weight of a Least Significant Bit among the upper bits of the digital data to supply a shunt current to the second D/A converter block. Moreover, the second D/A converter block includes second current shunt means for shunting the current supplied from the first D/A converter block at a shunt ratio corresponding to a value of the lower bits of the digital data to output a shunt current. The D/A converter outputs the current corresponding to the digital data by adding the current outputted from the first current shunt means and the current outputted from the second current shunt means each other.
A D/A converter according to a third aspect of the present invention, in the D/A converter of the foregoing second invention, in order to D/A convert extended digital data having an additional bit on an upper bit side of the digital data, further includes a current segment type D/A converter block which is composed of two or more current sources and outputs a current corresponding to a value of the additional bit, wherein the reference current source is any one of the two or more current sources, and wherein the output current from the current segment type D/A converter block is added to the output current from the first current shunt means and the output current from the second current shunt means, so that a current corresponding to the extended digital data is outputted.
An A/D converter according to a fourth aspect of the present invention performs the A/D conversion using the D/A converter according to any one of the foregoing first, second, and third aspects.
A signal converter according to a fifth aspect of the present invention includes at least one D/A converter according to any one of the foregoing first, second, and third aspects, wherein the output current is controlled using the D/A converter.
A signal converter according to a sixth aspect of the present invention includes at least one A/D converter according to the foregoing fourth aspect, wherein the output current is controlled using the D/A converter included in the A/D converter.
By implementing the aspects of the present invention, even when a current error occurs due to the variation in resistance caused by the manufacturing variability, occurrences of the differential linearity error can be reduced. Especially, when the high-resolution D/A conversion is performed using R-2R resistors, the current error due to the variation in resistance is significant, but the D/A conversion with the small differential linearity error can be achieved by applying the present invention.
Hereafter, referring to the drawings, embodiments according to the present invention will be described in detail.
This D/A converter performs a 10-bit D/A conversion. In
According to the first embodiment shown in
A decoder 230A shown in
In the D/A converter block 210, current sources 11 through 14 are configured, each outputting the same current value based on a reference current IREF inputted from a terminal IIN, by a current mirror composed of transistors M601 through M605. The current sources I1 through I4 shown here are the same as those represented by symbols I1 through I4 in
Moreover, the D/A converter block 210 includes the selection transistors M606 through M613, each two being assigned to each of the current sources I1 through I4, and outputs an output current of one transistor to a node VB for D/A converting the lower bits, and an output current of the other transistor to a node VA to be an output terminal. Here, the digital codes B9=1, B8=0, B7=1, B6 through B0=0 are inputted, and the D/A conversion for outputting the output currents corresponding to the input digital codes is performed (refer to
The currents I1 and I2 generated by the transistors M602 and M603 shown in
A section represented by symbol 220 in
The selection transistors M614 through M621 and selection transistors M622 through M629 are exclusively electrically conducted, respectively.
Here, it is assumed that a current value I/256 is generated on the current I13 shown in
When the current I3 is supplied to the node VB, the current I3 is shunt by the resistors R, and the current corresponding to (I3)/2 is outputted to the node VA in the case of B7=1 and B6 through B0=0.
Accordingly, the current I1+I2+(I3/2) is outputted at the node VA, allowing a D/A converted current to be outputted. Even when the lower bits B6 through B0 are changed, the current source 13 remains unchanged, but the current is continuously changed, and when B9=1 and B8=1 are achieved, the current I1+I2+I3 is outputted to the output terminal. When the digital codes are further increased and become from a range of B9=1, B8=1, B7 through B0=0 to a range of B9=1, B8=1, B7 through B0=1, a current obtained by adding a shunt current of 14 to the current (I1+I2+I3) will be outputted.
A differential linearity error shown in
Moreover, even when either of the currents I1, I2, I3, or I4 may cause an error due to a variation in characteristics of the transistors, the output current is obtained by adding the currents I1 through I4 to a shunt current of either of them as shown in
According to the embodiment shown in
Symbol 310 represents a D/A converter block for performing the D/A conversion using the current segment manner to the upper 2 bits. Symbol 320 represents a D/A converter block for D/A converting the lower 8 bits using the currents shunt by the R-2R resistors.
A voltage of a voltage source V901 shown in
The nodes VA, VB and VC shown in
When the selection transistors M901 through M912 are of the same size, they have the same on-resistance, so that the same voltage is applied to the resistor R and the selection transistors M901 through M912. For this reason, currents obtained by equally shunting the current IREF under no influence of the on-resistance will be current segments, namely the currents I1 through I4. When the digital codes B9=1, B8=0, B7=1 are inputted, the selection transistors M901, M902, M907, and M912 are set to an on-state, so that the currents I1+I2, I3, and I4 are outputted to the nodes VA, VB, and VC, respectively. Since the node VC is connected to the output terminal of the voltage follower, it does not contribute to the D/A converted output current.
The D/A converter block 320 shown in
As with the first embodiment, this embodiment can achieve the D/A converted output current with the excellent differential linearity regardless of the presence of the potential variation of the currents I1 through I4 due to the manufacturing variability.
This third embodiment is characterized by using a D/A converter block 420 by the shunt currents shown in
A configuration of the decoder 430C is shown in
According to the first and second embodiments, in order improve the differential linearity errors at three points corresponding to the upper 2 bits that cause an issue in the characteristic graph shown in
In order to eliminate the differential linearity error, which still slightly occurs, however, the configuration according to the third embodiment may be advantageously used. All the resistors R1 through R256 shown in
This fourth embodiment is characterized by using a D/A converter block 520 by the shunt currents shown in
The nodes VA and VC shown in
The embodiment shown in
Symbol 610 represents a D/A converter block for D/A converting the upper 4 bits by the current segment manner. Symbol 620 represents a D/A converter block for D/A converting the intermediate 4 bits by the current segment manner using the shunt currents. Symbol 630 represents a D/A converter block for D/A converting the lower 8 bits using the currents shunt by the R-2R resistors.
A decoder 640A is the decoder shown in
The D/A converter block 610 D/A converts the upper 4 bits in the first step using the current segments (11 through 116), where a current IREFIN′, one of the output currents from the D/A converter block 610, is inputted to the current IREF in
When the 16-bit D/A converter shown in the fifth embodiment is applied to the first or second embodiment, the number of bits to be converted in the first step D/A conversion will be 8 bits. In this case, the current segments in the first step will be 28=256 in total.
In the fifth embodiment, however, the D/A conversion in the first and second steps can be performed using the current segments totaling 24+24=32 in the first and the second D/A converting portions, a potential effect for reducing an increase in pattern layout area may be expected.
Moreover, when the steps is further increased to more than three, it is preferred to add the D/A converter block 620 shown in
The D/A converter according to the present invention may be used for a comparison type D/A converter. Furthermore, a signal converter may also be configured using the comparison type D/A converter composed of the D/A converter according to the present invention.
The present invention relates to the signal converter of driving the laser diode with the current. The signal converter includes the D/A and A/D converters, and that the differential linearity error of he D/A converter being used for it is small is required for setting the stable laser output. In the high-resolution D/A converter, the differential linearity tends to deteriorate due to the manufacturing variability. Implementation of the present invention may prevent the differential linearity error to occur, contributing to an improvement in manufacturing yield. Moreover, the present invention can be widely utilized for the current output type D/A converter.
Ohmi, Kazuyuki, Tatehara, Kenichi
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