A reverse current is prevented in a charge pump circuit. A complementary pair of clocks CLK and *CLK varies while a first through a fourth charge transfer MOS transistors M11, M12, M13 and M14 are turned off. Then the second charge transfer MOS transistor M12 is turned on to discharge a first pumping capacitor CA and the third charge transfer MOS transistor M13 is turned on to charge a second pumping capacitor CB. Next, the complementary pair of clocks CLK and *CLK varies after the first through the fourth charge transfer MOS transistors M11, M12, M13 and M14 are turned off again. Then the fourth charge transfer MOS transistor M14 is turned on to discharge the second pumping capacitor CB and the first charge transfer MOS transistor M11 is turned on to charge the first pumping capacitor CA.
|
1. A charge pump circuit comprising:
a first switching element for charge transfer and a second switching element for charge transfer that are connected in series;
a first capacitor comprising a first terminal and a second terminal, the first terminal of the first capacitor being connected to a connecting point between the first switching element for charge transfer and the second switching element for charge transfer;
a third switching element for charge transfer and a fourth switching element for charge transfer that are connected in series;
a second capacitor comprising a first terminal and a second terminal, the first terminal of the second capacitor being connected to a connecting point between the third switching element for charge transfer and the fourth switching element for charge transfer;
a clock driver for a pair of complementary clocks that alternate between a first voltage level and a second voltage level, the clock driver providing the second terminal of the first capacitor with one of the complementary clocks and providing the second terminal of the second capacitor with another of the complementary clocks;
an input terminal connected to the first switching element for charge transfer and the third switching elements for charge transfer;
a power supply providing the input terminal with an input voltage; and
a control circuit that turns on the second switching element and the third switching element after changing corresponding voltage levels of the complementary clocks while the first switching element, the second switching element, the third switching element and the fourth switching element are turned off, and turns on the first switching element and the fourth switching element after changing corresponding voltage levels of the complementary clocks while the first switching element, the second switching element, the third switching element and the fourth switching element are turned off.
2. The charge pump circuit of
3. The charge pump circuit of
4. The charge pump circuit of
5. The charge pump circuit of
6. The charge pump circuit of
7. The charge pump circuit of
8. The charge pump circuit of
9. The charge pump circuit of
|
This invention is based on Japanese Patent Application No. 2004-092639, the content of which is incorporated herein by reference in its entirety.
1. Field of the Invention
This invention relates to a charge pump circuit.
2. Description of the Related Art
Systems in which an EEPROM (Electrically Erasable Programmable Read Only Memory) or a flash memory is programmed and erased and systems in which an LCD (Liquid Crystal Display) or an analog switch is driven require a voltage higher than a power supply voltage Vdd.
Embedded charge pump circuits are commonly used in such systems. The charge pump circuit is a simple circuit that is capable of boosting a voltage using a single power supply in the system so that a voltage higher than the power supply voltage is provided.
In a common charge pump circuit, charge transfer MOS transistors are connected in series to form multiple stages of pumping packets so that an input voltage is boosted. Assuming the input voltage is Vdd and a threshold voltage of a transistor is Vd, the boosted voltage Vout of an N-stage charge pump circuit is expressed by an equation below.
Vout=(N+1)(Vdd−Vd)
Further details may be found in Japanese Patent Publication No. 2001-211637, and in “On-chip High-Voltage Generation in NMOS Integrated Circuits Using an Improved Voltage Multiplier Technique,” IEEE Journal of Solid-State Circuit, SC-11, No. 3, pp. 374–378, June 1976.
This invention is directed to offer a charge pump circuit suitable for a field of application that requires low current and low power consumption, such as a power supply circuit for a condenser microphone. More specifically, this invention is directed to prevent a voltage loss due to a reverse current in a charge transfer MOS transistor used in the charge pump circuit.
The charge pump circuit according to this invention includes a first switching element for charge transfer and a second switching element for charge transfer that are connected in series, and a first capacitor having a first terminal and a second terminal. The first terminal of the first capacitor is connected to a connecting point between the first switching element for charge transfer and the second switching element for charge transfer. The circuit also includes a third switching element for charge transfer and a fourth switching element for charge transfer that are connected in series, and a second capacitor having a first terminal and a second terminal. The first terminal of the second capacitor is connected to a connecting point between the third switching element for charge transfer and the fourth switching element for charge transfer. The circuit further includes a clock driver for a pair of complementary clocks that alternate between a first voltage level and a second voltage level. The clock driver provides the second terminal of the first capacitor with one of the complementary clocks and the second terminal of the second capacitor with another of the complementary clocks. The circuit includes an input terminal connected to the first switching element for charge transfer and the third switching element for charge transfer, a power supply providing the input terminal with an input voltage, and a control circuit that turns on the second switching element and the third switching element after changing corresponding voltage levels of the complementary clocks while the first switching element, the second switching element, the third switching element and the fourth switching element are turned off, and turns on the first switching element and the fourth switching element after changing corresponding voltage levels of the complementary clocks while the first switching element, the second switching element, the third switching element and the fourth switching element are turned off.
Next, a charge pump circuit according to an embodiment of this invention will be explained referring to figures.
Next, a circuit constituting the doubler (1)–the doubler (N) shown in
A third and a fourth charge transfer MOS transistors M3 and M4 are connected in series. One end of a second pumping capacitor C2 is connected to a connecting point between the charge transfer MOS transistors M3 and M4. A reverse clock *CLK from the clock driver (not shown) is applied to another end of the pumping capacitor C2. The input voltage Vin from the input terminal Pin is applied to a source of the third charge transfer MOS transistor M3. A source of the fourth charge transfer MOS transistor M4 is connected to the output terminal Pout.
A smoothing capacitor Cout is also connected to the output terminal Pout. The first and the third charge transfer MOS transistors M1 and M3 are N-channel type, while the second and the fourth charge transfer MOS transistors M2 and M4 are P-channel type. It is assumed that a power supply voltage is Vdd and that amplitude of the clock CLK and the reverse clock *CLK is also Vdd.
The charge pump circuit operates as described below. During a period in which the clock CLK is “high”, M2 and M3 are turned on and M1 and M4 are turned off. Thus the first pumping capacitor C1 is discharged while the second pumping capacitor C2 is charged. A discharging current from the first pumping capacitor C1 flows through M2 and an output voltage Vout=Vin+Vdd is obtained. During a period in which the clock CLK is “low”, on the other hand, M1 and M4 are turned on and M2 and M3 are turned off. Thus the second pumping capacitor C2 is discharged while the first pumping capacitor C1 is charged. A discharging current from the second pumping capacitor C2 flows through M4 and the output voltage Vout=Vin+Vdd is obtained. Voltage boosting is performed efficiently since the discharging current flows over a whole period of a clock cycle through either M2 or M4.
However, because the charge transfer MOS transistors turn on and off simultaneously in this charge pump circuit, there arise reverse currents I1 and I2 flowing during the switching of the charge transfer MOS transistors and causing a voltage loss ΔV in the charge pump circuit. That is, the output voltage Vout comes to be Vout=Vin+Vdd−ΔV.
For example, when the clock CLK varies from “high” to “low”, M2 switches from on to off while M1 switches from off to on. However, it is unavoidable that there arises a transient period during which both M1 and M2 turn on, since the MOS transistors need a certain amount of time for switching. The reverse current I1 flows from the output terminal Pout where the boosted voltage is generated to the input terminal Pin through M2 and M1 during the period both M1 and M2 are turned on. Similarly when the clock CLK varies from “low” to “high”, the reverse current I2 flows from the output terminal Pout to the input terminal Pin through M4 and M3.
A charge pump circuit that prevents such reverse currents will be described hereafter.
A third and a fourth charge transfer MOS transistors M13 and M14 are connected in series. One end of a second pumping capacitor CB is connected to a connecting point between the charge transfer MOS transistors M13 and M14. A reverse clock *CLK (an inversion of the clock CLK) from the clock driver (not shown) is applied to another end of the pumping capacitor CB. The input voltage Vin from the input terminal Pin is applied to a source of the third charge transfer MOS transistor M13. A source of the fourth charge transfer MOS transistor M14 is connected to the output terminal Pout.
A smoothing capacitor Cout is also connected to the output terminal Pout. The first and the third charge transfer MOS transistors M11 and M13 are N-channel type, while the second and the fourth charge transfer MOS transistors M12 and M14 are P-channel type.
A first clock CLK(B) is provided to a gate of the first charge transfer MOS transistor M11 through a first coupling capacitor C11. A first biasing MOS transistor M15 is connected between the input terminal Pin and the gate of the first charge transfer MOS transistor M11. A third clock CLK(C) is provided to a gate of the third charge transfer MOS transistor M13 through a third coupling capacitor C13.
A third biasing MOS transistor M17 is connected between the input terminal Pin and the gate of the third charge transfer MOS transistor M13. A gate of the first biasing MOS transistor M15 and the gate of the third charge transfer MOS transistor M13 are connected with each other. And a gate of the third biasing MOS transistor M17 and the gate of the first charge transfer MOS transistor M11 are connected with each other.
Similarly, a second clock CLK(A) is provided to a gate of the second charge transfer MOS transistor M12 through a second coupling capacitor C12. A second biasing MOS transistor M16 is connected between the output terminal Pout and the gate of the second charge transfer MOS transistor M12. A fourth clock CLK(D) is provided to a gate of the fourth charge transfer MOS transistor M14 through a fourth coupling capacitor C14. A fourth biasing MOS transistor M18 is connected between the output terminal Pout and the gate of the fourth charge transfer MOS transistor M14.
A gate of the second biasing MOS transistor M16 and the gate of the fourth charge transfer MOS transistor M14 are connected with each other. And a gate of the fourth biasing MOS transistor M18 and the gate of the second charge transfer MOS transistor M12 are connected with each other.
Furthermore, a first initial voltage setting diode D1 is connected between the gate of the first charge transfer MOS transistor M11 and the output terminal Pout. That is, an anode of the first initial voltage setting diode D1 is connected to the gate of the first charge transfer MOS transistor M11 and a cathode of the first initial voltage setting diode D1 is connected to the output terminal Pout. Similarly, a third initial voltage setting diode D3 is connected between the gate of the third charge transfer MOS transistor M13 and the output terminal Pout.
That is, an anode of the third initial voltage setting diode D3 is connected to the gate of the third charge transfer MOS transistor M13 and a cathode of the third initial voltage setting diode D3 is connected to the output terminal Pout.
And a second initial voltage setting diode D2 is connected between the gate of the second charge transfer MOS transistor M12 and the input terminal Pin. That is, a cathode of the second initial voltage setting diode D2 is connected to the gate of the second charge transfer MOS transistor M12 and an anode of the second initial voltage setting diode D2 is connected to the input terminal Pin. Similarly, a fourth initial voltage setting diode D4 is connected between the gate of the fourth charge transfer MOS transistor M14 and the input terminal Pin.
That is, a cathode of the fourth initial voltage setting diode D4 is connected to the gate of the fourth charge transfer MOS transistor M14 and an anode of the fourth initial voltage setting diode D4 is connected to the input terminal Pin.
Operation of the charge pump circuit of
In the operation of the charge pump circuit, it is important that the clock CLK and the reverse clock *CLK from the clock driver are turned from “low” to “high” or from “high” to “low” while all the charge transfer MOS transistors M11, M12, M13 and M14 are turned off, and then the second charge transfer MOS transistor M12 is turned on to discharge the first pumping capacitor CA and the third charge transfer MOS transistor M13 is turned on to charge the second pumping capacitor CB, as shown in
Next, the clock CLK and the reverse clock *CLK from the clock driver are turned from “high” to “low” or from “low” to “high” after all the charge transfer MOS transistors M11, M12, M13 and M14 are turned off again, and then the fourth charge transfer MOS transistor M14 is turned on to discharge the second pumping capacitor CB and the first charge transfer MOS transistor M11 is turned on to charge the first pumping capacitor CA, as shown in
By doing so, a reverse current is completely prevented, since simultaneous turning-on of the first charge transfer MOS transistor M11 and the second charge transfer MOS transistor M12 does not take place and simultaneous turning-on of the third charge transfer MOS transistor M13 and the fourth charge transfer MOS transistor M14 does not take place as well.
Next, the operation of the charge pump circuit will be explained in detail. The first charge transfer MOS transistor M11, the second charge transfer MOS transistor M12, the third charge transfer MOS transistor M13 and the fourth charge transfer MOS transistor M14 are simply referred to as M11, M12, M13 and M14, respectively, while the first biasing MOS transistor M15, the second biasing MOS transistor M16, the third biasing MOS transistor M17 and the fourth biasing MOS transistor M18 are simply referred to as M15, M16, M17 and M18, respectively, in the following explanation.
It is assumed that the power supply voltage of the clock driver is Vdd, the high level is Vdd and the low level is Vss (ground voltage) for the clock CLK and the reverse clock *CLK. Also, it is assumed that the high level is Vdd and the low level is Vss for the first clock CLK(B), the second clock CLK(A), the third clock CLK(C) and the fourth clock CLK(D). And the input voltage Vin is applied to the input terminal Pin.
First, the clock CLK is turned from “low” to “high” and the reverse clock *CLK is turned from “high” to “low” while all of M11, M12, M13 and M14 are turned off. As a result, a voltage at the connecting node between M11 and M12 varies from Vin to Vin+Vdd while a voltage at the connecting node between M13 and M14 varies from Vin+Vdd to Vin.
Next, the second clock CLK(A) is turned from “high” to “low” while the third clock CLK(C) is turned from “low” to “high” at the same time. Thereupon the charge pump circuit is in the state A shown in
When the second clock CLK(A) is turned from “high” to “low”, a voltage at the gate of M12 and a voltage at the gate of M18 become Vin to turn M12 and M18 on. Electric charge in the first pumping capacitor CA is discharged to the output terminal Pout by the turning-on of M12. An output voltage Vout=Vin+Vdd is obtained at the output terminal Pout thereupon. And M14 is turned off because a voltage at the gate of M14 becomes the same voltage Vin+Vdd as the output voltage Vout by the turning-on of M18.
When the third clock CLK(C) is turned from “low” to “high”, on the other hand, a voltage at the gate of M13 and a voltage at the gate of M15 become Vin+Vdd to turn M13 and M15 on. The second pumping capacitor CB is charged by the turning-on of M13. And M11 is turned off because a voltage at the gate of M11 becomes Vin by the turning-on of M15.
Next, after all of M11, M12, M13 and M14 are turned off again, the clock CLK is turned from “high” to “low” and the reverse clock *CLK is turned from “low” to “high”. As a result, the voltage at the connecting node between M11 and M12 varies from Vin+Vdd to Vin while the voltage at the connecting node between M13 and M14 varies from Vin to Vin+Vdd.
Then the first clock CLK(B) is turned from “low” to “high” while the fourth clock CLK(D) is turned from “high” to “low” at the same time. Thereupon the charge pump circuit is in the state B shown in
When the first clock CLK(B) is turned from “low” to “high”, the voltage at the gate of M11 and a voltage at the gate of M17 become Vin+Vdd to turn M11 and M17 on. The first pumping capacitor CA is charged by the turning-on of M11. And M13 is turned off because the voltage at the gate of M13 becomes Vin by the turning-on of M17.
When the fourth clock CLK(D) is turned from “high” to “low”, on the other hand, the voltage at the gate of M14 and a voltage at the gate of M16 become Vin to turn M14 and M16 on. Electric charge in the second pumping capacitor CB is discharged to the output terminal Pout by the turning-on of M14. An output voltage Vout=Vin+Vdd is obtained at the output terminal Pout thereupon. And M12 is turned off because the voltage at the gate of M12 becomes the same voltage Vin+Vdd as the output voltage Vout by the turning-on of M16.
Next, operation of the first through the fourth initial voltage setting diodes D1, D2, D3 and D4 will be explained hereafter, referring to
Suppose the initial voltage at the node A is higher than Vout+Vtn. Then the voltage at the gate of M15 is also higher than Vout+Vtn, which keeps M15 turned on. Also, since the voltage at the node A′ is kept at Vin, the voltage at the gate of M17 remains at Vin, which keeps M17 turned off. Therefore, the first and the third initial voltage setting diodes D1 and D3 are provided so that a forward current of the diode flows to reduce the voltage at the node A or A′ when the voltage at the node A or A′ is higher than Vout.
The second and the fourth initial voltage setting diodes D2 and D4 are added to secure the operation of the circuit under an extraordinary initial condition that an initial voltage at a node B or an initial voltage at a node B′ in
Also M16 is always turned off, since the voltage at the node B′ is kept at Vout and thus the voltage at the gate of M16 remains at Vout. Therefore, the second and the fourth initial voltage setting diodes D2 and D4 are provided so that a forward current of the diode flows to increase the voltage at the node B or B′ when the voltage at the node B or B′ is lower than Vin.
The charge pump circuit according to the embodiment of this invention can prevent the reverse current in the charge transfer MOS transistor and the resultant voltage loss.
Suzuki, Tatsuya, Kaneda, Yasuhiro
Patent | Priority | Assignee | Title |
11611276, | Dec 04 2014 | Taiwan Semiconductor Manufacturing Company, Ltd | Charge pump circuit |
7595683, | Nov 15 2007 | Semiconductor Components Industries, LLC | Low-input-voltage charge pump |
7675349, | Mar 27 2007 | JAPAN DISPLAY WEST INC | Power supply circuit and display device therewith |
7969235, | Jun 09 2008 | SanDisk Technologies LLC | Self-adaptive multi-stage charge pump |
7973592, | Jul 21 2009 | SanDisk Technologies LLC | Charge pump with current based regulation |
8044705, | Aug 28 2007 | SanDisk Technologies LLC | Bottom plate regulation of charge pumps |
8076968, | Mar 09 2009 | Semiconductor Components Industries, LLC | Low-input-voltage charge pump |
8154333, | Apr 01 2009 | Taiwan Semiconductor Manufacturing Company, Ltd. | Charge pump circuits, systems, and operational methods thereof |
8294509, | Dec 20 2010 | SanDisk Technologies LLC | Charge pump systems with reduction in inefficiencies due to charge sharing between capacitances |
8339183, | Jul 24 2009 | SanDisk Technologies LLC | Charge pump with reduced energy consumption through charge sharing and clock boosting suitable for high voltage word line in flash memories |
8339185, | Dec 20 2010 | SanDisk Technologies LLC | Charge pump system that dynamically selects number of active stages |
8378737, | Apr 01 2009 | Taiwan Semiconductor Manufacturing Company, Ltd. | Charge pump circuits, systems, and operational methods thereof |
8400212, | Sep 22 2011 | SanDisk Technologies LLC | High voltage charge pump regulation system with fine step adjustment |
8421524, | Dec 20 2010 | SanDisk Technologies LLC | Charge pump systems with reduction in inefficiencies due to charge sharing between capacitances |
8514628, | Sep 22 2011 | SanDisk Technologies LLC | Dynamic switching approach to reduce area and power consumption of high voltage charge pumps |
8699247, | Sep 09 2011 | SanDisk Technologies LLC | Charge pump system dynamically reconfigurable for read and program |
8710907, | Jun 24 2008 | SanDisk Technologies LLC | Clock generator circuit for a charge pump |
8710909, | Sep 14 2012 | SanDisk Technologies LLC | Circuits for prevention of reverse leakage in Vth-cancellation charge pumps |
8836412, | Feb 11 2013 | SanDisk Technologies LLC | Charge pump with a power-controlled clock buffer to reduce power consumption and output voltage ripple |
8860501, | Feb 11 2013 | SanDisk Technologies LLC | Charge pump with a power-controlled clock buffer to reduce power consumption and output voltage ripple |
8981835, | Jun 18 2013 | SanDisk Technologies LLC | Efficient voltage doubler |
9007046, | Jun 27 2013 | SanDisk Technologies LLC | Efficient high voltage bias regulation circuit |
9024680, | Jun 24 2013 | SanDisk Technologies LLC | Efficiency for charge pumps with low supply voltages |
9077238, | Jun 25 2013 | SanDisk Technologies LLC | Capacitive regulation of charge pumps without refresh operation interruption |
9083231, | Sep 30 2013 | SanDisk Technologies LLC | Amplitude modulation for pass gate to improve charge pump efficiency |
9154027, | Dec 09 2013 | SanDisk Technologies LLC | Dynamic load matching charge pump for reduced current consumption |
9385596, | Jan 07 2015 | eMemory Technology Inc. | Charge pump circuit capable of reducing reverse currents |
9520776, | Sep 18 2015 | SanDisk Technologies LLC | Selective body bias for charge pump transfer switches |
9531262, | Jan 03 2014 | Analog Devices International Unlimited Company | Charge pump |
9602921, | Jun 24 2015 | Robert Bosch GmbH | Independently charge pumps for differential microphone |
9647536, | Jul 28 2015 | SanDisk Technologies LLC | High voltage generation using low voltage devices |
9917507, | May 28 2015 | SanDisk Technologies LLC | Dynamic clock period modulation scheme for variable charge pump load currents |
9923459, | Oct 23 2014 | Infineon Technologies AG | Charge pump |
RE46263, | Dec 20 2010 | SanDisk Technologies LLC | Charge pump system that dynamically selects number of active stages |
Patent | Priority | Assignee | Title |
6429723, | Nov 18 1999 | Texas Instruments Incorporated | Integrated circuit with charge pump and method |
7046076, | Dec 19 2003 | Atmel Corporation | High efficiency, low cost, charge pump circuit |
JP2001211637, |
Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
Mar 25 2005 | Sanyo Electric Co., Ltd. | (assignment on the face of the patent) | / | |||
May 30 2005 | SUZUKI, TATSUYA | SANYO ELECTRIC CO , LTD | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 016685 | /0293 | |
May 30 2005 | KANEDA, YASUHIRO | SANYO ELECTRIC CO , LTD | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 016685 | /0293 | |
Jan 01 2011 | SANYO ELECTRIC CO , LTD | Semiconductor Components Industries, LLC | CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT #12 577882 PREVIOUSLY RECORDED ON REEL 026594 FRAME 0385 ASSIGNOR S HEREBY CONFIRMS THE ASSIGNMENT | 032836 | /0342 | |
Jan 01 2011 | SANYO ELECTRIC CO , LTD | Semiconductor Components Industries, LLC | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 026594 | /0385 | |
Apr 15 2016 | Semiconductor Components Industries, LLC | DEUTSCHE BANK AG NEW YORK BRANCH | SECURITY INTEREST SEE DOCUMENT FOR DETAILS | 038620 | /0087 | |
Apr 15 2016 | Semiconductor Components Industries, LLC | DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT | CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087 ASSIGNOR S HEREBY CONFIRMS THE SECURITY INTEREST | 039853 | /0001 | |
Jun 22 2023 | DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT | Semiconductor Components Industries, LLC | RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 | 064070 | /0001 | |
Jun 22 2023 | DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT | Fairchild Semiconductor Corporation | RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 | 064070 | /0001 |
Date | Maintenance Fee Events |
Sep 22 2010 | M1551: Payment of Maintenance Fee, 4th Year, Large Entity. |
Aug 05 2011 | ASPN: Payor Number Assigned. |
Sep 24 2014 | M1552: Payment of Maintenance Fee, 8th Year, Large Entity. |
Sep 21 2018 | M1553: Payment of Maintenance Fee, 12th Year, Large Entity. |
Date | Maintenance Schedule |
Apr 24 2010 | 4 years fee payment window open |
Oct 24 2010 | 6 months grace period start (w surcharge) |
Apr 24 2011 | patent expiry (for year 4) |
Apr 24 2013 | 2 years to revive unintentionally abandoned end. (for year 4) |
Apr 24 2014 | 8 years fee payment window open |
Oct 24 2014 | 6 months grace period start (w surcharge) |
Apr 24 2015 | patent expiry (for year 8) |
Apr 24 2017 | 2 years to revive unintentionally abandoned end. (for year 8) |
Apr 24 2018 | 12 years fee payment window open |
Oct 24 2018 | 6 months grace period start (w surcharge) |
Apr 24 2019 | patent expiry (for year 12) |
Apr 24 2021 | 2 years to revive unintentionally abandoned end. (for year 12) |