A semiconductor device (102) that includes a drain extended pmos transistor (CT1a) is provided, as well as fabrication methods (202) therefore. In forming the pmos transistor, a drain (124) of the transistor is formed over a region (125) of a p-type upper epitaxial layer (106), where the region (125) of the p-type upper epitaxial layer (106) is sandwiched between a left p-WELL region (130a) and a right p-WELL region (130b) formed within the p-type upper epitaxial layer (106). The p-type upper epitaxial layer (106) is formed over a semiconductor body (104) that has an n-buried layer (108) formed therein. This arrangement serves to increase the breakdown voltage (BVdss) of the drain extended pmos transistor.
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6. A semiconductor device, comprising:
a semiconductor body including a p-type upper epitaxial layer;
an n-buried layer formed under the p-type upper epitaxial layer in the semiconductor body; and
a drain-extended pmos transistor formed over the p-type upper epitaxial layer, where a p-type drain region of the pmos transistor is formed in a region of the p-type upper epitaxial layer that is sandwiched between a left p-WELL region and a right p-WELL region formed within the p-type upper epitaxial layer.
16. A method of fabricating a semiconductor device, the method comprising:
providing a semiconductor body;
forming an n-buried layer in the semiconductor body;
forming a p-type upper epitaxial layer over the semiconductor body; and
forming a drain-extended pmos transistor over the semiconductor body, where a drain of the pmos transistor is formed in a region of the p-type upper epitaxial layer that is sandwiched between a left p-WELL region and a right p-WELL region formed within the p-type upper epitaxial layer.
1. A drain extended pmos transistor, comprising:
a gate overlying a channel region formed within a semiconductor substrate;
a p-type source region formed within the semiconductor substrate to the left of the channel region; and
a p-type drain region formed within the semiconductor substrate to the right of the channel region, where the p-type drain region is formed over a region of the semiconductor substrate that is sandwiched between a left p-WELL region and a right p-WELL region formed within the semiconductor substrate, wherein a left n-WELL region, the p-type source region, the p-type drain region, the left p-WELL region and the right p-WELL region are formed within a p-type upper epitaxial layer formed on the semiconductor substrate.
14. A method of fabricating a drain-extended MOS transistor, the method comprising:
providing a p-type semiconductor body;
forming an n-buried layer in the semiconductor body;
forming a p-type upper epitaxial layer over the semiconductor body;
forming a left n-WELL region in the p-type upper epitaxial layer;
forming a split p-WELL region in the p-type upper epitaxial layer;
forming a gate over the p-type upper epitaxial layer;
forming a p-type source region in the left n-WELL region adjacent to a left side of the gate; and
forming a p-type drain region in the p-type upper epitaxial layer between a left p-WELL region and a right p-WELL region of the split PWELL region in the p-type upper epitaxial layer and to a right side of the gate.
2. The transistor of
3. The transistor of
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5. The transistor of
7. The device of
8. The device of
9. The device of
10. The device of
11. The device of
12. The device of
13. The device of
15. The method of
17. The method of
forming a p-type source region of the pmos transistor in a left n-WELL region formed within the p-type upper epitaxial layer.
18. The method of
19. The method of
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The present invention relates generally to semiconductor devices, and more particularly to a drain extended PMOS transistor having a split drain implant that facilitates an increased breakdown voltage.
Power semiconductor products are often fabricated using N or P channel drain-extended metal-oxide-semiconductor (DEMOS) transistor devices for high power switching applications. DEMOS devices advantageously combine short-channel operation with high current handling capabilities, relatively low drain-to-source on-state resistance (Rdson), and the ability to withstand high blocking voltages without suffering voltage breakdown failure (high breakdown voltage ratings). Breakdown voltage is typically measured as drain-to-source breakdown voltage with the gate and source shorted together (BVdss), where DEMOS device designs often involve a tradeoff between breakdown voltage BVdss and Rdson.
Referring to
A p-type source (S) 22 is formed in the N-WELL 12 along one side of a channel region 28 of the N-WELL 12, and an n-type backgate (BG) 26, in the illustrated example, is spaced from the source 22 in the N-WELL 12. A p-type extended drain (D) 24 is formed in the drift region 6a, and is spaced from the other side of the channel 28. The transistor gate structure (G) includes a thin gate dielectric or gate oxide 14 formed over the channel region 28 of the N-WELL 12, which also partially overlies a portion of the p-drift region 6a, with a conductive gate electrode 16 formed over the thin gate oxide 14 and sidewall spacers 20 formed along the lateral sides of the gate (G).
A supply voltage VCC is coupled to the drain D2 of the high-side driver T2, and can be a positive terminal of a battery source, wherein the ground may be the battery negative terminal, for example, in automotive applications. The low-side driver T1 and the high-side driver T2 are coupled in series between the supply voltage VCC and ground, where the high side driver transistor T2 has a drain D2 coupled to VCC and a source S2 coupled with the intermediate node N1 at the load. The low-side transistor T1 has a drain D1 coupled to the node N1 and a source S1 coupled to ground. The intermediate node N1 between the transistors T1 and T2 is coupled to a first terminal of a load and the other load terminal is coupled to ground, wherein the load is typically not a part of the device 2. The low and high side transistor gates G1 and G2 are controlled so as to drive the load in alternating fashion, wherein an inverter CT1, CT2 (including the DEPMOS transistor CT1 of
In the illustrated device 2, the source S of the DEPMOS control transistor CT1 is coupled to a high voltage VCC+VGS, where VGS is the gate-to-source voltage required to turn the high-side device T2 on, and VCC is the supply voltage. In this configuration, the upper control transistor CT1 must be designed to withstand high drain-to-source voltages without breakdown when the upper control transistor CT1 is off and the lower control transistor CT2 is on. In this condition, the drain D of the transistor CT1 is essentially at ground potential, while the source S remains at VCC+VGS. In automotive and other applications in which bridge driver circuits are used for high wattage digital audio equipment or in other high power circuits, the supply voltage VCC can be very high, such as 65 to 80 volts DC, wherein the driver devices T1 and T2 need to withstand drain-to-source voltages of about VCC without breakdown. Furthermore, the DEPMOS control transistor CT1 needs to withstand even higher drain-to-source voltages, since the drain D of the upper control transistor CT1 may be near ground potential when the lower control transistor CT2 is on. In particular, the VGS of the high-side driver transistor T2 may be 5 to 15 volts DC, wherein the off-state drain-to-source voltage across the DEPMOS transistor CT1 may be 100 volts or more.
As shown in
Another breakdown voltage limitation of the transistor CT1 relates to the thickness of the epitaxial silicon 6 in the device 2, wherein the substrate 4 is grounded and the transistor source, drain, and channel (e.g., including the N-WELL 12 and the p-drift region 6a) are formed in the epitaxial silicon 6. In particular, when the control transistor CT1 is on, the drain voltage is very high, and it is desirable to separate the p-type drain 24 and the drift region 6a from the underlying p-type substrate 4 that is grounded, to prevent punch-thru current between the drain 24 and the substrate 4. Accordingly, a rather heavily doped n-buried layer 8 is typically formed prior to forming the upper epitaxial silicon layer 6, in order to separate the drift region 6a and the drain 24 from the substrate 4, and to thereby inhibit on-state punch-thru current, with the n-buried layer 8 typically being connected to the n-type backgate 26 through the N-WELL 12, whereby the n-buried layer 8 is tied to the source voltage (VCC+VGS). However, the presence of the n-buried later at such a high voltage may lead to off-state breakdown when the drain 24 is near ground potential. Thus, while the n-buried layer 8 operates to prevent on-state punch-thru current, the n-buried layer 8 limits the off-state breakdown voltage rating of the DEPMOS transistor CT1 for a given epitaxial thickness and drift region doping amount.
In an “off” state of the transistor CT1, the drain 24 is essentially at ground, and the source voltage VCC+VGS is dropped across the drift region 6a portion extending between the bottom of the drain 24 and the n-buried layer 8, and also between the channel-side of the drift region 6a and the drain 24. If the breakdown occurs on the surface between the gate 16 and the p-type drain 24, the lateral extension of the drift region 6a can be increased (e.g., the lateral spacing of the drain 24 from the gate 16 may be increased to prevent lateral breakdown). However, the vertical spacing between the bottom of the p-type drain 24 and the n-buried layer 8 is more difficult to increase. One approach is to increase the thickness of the epitaxial silicon layer 6, wherein a thicker layer 6 allows a deeper drift region 6a to support higher voltages without suffering breakdown. However, increasing the epitaxial thickness is costly in terms of process complexity, larger spacing requirements, and larger design rules, particularly in forming the deep diffusions to connect to the n-buried layer 8 or other buried layers in the device 2. Accordingly, there is a need for improved DEPMOS devices and fabrication methods by which increased voltage breakdown withstanding capabilities can be achieved, without increasing epitaxial silicon thicknesses and without sacrificing device performance.
The following presents a simplified summary in order to provide a basic understanding of one or more aspects of the invention. This summary is not an extensive overview of the invention, and is neither intended to identify key or critical elements of the invention, nor to delineate the scope thereof. Rather, the primary purpose of the summary is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later. The present invention relates to an improved drain extended PMOS (DEPMOS) transistor that has an increased breakdown voltage.
According to one or more aspects of the present invention, a method of fabricating a drain-extended MOS transistor is disclosed. The method includes providing a p-type semiconductor body, forming an n-buried layer in the semiconductor body and forming a p-type upper epitaxial layer over the semiconductor body. A left N-WELL region is then formed in the p-type upper epitaxial layer, followed by a split P-WELL region which is also formed in the p-type upper epitaxial layer. A gate is then formed over the p-type upper epitaxial layer, and a p-type source region is formed in the left N-WELL region adjacent to a left side of the gate. Subsequently, a p-type drain region is formed in the p-type upper epitaxial layer between a left P-WELL region and a right P-WELL region of the split PWELL region in the p-type upper epitaxial layer. The p-type drain region is formed to a right side of the gate.
The following description and annexed drawings set forth in detail certain illustrative aspects and implementations of the invention. These are indicative of but a few of the various ways in which principles of the invention may be employed.
One or more implementations of the present invention will now be described with reference to the attached drawings, wherein like reference numerals are used to refer to like elements throughout, and wherein the illustrated structures are not necessarily drawn to scale. The invention provides drain extended PMOS (DEPMOS) transistors and associated fabrication techniques by which various shortcomings of conventional DEPMOS transistors can be mitigated or overcome, and which may be employed to facilitate increased breakdown voltage ratings without increased epitaxial silicon thicknesses.
Referring now to
An n-buried layer 108 (NBL) extends into an upper portion of the lower EPI 104a and a lower portion of the upper EPI 106. In the illustrated example, left and right N-WELL regions 112a, 112b are formed in an upper portion of the upper EPI 106. Various field oxide (FOX) isolation structures 110a-110e are formed to separate different terminals of the transistor CT1a from one another and from other components in the device 102, although other isolation techniques may be used (e.g., shallow trench isolation (STI), local oxidation of silicon (LOCOS), etc.).
The exemplary DEPMOS transistor CT1a comprises a gate (G) having a thin gate dielectric 114 that underlies a conductive gate electrode 116, where the gate 114, 116 overlies a channel region 128 in the semiconductor body 104 and is abutted by a left sidewall spacer 120a along a left lateral side and a right sidewall spacer 120b along a right lateral side. A p-type source (S) 122 is formed in the semiconductor body within left N-WELL region 112a. Similarly, left and right n-type backgates (BG) 126a, 126b are formed within left and right N-WELL regions 112a, 112b, respectively. The source 122 has left and right laterally opposite sides, with the right lateral side located along a left lateral side of a channel 128 proximate the left lateral side of the gate, where the left opposite side of the source 122 is separated from the left backgate 126a by isolation structure 110b.
A split P-WELL having left and right regions 130a, 130b is also formed in an upper portion of the upper EPI 106 such that a p-type drain (D) 124 formed in the semiconductor body overlies a region 125 of upper EPI 106 that is abutted by the left and right P-WELL regions 130a, 130b. The channel region 128 underlying the gate 114, 116 is thereby established within some of the left N-WELL region 112a and some of the left split P-WELL region 130a. The p-type drain (D) 124 is spaced from the right side of the gate 114, 116 to provide an extended drain, wherein the n-buried layer 108 is situated in the upper and lower epitaxial silicon layers 106, 104a beneath at least a portion of the gate 114, 116 and the drain 124.
With regard to some of the dimensions of the features, a distance 140 between about the right side of the source 122 and about a left side of isolation structure 110c is about 0.5 um and above. A distance 142 between about the left side of isolation structure 110c and about the right side of isolation structure 110c is between about 0.5 um and about 5 um. Similarly, a distance 144 between about the left side of the isolation structure 110c and the right side of the gate structure 114, 116 is between about 0.3 um and about 2 um. A distance 146 between about the left side of isolation structure 110d and about a left side of the right N-WELL 112b is between about 0.5 um and about 5 um. Likewise, a distance 148 between about the left side of the right N-WELL 112b and about a right side of isolation structure 110d is between about 0.5 um and about 5 um. Also, a distance 150 between about a right side of the left P-WELL region 130a and about the right side of isolation structure 110c is between 0 um and about 1 um. Similarly a distance 152 between about the left side of the right P-WELL region 130b and about the left side of isolation structure 110d is between about 0 um and about 1 um. As a final example, a distance 154 between about a right side of the left N-WELL region 112a and about the left side of isolation structure 110c is between about 0.3 um and about 1.5 um. It will be appreciated that the left and right P-WELL regions 130a, 130b may diffuse laterally under the drain 124 by about distances 150 and 152 respectively as a result of annealing or heat treating, for example. In so doing, areas of the EPI region 125 corresponding to these distances 150, 152 may have a slightly increased p dopant concentration, such as between about low E16 cm2 and about mid E16 cm2, for example, where the left and right P-WELL regions 130a, 130b have a p dopant concentration of about low E16 cm2 and the upper EPI 106 has an p dopant concentration of about low E15 cm2, for example.
A transistor formed according to that which is disclosed herein has a breakdown voltage BVdss that is increased to around 40 volts as compared to a comparable conventional transistor that has a lesser breakdown voltage of around 40 volts. The breakdown voltage is increased as the left and right P-WELL regions 130a, 130b and the EPI region 125 underlying the drain 124 facilitate more evenly distributed field (lines) between the drain 124 and the NBL 108. In this manner, the transistor breakdown voltage BVdss is essentially decoupled to an extent from the epitaxial thickness, and the breakdown voltage can be increased without having to make the upper epitaxial silicon 106 thicker.
Turning to
As illustrated in
By way of example, as with all layers described herein (unless specifically indicated otherwise), n-buried layer 108 can, at least partially, be formed via lithographic techniques, where lithography generally refers to processes for transferring one or more patterns between various media. In lithography, a radiation sensitive resist coating is formed over one or more layers which are to be treated in some manner, such as to be selectively doped and/or to have a pattern transferred thereto. The resist, which is sometimes referred to as a photoresist, is itself first patterned by exposing it to radiation, where the radiation (selectively) passes through an intervening mask or template containing the pattern. As a result, the exposed or unexposed areas of the resist coating become more or less soluble, depending on the type of resist used. A developer is then used to remove the more soluble areas of the resist leaving a patterned resist. The pattered resist can then serve as a mask for the underlying layers which can be selectively treated, such as to receive dopants and/or undergo etching.
Referring to
Referring to
At 220 in
As illustrated in
Referring to
Note that although the present examples provided herein are provided in the context of a device having two EPI regions with one or more buried layers formed after the lower EPI is formed, but before the upper EPI is formed, the above structure may be formed in the starting material using high energy implants. For example, the n-buried layer can be formed with high energy implants, and such variations are contemplated as falling within the scope of the present invention.
Although the invention has been illustrated and described with respect to one or more implementations, alterations and/or modifications may be made to the illustrated examples without departing from the spirit and scope of the appended claims. In particular regard to the various functions performed by the above described components or structures (assemblies, devices, circuits, systems, etc.), the terms (including a reference to a “means”) used to describe such components are intended to correspond, unless otherwise indicated, to any component or structure which performs the specified function of the described component (e.g., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary implementations of the invention. In addition, while a particular feature of the invention may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for any given or particular application. Furthermore, to the extent that the terms “including”, “includes”, “having”, “has”, “with”, or variants thereof are used in either the detailed description and the claims, such terms are intended to be inclusive in a manner similar to the term “comprising”.
Pendharkar, Sameer, Pan, Shanjen, Todd, James R.
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