A CMOS image sensor obtains color through the use of two or three superposed layers. Each pixel in the image sensor includes a plurality of superposed photosensitive p-n junctions with individual charge integration regions. The combination of each of the superposed layers provides increased sensitivity and resolution of a single chip color imager.

Patent
   7279670
Priority
Mar 09 1999
Filed
Oct 28 2004
Issued
Oct 09 2007
Expiry
Mar 09 2020
Assg.orig
Entity
Large
0
19
all paid
1. A device, comprising:
a semiconductor substrate, with a top surface; and
a single multi-color pixel for sensing radiation of red, green, and blue wavelengths forming a corresponding single pixel of an image frame and comprising: first, second and third photoreceptor parts, located within said semiconductor substrate, said first, second and third photoreceptor parts being arranged to respectively receive said radiation of said red, green, and blue wavelengths during respective first, second, and third integration periods, said first, second and third photoreceptor parts being capable of independently beginning their respective integration periods.
15. A multi-color pixel cell, comprising:
a first photoreceptor part, sensitive primarily to a first primary color, and in a first layer of a substrate; and
a second photoreceptor part, sensitive primarily to a second primary color different than said first primary color, and located in a second layer of said substrate which is superposed relative to said first layer,
wherein said first and second photoreceptor parts have respective associated first and second individually controlled storage regions for respectively collecting charges formed in said photoreceptor parts in response to applied light during respective first and second integration periods, said first and second integration periods being based on respective saturation exposures of said first and second individually controlled storage regions.
2. A device as in claim 1, wherein said first, second and third photoreceptor parts are at different depths in the semiconductor substrate relative to said top surface.
3. A device as in claim 1, wherein said first, second and third photoreceptor parts are superposed.
4. A device as in claim 1, further comprising separate associated circuits for each of said first, second and third photoreceptor parts.
5. A device as in claim 4, wherein said associated circuits include output circuits for reading out a signal based on the charges respectively collected.
6. A device as in claim 5, wherein said associated circuits also each include a reset circuit that resets a level of an associated photoreceptor part.
7. A device as in claim 6, wherein each of said reset circuits includes its own separate reset transistor that is not part of the other reset circuits.
8. A device as in claim 1, further comprising separate reset transistors for each of said photoreceptor parts.
9. A device as in claim 1, wherein each of said first, second and third photoreceptor parts are located at least partially in a different layer of the substrate.
10. A device as in claim 9, further comprising a respective reset circuit for each of said first, second and third photoreceptor parts.
11. A device as in claim 10, wherein said reset circuits include a respective separate control line.
12. A device as in claim 1, wherein said first, second, and third integration periods are each different.
13. The device of claim 1, wherein said multi-color pixel is isolated by a field oxide region.
14. The device of claim 1, wherein said respective integration periods of said first, second, and third photoreceptor parts are based on their respective saturation exposures.
16. The pixel cell of claim 15, further comprising:
a third photoreceptor part, sensitive primarily to a third primary color which is different than said first and second primary colors, and is located in a third layer which is superposed relative to said first and second layers; and
an associated separately controlled third storage region for collecting charges formed in said third photoreceptor part.
17. The pixel cell of claim 16, further comprising an associated circuitry for each of said first, second and third photoreceptor parts.
18. The pixel cell of claim 17, wherein said associated circuitry includes separate readout circuits for each of said first, second and third storage regions.
19. The pixel cell of claim 17, wherein said associated circuitry further includes reset circuitry which includes separate reset transistors for each of said storage regions.
20. The pixel cell of claim 15, further comprising an isolation region located in the substrate on at least one side of said individually controlled storage regions.

This application is a divisional of U.S. application Ser. No. 10/254,140, filed on Sep. 24, 2002, now U.S. Pat. No. 6,870,149, which is a continuation of U.S. application Ser. No. 09/522,286, filed Mar. 9, 2000, now U.S. Pat. No. 6,455,833, which claims the benefit of the U.S. provisional application Ser. No. 60/124,084, filed Mar. 9, 1999, the disclosures of which are hereby incorporated by reference.

This invention relates to image sensors, and more particularly to active pixel sensors having superposed regions.

CMOS image sensors have a significant advantage of allowing lower power consumption. An active pixel sensor (APS) is one example of a low power consumption image sensor which has photoreceptors, and buffer circuitry, and processing circuitry, all on one substrate.

Many different things can be done using the CMOS technology. For example, many of the applications by Photobit, Inc. of Pasadena, Calif. have enabled various operations to be carried out on the same substrate as the image sensor.

Certain resolutions are desired for different operations. For example, for a still camera, one often wants very high resolution, e.g. similar to the resolution that one could get from a photograph. This could require more than 1½ megapixels. However, people are accustomed to obtaining less resolution in a video environment, which shows a progression of information, e.g., 30 to 60 frames per second.

Another consideration is the way in which one obtains color from a color sensor. Each pixel value includes an indication of values for red, green and blue at the location of that pixel. However, in actuality, the system obtains red values from one pixel area, green from another, and blue from yet another. The three values are neighboring values, so the actually-obtained information is interpolated to obtain postulated magnitudes of colors at other locations.

Another way in which this can be done is by putting small prisms at each pixel. A lot of adjustment can be required.

The present invention obtains color in a CMOS image sensor with the use of two or three superposed layers. Each pixel in the image sensor includes a plurality of superposed photosensitive p-n junctions with individual charge integration regions. The combination of each of the superposed layers provides increased sensitivity and resolution of a single chip color imager.

One aspect of the invention includes a photosensor comprising a first charge collection region having a first absorption length and a second charge collection region having a second absorption length. The first charge collection region and the second charge collection region are superposed. The photosensor further comprises a third charge collection region having a third absorption length. The third charge collection region is superposed with the first and second charge collection region.

Another aspect of the invention is a method of generating color in an active pixel sensor comprising generating light of a first color in a first charge collection region and generating light of a second color in a second charge collection region. The method further superposes the light of the first color with the light of the second color.

These and other features and advantages of the invention will become more apparent upon reading the following detailed description and upon reference to the accompanying drawings.

FIG. 1 illustrates a color sensor with three superposed charge collection regions.

FIG. 2 illustrates a pixel layout according to the present invention using a 4:2:2 sampling standard.

FIG. 3 is a cross-section and schematic diagram for three superposed p-n junction color APS according to the present invention.

During video signal processing, numerous data formats are used to represent image information associated with each pixel of a video field so that an original image can be faithfully reproduced. For example, one common color format represents a color using red, green, and blue color components. With this color format, the color of each pixel is represented by quantities of red (R), green (G) and blue (B) color components detected in the original.

FIG. 1 illustrates a color sensor 100 with three superposed charge collection regions 105. The charge collection regions 105 are superposed to provide the color sensor 100 with increased color sensitivity and resolution. The charge collection regions 105 include a first p-n junction 110, a second p-n junction 115, and a third p-n junction 120. Because the absorption length for incident photons in silicon is wavelength dependent, the charge collection regions 105 are highly sensitive to light of different color. The first p-n junction 110 is sensitive to blue light, the second p-n junction 115 is sensitive to green light, and the third p-n junction 120 is sensitive to red light. The spectral response of the charge collection regions 105 is dependent upon the thickness and location of the layers.

The superposed charge collection regions 105 may be used with a pixel having a 4:2:2 sampling mode. The 4:2:2 mode is a ratio of sampling frequencies used to digitize the luminance (Y) and color difference components (R-Y and B-Y). For example, the first color difference component may represent the difference between the red image information and the luminance image information (R-Y) and the second color difference component may represent the difference between the blue image information and the luminance image information (B-Y). The term 4:2:2 denotes that for every four samples of Y, there are 2 samples each of R-Y and B-Y, giving more chrominance bandwidth in relation to luminance compared to standard 4:1:1 sampling.

FIG. 2 illustrates a pixel 200 layout according to the present invention using a 4:2:2 sampling mode. Applying color separation in an APS through the use of superposed regions is possible through development of pinned and buried photodiodes, advances in color processing and the continuous scaling down of the CMOS features. The pixel 200 includes a green component 205, a blue component 210, and a red component 215. The combination of the color components 205, 210, 215 provides for increased color sensitivity in the pixel 200.

FIG. 3 is a cross-section and schematic diagram for three p-n junction color APS 300 according to the present invention. The APS 300 comprises a plurality of N+ floating diffusion regions 305, a plurality of P+ floating diffusion regions 310, a P- buried region 315, a N− surface region 320, a fully depleted N− well 325, NMOS reset transistors 330, 335, a PMOS reset transistor 340, a red output transistor 345, a blue output transistor 350, and a green output transistor 355. Each of the floating diffusion regions 305, 310 is connected to a reset transistor 330, 335, 340 and an output transistor 345, 350, 355. The P+ diffusion region 310 is connected to the PMOS reset transistor 340 and the N+ diffusion region 305 is connected to the NMOS reset transistor 330. The fully depleted N− well 325 overlaps the N+ diffusion region 305. The N− well 325 also surrounds the P− buried region 315 and the N− surfaced region 320. The N− surfaced region 320 is proximate the P+ diffusion region 310 and the P− buried region 315. Each of the floating diffusion regions 305, 310 preferably have different integration periods that allow each spectral selection to have flexible saturation exposure.

The color components of the pixel 300 are provided by the output transistors 345, 350, 355. In one embodiment, the output transistor 345 outputs the red component, the output transistor 350 outputs the blue component, and the output transistor 355 outputs the green component. If only two output transistors are desired, the green component may be omitted.

The color APS 300 is capable of performing 4:4:4 sampling mode. In the 4:4:4 sampling mode, there are always an equal number of samples of luminance (Y) and color difference components (R-Y and B-Y). The 4:4:4 sampling mode provides for more data to form the images, and thus the potential of images having a higher resolution and clarity. To perform 4:4:4 sampling, the color APS 300 preferably has at least two separate reset control lines. The number of reset control line is dependent upon the number of implemented superposed layers, with each layer having a separate reset control line.

Numerous variations and modifications of the invention will become readily apparent to those skilled in the art. Accordingly, the invention may be embodied in other specific forms without departing from its spirit or essential characteristics.

Berezin, Vladimir

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Executed onAssignorAssigneeConveyanceFrameReelDoc
Mar 08 2000BEREZIN, VLADIMIRPhotobit CorporationASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS 0401000773 pdf
Nov 21 2001Photobit CorporationMicron Technology, IncASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS 0401880115 pdf
Oct 28 2004Micron Technology, Inc.(assignment on the face of the patent)
Sep 26 2008Micron Technology, IncAptina Imaging CorporationASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS 0405420035 pdf
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