A 1T1R resistive memory array comprised of chains of memory cells, where each memory cell is composed of a resistive element in parallel with a switch. Such chains of memory cells are non-volatile and provide for each of the memory cells to be randomly accessed.
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1. An electronic memory comprising a plurality of memory cells, each memory cell including:
a switch;
a resistive memory element connected in parallel with said switch, said resistive memory element capable of existing in one of a plurality of resistive states, each resistive state representing a different data state; and
a memory write and read circuit selectably coupled to said resistive memory element and capable of writing a data state to said resistive memory element and reading the data state;
wherein said plurality of memory cells are arranged in a row/column configuration, each row/column configuration including a plurality of said resistive memory elements connected in series and a plurality of said switches connected in series, each of said switches associated with one of said resistive memory elements; and
said memory further comprising a source of a programming voltage and a row/column selection transistor connected between said source of the programming voltage and said row/column of memory cells.
2. The electronic memory according to
3. The electronic memory according to
4. The electronic memory according to
5. The electronic memory according to
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This application claims priority from U.S. Provisional Patent Application Ser. No. 60/567,486 filed May 3, 2004, the entire teachings of which are herein incorporated by reference.
1. Field of the Invention
The principles of the present invention are generally related to resistive memory arrays, and in particular, but not by way of limitation, to a device and method for configuring a resistive memory array, writing and reading from the resistive memory array, and producing the resistive memory array.
2. Description of Related Art
Resistive memory materials have recently been used to produce non-volatile memory cells. Data is stored in the memory cells by changing resistance of the resistive memory materials. Resistive memory materials may include colossal magnetoresistance (CMR) material, high temperature superconductivity (HTSC) materials, or other materials that have a perovskite structure capable of having electrical resistance characteristics altered by external influences. Such external influences may include applying positive and negative or reverse polarity voltages to the resistive memory materials to change the resistance characteristics thereof. The electric field strength or electric current density from one or more pulses is generally sufficient to switch the physical state of the resistive memory materials so as to modify the resistive properties. Alternatively, a pulse with the same polarity, but with different pulse widths, may be utilized to reverse the resistive property of the resistive memory materials previously set. Whichever technique is selected, in applying a pulse to the resistive memory materials, the pulse is to be low enough in energy so as not to destroy or damage the resistive material.
To improve size, speed, and efficiency of resistive memory arrays, the principles of the present invention provide for a 1T1R resistive memory array configured as chains of memory cells, where each memory cell is composed of a resistive element in parallel with a switch. Such a configuration is non-volatile and provides for each of the memory cells to be randomly accessed. One embodiment of the principles of the present invention includes an electronic memory including a plurality of memory cells, each memory cell includes a switch and a resistive memory element connected in parallel. The resistive memory element is capable of existing in one of a plurality of resistive states, where each resistive state represents a different data state. The electronic memory further includes a memory write and read circuit selectably coupled to the resistive memory element and capable of writing a data state to the resistive memory element and reading the data state.
Another embodiment includes a method of writing to an electronic memory including a plurality of memory cells, where each memory cell is composed of a resistive memory element. The method includes randomly accessing one of the resistive memory cells and writing data to the randomly accessed resistive memory cell without altering data in any other memory cell.
Yet another embodiment includes an electronic memory including a plurality of memory cells, where each memory cell is composed of a switch connected in parallel with a resistive memory element, a plurality of bit lines may form columns electrically coupling memory cells in series along the bit lines. The memory cells along at least two columns may have substantially the same spacing. A plurality of word lines may form forming rows and be coupled to the switches of the memory cells along the word lines. Circuitry may be coupled to the bit lines and word lines to write and read data to and from at least one memory cell.
Still yet, another embodiment may include an electronic memory cell, including a switch and a resistive memory element coupled in parallel.
Another embodiment may include a method for reading data from an electronic memory having memory cells arranged in rows of word lines and columns of bit lines, each bit line being connected to a column of memory cells having a switch in parallel with a resistive memory element and each word line being connected to switches in rows of the memory cells. The method may include applying a voltage level to all but one word line to turn on each of the switches of the corresponding memory cells, applying a voltage level to the one remaining word line to turn off the switch of the corresponding memory cell to access that memory cell, applying a voltage level to a first side of a bit line of the memory cell being accessed, and sensing the voltage level on the bit line on a second, opposite side of the memory cell being accessed.
An electronic system, including an electronic memory. The electronic memory may include a switch and a resistive memory element coupled in parallel. The system may further include a processor in communication with the memory to write data to and read data from the electronic memory. The electronic system may be a communication device, computing device, or other device that utilizes a memory for storing data.
Yet another embodiment may include a method of manufacturing an integrated circuit electronic memory. The method may include forming a plurality of transistors, forming an insulating layer above the transistors, depositing a resistive material on the insulating layer, etching the resistive material to form a resistive element associated with each of the transistors, etching the insulating layer between the resistive elements to form vias through to the active areas of the transistors, and depositing a conductor in the vias to connect said transistors to the resistive elements.
The principles of the present invention further provide for a substrate and transistor deposited on the substrate. An insulating layer may be disposed above the transistor. A resistive element may be disposed on the insulating layer above the transistor and at least two conductors may electrically connect the transistor in parallel with the resistive element.
A more complete understanding of the method and apparatus of the present invention may be obtained by reference to the following Detailed Description when taken in conjunction with the accompanying Drawings wherein:
The memory array 200 may be configured by forming series or chains of memory cells 202. As shown, the chains of memory cells 202 may be connected along bit lines BL1-BL4. Word lines WL1-WL4 may be connected to memory cells 202 via gate terminals of the switches along respective memory cells 202. Each bit line may have a select switch MB1-MB4 and sense switch MS1-MS4 connected thereto used to control access to memory cells 202 along the corresponding bit lines BL1-BL4. For example, to access a memory cell 202 having switch M11, select switch MB1 and control switch MS1 are selectably turned on. Below control switch MS1 may be a sense amplifier (see,
As previously described, the switches at the top and bottom of the bit lines BL1-BL4 are row/column select switches MB1-MB4 and sense switches MS1-MS4. The select switches MB1-MB4 and sense switches MS1-MS4 are used to select a certain bit and to separate the memory array 200 from external circuitry. For example, if memory cell 302 is to be selected, select switch MB2 and sense switch MS2 are turned on and the other select and sense switches are turned off. In addition, word line WL2 is grounded and each of the other word lines WL1, WL3-WL4 are turned high. By applying a low voltage onto word line WL2, switch M22 remains or is turned off so that current is forced through resistive element R22 connected in parallel to the switch M22. Because word lines WL1, WL3 and WL4 are high, each of the corresponding switches M12, M32, and M42, respectively, are turned on such that current flows through the switches and bypasses each of the resistive elements R12, R32, and R42, respectively connected in parallel. The process of being able to select one memory cell along a bit line enables random access writing and reading. While not writing to or reading from the memory array 200, select switches MB1-MB4 and sense switches MS1-MS4 may be turned off so that the memory array 200 is isolated from the external circuitry, thereby keeping electrical noise from the memory array 200. It should be understood that the memory array 200 is shown as a 4×4 chain array, and may be sized and dimensioned as desired, such as 128×128 or larger.
In operation, an external processor (see,
The particular systems, memory designs, and methods described herein are intended to illustrate the functionality and versatility of the invention, but the invention should not be construed to be limited to those particular embodiments. It is evident that those skilled in the art may make numerous uses and modifications of the specific embodiments described, or equivalent structures and processes may be substituted for the structures and processed described. For example, the memory is shown with the resistive elements and their associated transistors arranged in columns. The resistive elements may just as well have been arranged in rows. Thus, herein, the arrangement is referred to as a row/column arrangement. Since certain changes may be made in the above systems and methods without departing from the scope of the invention, it is intended that all subject matter contained in the above description or shown in the accompanying drawings may be interpreted as illustrative and not in a limiting sense, consequently, the invention is to be construed as embracing each and every novel feature and novel combination of features present or inherently possessed by the systems, devices, and methods described in the claims below and their equivalence.
Paz de Araujo, Carlos A., McMillan, Larry D., Chen, Zheng
Patent | Priority | Assignee | Title |
10002665, | Apr 05 2017 | Arm LTD | Memory devices formed from correlated electron materials |
10002669, | May 10 2017 | ARM Ltd. | Method, system and device for correlated electron switch (CES) device operation |
10008263, | Sep 22 2015 | ARM Ltd. | Method, system and device for complementary non-volatile memory device operation |
10014052, | Mar 31 2016 | ARM Ltd. | Method, system and device for read signal generation |
10014468, | Feb 29 2016 | CERFE LABS, INC | Barrier layer for correlated electron material |
10038141, | Jan 26 2016 | CERFE LABS, INC | Fabrication of correlated electron material devices |
10043559, | Feb 24 2016 | ARM Ltd. | Sense amplifier |
10049735, | Sep 22 2015 | ARM Ltd. | Method, system and device for complementary non-volatile memory device operation |
10049739, | Dec 22 2015 | ARM Ltd. | Latching device and method |
10056143, | Sep 08 2015 | CERFE LABS, INC | Correlated electron switch programmable fabric |
10062435, | Oct 27 2016 | ARM Ltd. | Method, system and device for non-volatile memory device operation |
10096361, | Aug 13 2015 | Arm LTD | Method, system and device for non-volatile memory device operation |
10115473, | Apr 06 2017 | ARM Ltd. | Method, system and device for correlated electron switch (CES) device operation |
10127977, | Oct 14 2016 | ARM Ltd. | Method, system and device for non-volatile memory device state detection |
10127981, | Oct 25 2016 | ARM Ltd. | Method, system and device for non-volatile memory device operation |
10134986, | Jul 05 2016 | CERFE LABS, INC | Correlated electron material devices using dopant species diffused from nearby structures |
10134987, | Dec 22 2015 | CERFE LABS, INC | Access devices to correlated electron switch |
10141504, | Jan 24 2017 | CERFE LABS, INC | Methods and processes for forming devices from correlated electron material (CEM) |
10147879, | Sep 30 2015 | CERFE LABS, INC | Multiple impedance correlated electron switch fabric |
10148279, | Nov 30 2016 | ARM Ltd. | Digital to analog conversion with correlated electron switch devices |
10170700, | Feb 19 2016 | CERFE LABS, INC | Fabrication of correlated electron material devices method to control carbon |
10193063, | Dec 01 2016 | CERFE LABS, INC | Switching device formed from correlated electron material |
10211398, | Jul 03 2017 | CERFE LABS, INC | Method for the manufacture of a correlated electron material device |
10217935, | Dec 07 2016 | CERFE LABS, INC | Correlated electron device formed via conversion of conductive substrate to a correlated electron region |
10217937, | Sep 10 2015 | CERFE LABS, INC | Asymmetric correlated electron switch operation |
10229731, | Oct 11 2017 | Arm LTD | Method, system and circuit for staggered boost injection |
10236888, | Mar 29 2016 | ARM Ltd. | Correlated electron switch device |
10267831, | Sep 30 2016 | ARM Ltd. | Process variation compensation with correlated electron switch devices |
10269414, | May 09 2017 | ARM Ltd. | Bit-line sensing for correlated electron switch elements |
10276238, | Sep 22 2015 | ARM Ltd. | Method, system and device for complementary non-volatile memory device operation |
10276795, | Aug 15 2016 | CERFE LABS, INC | Fabrication of correlated electron material film via exposure to ultraviolet energy |
10340453, | May 31 2017 | CERFE LABS, INC | Forming and operating memory devices that utilize correlated electron material (CEM) |
10352971, | Sep 30 2016 | Arm LTD | Voltage detection with correlated electron switch |
10354727, | Oct 05 2015 | ARM Ltd. | Circuit and method for monitoring correlated electron switches |
10366753, | Sep 08 2015 | CERFE LABS, INC | Correlated electron switch programmable fabric |
10373680, | May 09 2017 | ARM Ltd. | Controlling current through correlated electron switch elements during programming operations |
10381560, | Aug 11 2016 | CERFE LABS, INC | Fabrication of correlated electron material films with varying atomic or molecular concentrations of dopant species |
10388377, | Sep 22 2015 | ARM Ltd. | Method, system and device for complementary non-volatile memory device operation |
10418553, | Mar 28 2018 | CERFE LABS, INC | Formation of correlated electron material (CEM) device via dopant deposition and anneal |
10431304, | Feb 27 2017 | ARM Ltd. | Method, system and device for non-volatile memory device operation |
10447260, | Aug 13 2015 | ARM Ltd. | Programmable current for correlated electron switch |
10454026, | Dec 06 2016 | CERFE LABS, INC | Controlling dopant concentration in correlated electron materials |
10504593, | Nov 01 2016 | ARM Ltd. | Method, system and device for non-volatile memory device operation with low power, high speed and high density |
10516110, | Jul 12 2016 | CERFE LABS, INC | Fabrication of correlated electron material devices with reduced interfacial layer impedance |
10521338, | Jun 05 2017 | ARM Ltd. | Method, system and device for memory device operation |
10529420, | Aug 13 2015 | ARM Ltd. | Memory write driver, method and system |
10566527, | Mar 23 2018 | CERFE LABS, INC | Method for fabrication of a CEM device |
10580489, | Apr 23 2018 | TREV Labs, LLC | Method, system and device for complementary impedance states in memory bitcells |
10580981, | Aug 07 2018 | CERFE LABS, INC | Method for manufacture of a CEM device |
10580982, | Feb 19 2016 | CERFE LABS, INC | Fabrication of correlated electron material devices method to control carbon |
10586924, | Aug 22 2016 | CERFE LABS, INC | CEM switching device |
10593880, | Jul 03 2017 | CERFE LABS, INC | Method for the manufacture of a correlated electron material device |
10607659, | Apr 23 2018 | ARM Limited | Method, system and device for integration of bitcells in a volatile memory array and bitcells in a non-volatile memory array |
10672982, | Nov 30 2018 | CERFE LABS, INC | Fabrication of correlated electron material (CEM) devices |
10700280, | May 31 2017 | CERFE LABS, INC | Forming and operating memory devices that utilize correlated electron material (CEM) |
10707415, | Jan 24 2017 | CERFE LABS, INC | Methods and processes for forming devices from correlated electron material (CEM) |
10714175, | Oct 10 2017 | Arm LTD | Method, system and device for testing correlated electron switch (CES) devices |
10719236, | Nov 20 2015 | Arm LTD | Memory controller with non-volatile buffer for persistent memory operations |
10727408, | Dec 22 2015 | CERFE LABS, INC | Access devices to correlated electron switch |
10741246, | Apr 23 2018 | ARM Limited | Method, system and device for integration of volatile and non-volatile memory bitcells |
10763433, | Sep 10 2015 | CERFE LABS, INC | Asymmetric correlated electron switch operation |
10770140, | Jan 27 2016 | Hewlett Packard Enterprise Development LP | Memristive array with parallel reset control devices |
10797238, | Jan 26 2016 | CERFE LABS, INC | Fabricating correlated electron material (CEM) devices |
10832746, | Jul 01 2014 | GSI TECHNOLOGY INC | Non-volatile in-memory computing device |
10833271, | Mar 23 2018 | CERFE LABS, INC | Method for fabrication of a CEM device |
10854811, | Oct 17 2018 | ARM Limited | Formation of correlated electron material (CEM) devices with restored sidewall regions |
10854814, | Jul 05 2016 | CERFE LABS, INC | Correlated electron material devices using dopant species diffused from nearby structures |
10861541, | Aug 13 2015 | ARM Ltd. | Method, system and device for non-volatile memory device operation |
10971229, | Apr 23 2018 | ARM Limited | Method, system and device for integration of volatile and non-volatile memory bitcells |
11004479, | Apr 23 2018 | ARM Limited | Method, system and device for integration of bitcells in a volatile memory array and bitcells in a non-volatile memory array |
11005039, | Aug 07 2018 | CERFE LABS, INC | Correlated electron material (CEM) device |
11011227, | Jun 15 2018 | Arm LTD | Method, system and device for non-volatile memory device operation |
11011701, | Dec 01 2016 | CERFE LABS, INC | Switching device formed from correlated electron material |
11075339, | Oct 17 2018 | CERFE LABS, INC | Correlated electron material (CEM) devices with contact region sidewall insulation |
11133466, | Apr 29 2020 | CERFE LABS, INC | Methods for controlling switching characteristics of a correlated electron material device |
11137919, | Oct 30 2017 | ARM Ltd.; Arm LTD | Initialisation of a storage device |
11183998, | Jul 31 2015 | CERFE LABS, INC | Correlated electron switch |
11258010, | Sep 12 2019 | CERFE LABS, INC | Formation of a correlated electron material (CEM) |
11347254, | Aug 13 2015 | ARM, Ltd. | Programmable voltage reference |
11355192, | Feb 23 2016 | ARM Ltd. | CES-based latching circuits |
11450804, | Jan 26 2016 | CERFE LABS, INC | Fabricating correlated electron material (CEM) devices |
11522133, | Dec 07 2016 | CERFE LABS, INC | Correlated electron device formed via conversion of conductive substrate to a correlated electron region |
11881263, | Apr 23 2018 | ARM Limited | Method, system and device for integration of volatile and non-volatile memory bitcells |
7447053, | Mar 07 2006 | Infineon Technologies AG | Memory device and method for operating such a memory device |
7830693, | Nov 12 2008 | Seagate Technology LLC | NAND based resistive sense memory cell architecture |
7961534, | Sep 10 2007 | Hynix Semiconductor Inc. | Semiconductor memory device for writing data to multiple cells simultaneously and refresh method thereof |
8320159, | Mar 25 2009 | PANASONIC SEMICONDUCTOR SOLUTIONS CO , LTD | Resistance variable nonvolatile memory device |
8331127, | May 24 2010 | Macronix International Co., Ltd. | Nonvolatile memory device having a transistor connected in parallel with a resistance switching device |
8363442, | Nov 12 2008 | Seagate Technology LLC | NAND based resistive sense memory cell architecture |
8942023, | Aug 05 2011 | Renesas Electronics Corporation | Semiconductor device |
9514814, | Aug 13 2015 | Arm LTD | Memory write driver, method and system |
9548118, | Sep 22 2015 | Arm LTD | Method, system and device for complementary non-volatile memory device operation |
9558819, | Aug 13 2015 | Arm LTD | Method, system and device for non-volatile memory device operation |
9621161, | Dec 28 2015 | ARM Ltd. | Method and circuit for detection of a fault event |
9627615, | Jan 26 2016 | CERFE LABS, INC | Fabrication of correlated electron material devices |
9647037, | Aug 25 2015 | Qualcomm Incorporated | Resistive random access memory device with resistance-based storage element and method of fabricating same |
9660189, | Feb 29 2016 | CERFE LABS, INC | Barrier layer for correlated electron material |
9734895, | Dec 22 2015 | ARM Ltd. | Latching device and method |
9735360, | Dec 22 2015 | CERFE LABS, INC | Access devices to correlated electron switch |
9735766, | Jul 31 2015 | CERFE LABS, INC | Correlated electron switch |
9747982, | Feb 22 2016 | Arm LTD | Device and method for generating random numbers |
9748943, | Aug 13 2015 | ARM Ltd.; Arm LTD | Programmable current for correlated electron switch |
9755146, | Sep 10 2015 | CERFE LABS, INC | Asymmetric correlated electron switch operation |
9773550, | Dec 22 2015 | ARM Ltd. | Circuit and method for configurable impedance array |
9786370, | Feb 23 2016 | Arm LTD | CES-based latching circuits |
9792982, | Mar 31 2016 | Arm LTD | Method, system and device for read signal generation |
9792984, | Oct 27 2016 | Arm LTD | Method, system and device for non-volatile memory device operation |
9805777, | Feb 24 2016 | Arm LTD | Sense amplifier |
9851738, | Aug 13 2015 | ARM Ltd.; Arm LTD | Programmable voltage reference |
9871528, | Nov 30 2016 | ARM Ltd. | Digital to analog conversion with correlated electron switch devices |
9899083, | Nov 01 2016 | ARM Ltd. | Method, system and device for non-volatile memory device operation with low power high speed and high density |
9905295, | Dec 22 2015 | ARM Ltd. | Circuit and method for configurable impedance array |
9912334, | Dec 28 2015 | ARM Ltd. | Method and circuit for detection of a fault event |
9916895, | Aug 13 2015 | Arm LTD | Memory write driver, method and system |
9947402, | Feb 27 2017 | Arm LTD | Method, system and device for non-volatile memory device operation |
9966138, | Feb 22 2016 | ARM Ltd. | Device and method for generating random numbers |
9972388, | Oct 12 2016 | Arm LTD | Method, system and device for power-up operation |
9979385, | Oct 05 2015 | ARM Ltd. | Circuit and method for monitoring correlated electron switches |
9979649, | Dec 04 2015 | Wisconsin Alumni Research Foundation | High density content addressable memory |
9990992, | Oct 25 2016 | Arm LTD | Method, system and device for non-volatile memory device operation |
9997242, | Oct 14 2016 | Arm LTD | Method, system and device for non-volatile memory device state detection |
9997702, | Aug 11 2016 | CERFE LABS, INC | Fabrication of correlated electron material films with varying atomic or molecular concentrations of dopant species |
Patent | Priority | Assignee | Title |
5313418, | Oct 31 1991 | United Microelectronics Corporation | Semiconductor memory and memorizing method to read only semiconductor memory |
6204139, | Aug 25 1998 | UNIVERSITY OF HOUSTON | Method for switching the properties of perovskite materials used in thin film resistors |
6473330, | Jun 02 1999 | TOSHIBA MEMORY CORPORATION | Chain type ferroelectric memory with isolation transistors coupled between a sense amplifier and an equalization circuit |
6583003, | Sep 26 2002 | SAMSUNG ELECTRONICS CO , LTD | Method of fabricating 1T1R resistive memory array |
6841833, | Sep 26 2002 | SAMSUNG ELECTRONICS CO , LTD | 1T1R resistive memory |
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