A bit manipulation processor, system and method are provided which reduces the number of operations performed during data processing. An additional register is used as a buffer. The buffer has a bit length which is preferably greater than the address boundaries in a memory or register address. A bitstream can be processed using the buffer by itself or in combination with a standard register, depending upon the particular function to be implemented.

PTO Wrapper PDF
Dossier Espace Google
Patent
   7334116
Priority
Oct 06 2004
Filed
Oct 06 2004
Issued
Feb 19 2008
Expiry
May 07 2025
Extension
213 days
Inventors
Iwata, Eiji
Assg.orig
Sony Compu…
Assg.curr
SONY NETWO…
Sony Compu…
Entity
Large
Referenced by
5
References
40
Maint.:
all paid
BACKGROUND OF THE IN…
SUMMARY OF THE INVEN…
BRIEF DESCRIPTION OF…
DETAILED DESCRIPTION
5. A method of performing bit manipulation on data in a bitstream that is stored in a memory having an address boundary length, said method comprising:
(I) transferring the data in the bitstream from the memory into a buffer, the buffer having a bit length greater than the address boundary length of the memory; and
(II) manipulating the transferred data while it is stored in the buffer to delete a number of bits from the buffer;
wherein when the number of valid bits in the transferred data is greater than the bit length of a register address plus the number of bits to be deleted, said step of manipulating the bitstream data includes:
logically left shifting the transferred data stored in the buffer by the number of bits to be deleted.
9. A processor having instructions for carrying out a method of performing bit manipulation on data in a bitstream that is stored in a memory having an address boundary length, said method comprising:
(I) transferring the data in the bitstream from the memory into a buffer, the buffer having a bit length greater than the address boundary length of the memory; and
(II) manipulating the transferred data while it is stored in the buffer to delete a number of bits from the buffer;
wherein when the number of valid bits in the transferred data is greater than the bit length of a register address plus the number of bits to be deleted, said step of manipulating the bitstream data includes:
logically left shifting the transferred data stored in the buffer by the number of bits to be deleted.
18. A computer-readable medium storing instructions for a processor to carry out a method of performing bit manipulation on data in a bitstream that is stored in a memory having an address boundary length, said method comprising:
(I) transferring the data in the bitstream from the memory into a buffer, the buffer having a bit length greater than the address boundary length of the memory; and
(II) manipulating the transferred data while it is stored in the buffer to delete a number of bits from the buffer;
wherein when the number of valid bits in the transferred data is greater than the bit length of a register address plus the number of bits to be deleted, said step of manipulating the bitstream data includes:
logically left shifting the transferred data stored in the buffer by the number of bits to be deleted.
3. A method of performing bit manipulation on data in a bitstream that is stored in a memory having an address boundary length, said method comprising:
(I) transferring the data in the bitstream from the memory into a buffer, the buffer having a bit length greater than the address boundary length of the memory; and
(II) when a number of invalid bits in the transferred data of the buffer is greater than the number of bits to be put into the buffer, manipulating the transferred data while it is stored in the buffer, including:
(i) loading the bits to be put into the buffer into a register,
(ii) logically left-shifting the loaded data stored in the register by the number of invalid bits in the buffer minus the number of bits to be put in the buffer,
(iii) logically summing the transferred data of the buffer with the left-shifted contents of the register, and
(iv) storing the logical sum in the buffer.
8. A processor having instructions for carrying out a method of performing bit manipulation on data in a bitstream that is stored in a memory having an address boundary length, said method comprising:
(I) transferring the data in the bitstream from the memory into a buffer, the buffer having a bit length greater than the address boundary length of the memory; and
(II) when a number of invalid bits in the transferred data of the buffer is greater than the number of bits to be put into the buffer, manipulating the transferred data while it is stored in the buffer, including:
(i) loading the bits to be put into the buffer into a register,
(ii) logically left-shifting the loaded data stored in the register by the number of invalid bits in the buffer minus the number of bits to be put in the buffer,
(iii) logically summing the transferred data of the buffer with the left-shifted contents of the register, and
(iv) storing the logical sum in the buffer.
16. A computer-readable medium storing instructions for a processor to carry out a method of performing bit manipulation on data in a bitstream that is stored in a memory having an address boundary length, said method comprising:
(I) transferring the data in the bitstream from the memory into a buffer, the buffer having a bit length greater than the address boundary length of the memory; and
(II) when a number of invalid bits in the transferred data of the buffer is greater than the number of bits to be put into the buffer, manipulating the transferred data while it is stored in the buffer, including:
(i) loading the bits to be put into the buffer into a register,
(ii) logically left-shifting the loaded data stored in the register by the number of invalid bits in the buffer minus the number of bits to be put in the buffer,
(iii) logically summing the transferred data of the buffer with the left-shifted contents of the register, and
(iv) storing the logical sum in the buffer.
22. A system, comprising:
a memory operable to store data in a bitstream and having an address boundary length; and
a processor that includes a buffer having a bit length greater than the address boundary length of the memory, said processor having instructions for carrying out a method of performing bit manipulation on data in a bitstream that is stored in a memory having an address boundary length, said method comprising:
(I) transferring the data in the bitstream from the memory into a buffer, the buffer having a bit length greater than the address boundary length of the memory; and
(II) manipulating the transferred data while it is stored in the buffer to delete a number of bits from the buffer;
wherein when the number of valid bits in the transferred data is greater than the bit length of a register address plus the number of bits to be deleted, said step of manipulating the bitstream data includes:
logically left shifting the transferred data stored in the buffer by the number of bits to be deleted.
20. A system, comprising:
a memory operable to store data in a bitstream and having an address boundary length; and
a processor that includes a buffer having a bit length greater than the address boundary length of the memory, said processor having instructions for carrying out a method of performing bit manipulation on data in a bitstream that is stored in a memory having an address boundary length, said method comprising:
(I) transferring the data in the bitstream from the memory into a buffer, the buffer having a bit length greater than the address boundary length of the memory; and
(II) when a number of invalid bits in the transferred data of the buffer is greater than the number of bits to be put into the buffer, manipulating the transferred data while it is stored in the buffer, including:
(i) loading the bits to be put into the buffer into a register,
(ii) logically left-shifting the loaded data stored in the register by the number of invalid bits in the buffer minus the number of bits to be put in the buffer,
(iii) logically summing the transferred data of the buffer with the left-shifted contents of the register, and
(iv) storing the logical sum in the buffer.
6. A method of performing bit manipulation on data in a bitstream that is stored in a memory having an address boundary length, said method comprising:
(I) transferring the data in the bitstream from the memory into a buffer, the buffer having a bit length greater than the address boundary length of the memory; and
(II) manipulating the transferred data while it is stored in the buffer to delete a number of bits from the buffer;
(III) wherein when the number of valid bits in the transferred data is less than or equal to the bit length of a register address plus the number of bits to be deleted, said step of manipulating the transferred data includes:
(i) loading the contents of memory including the bits to be deleted into first and second registers, the first and the second register having a bit length greater than the memory address bit length,
(ii) logically left-shifting the first register by M bits, M being the number of bits between the buffer boundary and the most significant bit of the address pointed to by the bitstream pointer,
(iii) logically right-shifting the bit loaded into the second register by the difference of the buffer bit capacity and M,
(iv) logically summing the left-shifted contents of the first register with the right-shifted contents of the second register, and
(v) storing the logical sum in the buffer.
4. A method of performing bit manipulation on data in a bitstream that is stored in a memory having an address boundary length, said method comprising:
(I) transferring the data in the bitstream from the memory into a buffer, the buffer having a bit length greater than the address boundary length of the memory; and
(II) when a number of invalid bits of transferred data in the buffer is less than or equal to the number of bits to be put into the buffer, manipulating the transferred data while it is stored in the buffer, including:
(i) storing a first part of bits to be put into the buffer into a first register,
(ii) logically right shifting the first part of the bits to be put that are stored in the first register by the number of bits to be put in the buffer minus the number of invalid bits in the buffer,
(iii) logically summing the right shifted contents of the first register with the transferred data of the buffer and putting the results into the memory,
(iv) storing a second part of bits to be put into the buffer into a second register,
(v) logically left shifting the second part of bits to be put that are stored in the second register by the bit length of the buffer minus the number of bits to put into the buffer plus the number of invalid bits in the buffer, and
(vi) storing the left shifted contents of the second register into the buffer.
15. A processor having instructions for carrying out a method of performing bit manipulation on data in a bitstream that is stored in a memory having an address boundary length, said method comprising:
(I) transferring the data in the bitstream from the memory into a buffer, the buffer having a bit length greater than the address boundary length of the memory; and
(II) manipulating the transferred data while it is stored in the buffer to delete a number of bits from the buffer;
(III) wherein when the number of valid bits in the transferred data is less than or equal to the bit length of a register address plus the number of bits to be deleted, said step of manipulating the transferred data includes:
(i) loading the contents of memory including the bits to be deleted into first and second registers, the first and the second register having a bit length greater than the memory address bit length,
(ii) logically left-shifting the first register by M bits, M being the number of bits between the buffer boundary and the most significant bit of the address pointed to by the bitstream pointer,
(iii) logically right-shifting the bit loaded into the second register by the difference of the buffer bit capacity and M,
(iv) logically summing the left-shifted contents of the first register with the right-shifted contents of the second register, and
(v) storing the logical sum in the buffer.
14. A processor having instructions for carrying out a method of performing bit manipulation on data in a bitstream that is stored in a memory having an address boundary length, said method comprising:
(I) transferring the data in the bitstream from the memory into a buffer, the buffer having a bit length greater than the address boundary length of the memory; and
(II) when a number of invalid bits of transferred data in the buffer is less than or equal to the number of bits to be put into the buffer, manipulating the transferred data while it is stored in the buffer, including:
(i) storing a first part of bits to be put into the buffer into a first register,
(ii) logically right shifting the first part of the bits to be put that are stored in the first register by the number of bits to be put in the buffer minus the number of invalid bits in the buffer,
(iii) logically summing the right shifted contents of the first register with the transferred data of the buffer and putting the results into the memory,
(iv) storing a second part of bits to be put into the buffer into a second register,
(v) logically left shifting the second part of bits to be put that are stored in the second register by the bit length of the buffer minus the number of bits to put into the buffer plus the number of invalid bits in the buffer, and
(vi) storing the left shifted contents of the second register into the buffer.
19. A computer-readable medium storing instructions for a processor to carry out a method of performing bit manipulation on data in a bitstream that is stored in a memory having an address boundary length, said method comprising:
(I) transferring the data in the bitstream from the memory into a buffer, the buffer having a bit length greater than the address boundary length of the memory; and
(II) manipulating the transferred data while it is stored in the buffer to delete a number of bits from the buffer;
(III) wherein when the number of valid bits in the transferred data is less than or equal to the bit length of a register address plus the number of bits to be deleted, said step of manipulating the transferred data includes:
(i) loading the contents of memory including the bits to be deleted into first and second registers, the first and the second register having a bit length greater than the memory address bit length,
(ii) logically left-shifting the first register by M bits, M being the number of bits between the buffer boundary and the most significant bit of the address pointed to by the bitstream pointer,
(iii) logically right-shifting the bit loaded into the second register by the difference of the buffer bit capacity and M,
(iv) logically summing the left-shifted contents of the first register with the right-shifted contents of the second register, and
(v) storing the logical sum in the buffer.
17. A computer-readable medium storing instructions for a processor to carry out a method of performing bit manipulation on data in a bitstream that is stored in a memory having an address boundary length, said method comprising:
(I) transferring the data in the bitstream from the memory into a buffer, the buffer having a bit length greater than the address boundary length of the memory; and
(II) when a number of invalid bits of transferred data in the buffer is less than or equal to the number of bits to be put into the buffer, manipulating the transferred data while it is stored in the buffer, including:
(i) storing a first part of bits to be put into the buffer into a first register,
(ii) logically right shifting the first part of the bits to be put that are stored in the first register by the number of bits to be put in the buffer minus the number of invalid bits in the buffer,
(iii) logically summing the right shifted contents of the first register with the transferred data of the buffer and putting the results into the memory,
(iv) storing a second part of bits to be put into the buffer into a second register,
(v) logically left shifting the second part of bits to be put that are stored in the second register by the bit length of the buffer minus the number of bits to put into the buffer plus the number of invalid bits in the buffer, and
(vi) storing the left shifted contents of the second register into the buffer.
1. A method of performing bit manipulation on data in a bitstream that is stored in a memory having an address boundary length, said method comprising:
(I) transferring the data in the bitstream from the memory into a buffer, the buffer having a bit length greater than the address boundary length of the memory;
(II) locating a number of valid bits to get in a predetermined alignment in the buffer; and
(III) when the number of valid bits in the transferred data of the buffer is less than or equal to a register address bit length plus the number of bits to get, manipulating the transferred data while it is stored in the buffer, including:
(i) loading the contents of the memory containing the bits to get into the buffer and a register, the buffer and the register having a bit length greater than the memory address bit length,
(ii) logically left-shifting the loaded data stored in the buffer by M bits, wherein M is the number of bits between the buffer boundary and the most significant bit of the address pointed to by a bitstream pointer,
(iii) logically right-shifting the loaded data stored in the register by the difference of the buffer bit length and M,
(iv) logically summing the left-shifted contents of the buffer with the right-shifted contents of the register,
(v) storing the logical sum in the buffer,
(vi) logically right-shifting the logical sum in the buffer by the bit capacity of the buffer minus the number of bits to get, and
(vii) shifting the bitstream pointer past the memory address holding the number of bits to get.
7. A processor having instructions for carrying out a method of performing bit manipulation on data in a bitstream that is stored in a memory having an address boundary length, said method comprising:
(I) transferring the data in the bitstream from the memory into a buffer, the buffer having a bit length greater than the address boundary length of the memory;
(II) locating a number of valid bits to get in a predetermined alignment in the buffer; and
(III) when the number of valid transferred bits in the buffer is less than or equal to a register address bit length plus the number of bits to get, manipulating the transferred bit data while it is stored in the buffer, including:
(i) loading the contents of the memory containing the bits to get into the buffer and a register, the buffer and the register having a bit length greater than the memory address bit length,
(ii) logically left-shifting the loaded data stored in the buffer by M bits, wherein M is the number of bits between the buffer boundary and the most significant bit of the address pointed to by a bitstream pointer,
(iii) logically right-shifting the loaded data stored in the register by the difference of the buffer bit length and M,
(iv) logically summing the left-shifted contents of the buffer with the right-shifted contents of the registers,
(v) storing the logical sum in the buffer,
(vi) logically right-shifting the logical sum in the buffer by the bit capacity of the buffer minus the number of bits to get, and
(vii) shifting the bitstream pointer past the memory address holding the number of bits to get.
23. A system, comprising:
a memory operable to store data in a bitstream and having an address boundary length; and
a processor that includes a buffer having a bit length greater than the address boundary length of the memory, said processor having instructions for carrying out a method of performing bit manipulation on data in a bitstream that is stored in a memory having an address boundary length, said method comprising:
(I) transferring the data in the bitstream from the memory into a buffer, the buffer having a bit length greater than the address boundary length of the memory; and
(II) manipulating the transferred data while it is stored in the buffer to delete a number of bits from the buffer;
(III) wherein when the number of valid bits in the transferred data is less than or equal to the bit length of a register address plus the number of bits to be deleted, said step of manipulating the transferred data includes:
(i) loading the contents of memory including the bits to be deleted into first and second registers, the first and the second register having a bit length greater than the memory address bit length,
(ii) logically left-shifting the first register by M bits, M being the number of bits between the buffer boundary and the most significant bit of the address pointed to by the bitstream pointer,
(iii) logically right-shifting the bit loaded into the second register by the difference of the buffer bit capacity and M,
(iv) logically summing the left-shifted contents of the first register with the right-shifted contents of the second register, and
(v) storing the logical sum in the buffer.
10. A computer-readable medium storing instructions for a processor to carry out a method of performing bit manipulation on data in a bitstream that is stored in a memory having an address boundary length, said method comprising:
(I) transferring the data in the bitstream from the memory into a buffer, the buffer having a bit length greater than the address boundary length of the memory;
(II) locating a number of valid bits to get in a predetermined alignment in the buffer; and
(III) when the number of valid bits in the transferred data of the buffer is less than or equal to a register address bit length plus the number of bits to get, manipulating the transferred data while it is stored in the buffer, including:
(i) loading the contents of the memory containing the bits to get into the buffer and a register, the buffer and the register having a bit length greater than the memory address bit length,
(ii) logically left-shifting the loaded data stored in the buffer by M bits, wherein M is the number of bits between the buffer boundary and the most significant bit of the address pointed to by a bitstream pointer,
(iii) logically right-shifting the loaded data stored in the register by the difference of the buffer bit length and M,
(iv) logically summing the left-shifted contents of the buffer with the right-shifted contents of the register,
(v) storing the logical sum in the buffer,
(vi) logically right-shifting the logical sum in the buffer by the bit capacity of the buffer minus the number of bits to get, and
(vii) shifting the bitstream pointer past the memory address holding the number of bits to get.
21. A system, comprising:
a memory operable to store data in a bitstream and having an address boundary length; and
a processor that includes a buffer having a bit length greater than the address boundary length of the memory, said processor having instructions for carrying out a method of performing bit manipulation on data in a bitstream that is stored in a memory having an address boundary length, said method comprising:
(I) transferring the data in the bitstream from the memory into a buffer, the buffer having a bit length greater than the address boundary length of the memory; and
(II) when a number of invalid bits of transferred data in the buffer is less than or equal to the number of bits to be put into the buffer, manipulating the transferred data while it is stored in the buffer, including:
(i) storing a first part of bits to be put into the buffer into a first register,
(ii) logically right shifting the first part of the bits to be put that are stored in the first register by the number of bits to be put in the buffer minus the number of invalid bits in the buffer,
(iii) logically summing the right shifted contents of the first register with the transferred data of the buffer and putting the results into the memory,
(iv) storing a second part of bits to be put into the buffer into a second register,
(v) logically left shifting the second part of bits to be put that are stored in the second register by the bit length of the buffer minus the number of bits to put into the buffer plus the number of invalid bits in the buffer, and
(vi) storing the left shifted contents of the second register into the buffer.
11. A system, comprising:
a memory operable to store data in a bitstream and having an address boundary length; and
a processor that includes a buffer having a bit length greater than the address boundary length of the memory, said processor having instructions for carrying out a method of performing bit manipulation on data in a bitstream that is stored in a memory having an address boundary length, said method comprising:
(I) transferring the data in the bitstream from the memory into a buffer, the buffer having a bit length greater than the address boundary length of the memory;
(II) locating a number of valid bits to get in a predetermined alignment in the buffer; and
(III) when the number of valid bits in the transferred data of the buffer is less than or equal to a register address bit length plus the number of bits to get, manipulating the transferred data while it is stored in the buffer, including:
(i) loading the contents of the memory containing the bits to get into the buffer and a register, the buffer and the register having a bit length greater than the memory address bit length,
(ii) logically left-shifting the loaded data stored in the buffer by M bits, wherein M is the number of bits between the buffer boundary and the most significant bit of the address pointed to by a bitstream pointer,
(iii) logically right-shifting the loaded data stored in the register by the difference of the buffer bit length and M,
(iv) logically summing the left-shifted contents of the buffer with the right-shifted contents of the register,
(v) storing the logical sum in the buffer,
(vi) logically right-shifting the logical sum in the buffer by the bit capacity of the buffer minus the number of bits to get, and
(vii) shifting the bitstream pointer past the memory address holding the number of bits to get.
2. The method as recited in claim 1, further comprising:
(IV) when the number of valid bits in the transferred data of the buffer is greater than the bit length of the register plus the number of bits to get, manipulating the bitstream data while it is stored in the buffer, including:
(i) logically right-shifting the transferred data stored in the buffer by the bit length of the buffer minus the number of bits to get, and
(ii) logically shifting the bitstream pointer to a new memory address past an address including the number of bits to get.
12. A system as claimed in claim 11, wherein the memory and processor are integrated on a single chip.
13. A system as claimed in claim 11, wherein the memory and processor are separately provided.
BACKGROUND OF THE INVENTION

Bit manipulation is the process of altering or manipulating bits in memory, and typically consists of the following activities: clearing bits, testing bits, comparing bits, inverting bits, inserting bits into a bit string and extracting bits from a bit string. From some of the earliest microprocessor days, AND, OR, EOR, NOT, TEST and SHIFT and ROTATE instructions were primarily relied upon to manipulate bits of data.

In conventional systems, a general purpose computer may spend a significant portion of available processing resources in order to handle variable length data streams in coding and decoding algorithms. The computer loads the variable length bitstream directly from memory (which acts as a bitstream buffer) into a register and then performs various procedures on the data, such as deleting bits, getting bits and showing bits. Interactions between the register and the memory can require a significant number of operations, depending upon the size of the register. For example, performing a “show_bits” function, denoted only herein as the name “show_bits” for ease of understanding its function, which functions to locate the bits of interest in proper alignment in a register using a conventional 32-bit register can require a significant number of operations (e.g., eight operations) if the data of interest does not exceed 32 bits and does not cross a 32-bit boundary in the memory, or even more operations (e.g., 13 operations) if the data of interest does cross the 32-bit boundary. Of course, the number of instructions and the bit boundary may change depending on the instruction set architecture of the processor.

For instance, FIG. 1 illustrates a diagram of a conventional method of showing N bits (“Show_Bits(N)”). Show_Bits(N) provides an integer number, N, of bits in a register. For instance, bitstream data is loaded into memory, such as system memory, and the Show_Bits(N) method places or loads a predetermined number of bitstream bits, N, in a register. Each register and memory location may be addressed with a 32 bit address and two conditions must be accounted for with the Show_bits command: the case where the N bits requested cross a 32-bit boundary in system memory and the case where the N bits requested do not cross a 32-bit boundary in system memory. The bit size of the actual memory locations can vary and can be addressed virtually. In general, a register is distinguished from system memory in that a register is memory which has a specific address which is used to hold information of a specific kind. The bitstream pointer points to a specific memory address in which bitstream data is stored. The bitstream data can arrive asynchronously and can be of variable length.

For example, it may be desired to show a byte of memory from the 70th through the 77th bit locations, a 32-bit boundary occurs at the 95th and 63rd bit (starting bit position occupying the 0th bit position). This represents an instance where N bits does not cross the 32-bit boundary. In a conventional Show_bits method, after determining that the N bits does not cross the 32 bit boundary, the contents of the memory location addressed by the bitstream pointer containing the N bits is loaded into a 32-bit register. M represents the number of bits from the Nth bit to the next memory address boundary. For the case where the byte of memory represented by the 70th through 77th bit locations is desired to be shown, M is 18, the difference from the next boundary, the 95th bit location to the Nth bit or rather 77th bit. Next, the contents of the 32-bit register is logically left shifted by M bits. This ensures that that portion of the register containing the most significant bits are occupied by the N bits to be shown. For this example, N is 8. This is followed by a logical right shift of the contents of the 32 bit register by 32−N bits, or rather 24 bits for this example. All but the relevant N bit portion of the bitstream now remains in the 32 bit register, right-aligned with all non-relevant bitstream data having been shifted out of the 32-bit register. This conventional Show_Bits method thus typically requires at least 8 operations: 3 arithmetic (M+N, the bit difference between the bit position of the most significant bit position of the bitstream and the 32-bit boundary, and 32−N); 1 compare (with 32); 2 shift; 1 load; and 1 branch to the appropriate Show_Bits(N) routine (based off of the results of the compare).

FIG. 2 is a diagram which illustrates another conventional method of a Show_Bits(N) method where the N bits of bitstream data to be shown crosses a 32-bit boundary in memory and/or is greater than 32 bits. Should, for instance, it be desired to show a byte of memory from the 90th through the 97th bit locations, a 32-bit boundaries occur at the 127th, 95th and 63rd bit (starting bit position occupying the 0th bit position). This represents an instance where N bits crosses a 32-bit boundary. The conventional method loads the desired N bits, which, in this example, occupy two memory locations, into to 32-bit registers. That portion of the N bits which lies in the register with the most significant bit portion is logically shifted to the left by M bits. M being the number of bit positions to the 32-bit boundary of the next memory location. In this instance, M is 30, the difference between the boundary at bit position 127 and the most significant bit position in the N bit portion at bit position 97. That portion of the N bits which lies in the register with the least significant bit portion is logically right shifted by 64−M−N bits. Next, the register with the most significant bit portion of the N bits is logically right shifted by 32−N bits and the resultant registers are logically summed, such as performing a logical OR operation. The resultant value, stored in one of the registers holds the bits desired to be shown. This procedure requires at least 13 operations: 5 arithmetic (M+N, the difference of the Bitstream pointer bit position and the 32-bit boundary, 32−N, 64−M, and (64−M)−N); 1 logical OR; 1 compare with greater than 32; 3 shift; 2 load; and 1 branch to the appropriate Show_Bits(N) routine after determining the compare result.

FIG. 3 is a diagram which illustrates a conventional method of deleting bits (“Delete_Bits(N)”) for deleting N data bits from the bitstream. The bitstream pointer is merely moved forward by N bits. By advancing the bitstream pointer by assigning it a value of the bitstream pointer plus N, those N bits are no longer being addressed. Delete bits requires only one arithmetic operation; namely, bitstream pointer+N.

FIG. 4 is a diagram illustrating a conventional method of getting bits from memory (“Get Bits(N)”, which combines a conventional Delete_Bits(N) with a conventional Show_Bits(N) method. Consequently, N bits will be placed and right-aligned in a 32-bit register and the bitstream pointer will be advanced to the next N address. This operation requires either a minimum of 9 or 14 operations depending upon the Show_Bits(N) operation required.

FIG. 5 is a diagram which illustrates a conventional method to place or store N bits (i.e., “Put_Bits(N)”), in memory such as system memory. Two conditions must be evaluated first; namely, whether the N bit portion to be placed in memory will cross a 32-bit boundary in memory or whether it will not cross a 32-bit boundary in memory. The diagram of FIG. 5 illustrates an example where N bits are desired to be placed at the location pointed to by the bitstream pointer in memory. As shown, M bits exist from the end of a 32-bit boundary in memory to the beginning of the memory location addressed by the bitstream pointer at which the N bits is desired to be stored. For the case where the total of M bits plus N bits is less than or equal to 32, the contents of the memory bound by the 32-bit boundary is loaded into a 32-bit register. This 32-bit register is logically right shifted by 32−M bits, thereby right-aligning the M bits. Next, the M bits are logically left shifted by 32−M bits, thereby left-aligning the M bits. The N bits to be placed into memory are then taken from a right-aligned 32-bit register. The register containing the N bits is then logically left shifted by 32−M−N bits. Next the two 32-bit registers are logically summed (e.g., logically OR'ed) together and the result, including the N bits is stored in memory. This method requires at least 12 operations: namely, 4 arithmetic (such as M+N; the bit difference between the 32 bit boundary and the bitstream pointer); 1 compare; 1 logic OR 3 shift, 1 load, 1 store, and 1 branch to the appropriate Put_Bits routine.

FIG. 6 is a diagram illustrating another conventional Put_Bits(N) method for the case where the N-bit portion does cross the 32-bit boundary on memory. M bits from the 32-bit boundary to the bitstream pointer together with the remaining contents of the 32 bit boundary crossing in memory is loaded into a 32-bit register. The 32-bit register is logically right shifted by 32−M bits. Next, the register contents are logically left shifted by 32−M bits. This serves to left-align the M bit contents with zeros placed in the remaining register bit locations. A register holding the N bits to be placed in memory is logically right shifted by 64−M−N bits. However, the shift is accomplished with yet another register which is loaded with the overflow past a 32-bit boundary. This register is logically right-shifted again by M+N−32 bits. The contents of the register holding the shifted overflow, the register holding the left-shifted M bits and the register originally holding the N bits are logically summed (e.g., logically OR'ed) together and the result is stored in memory. This resulting N bits being placed in memory starting at the memory location pointed to by the bitstream pointer next to the M bits in memory. This requires a minimum of 17 operations: 6 arithmetic (which include calculating the difference between the bitstream pointer location and the 32 bit boundary, 32−M, 64−M, (64−M)−N, M+N and (M+N)−32); 1 compare with greater than 32; 1 logical OR; 3 shifts; 3 loads; 2 stores; and 1 branch to the appropriate Put_Bits(N) routine.

Given the conventional methods of bit manipulation examples of which are described above, there exists a need for improved methods and systems for fast bit manipulation that are more efficient and decrease the number of necessary bit manipulation operations.

SUMMARY OF THE INVENTION

The present invention provides apparatus and methods for performing bit manipulation of data in a bitstream. In accordance with one aspect of the present invention, a method of performing bit manipulation on data in a bitstream that is stored in a memory having an address boundary length is provided. The method comprises transferring data in the bitstream from the memory into a buffer, the buffer having a bit length greater than the address boundary length of the memory; and manipulating the bitstream data while it is stored in the buffer.

Preferably, the manipulating of the bitstream data aligns the bits of interest to be shown in a register in a predetermined alignment. Further, the manipulating of the bitstream data may include logically right shifting the bitstream data stored in the buffer by a number of bits equal to the difference between the bit length of the buffer and the number of bits to be shown.

In accordance with another aspect of the present invention, the manipulating of the bitstream data locates a number of valid bits to get in a predetermined alignment in the buffer. Preferably, when the number of valid bits in the buffer is greater than the bit length of the register plus the number of bits to get, and the manipulating of the bitstream data includes logically right-shifting the bitstream data stored in the buffer by the bit length of the buffer minus the number of bits to get; and logically shifting a bitstream pointer to a new address past an address including the number of bits to get.

Further, when the number of valid bits in the bitstream is less than or equal to a register address bit length plus the number of bits to get, the manipulating of the bitstream data includes loading the contents of the memory containing the bits to get into the buffer and a register, the buffer and the register having a bit length greater than the memory address bit length; logically left-shifting the data stored in the buffer by M bits, wherein M is the number of bits between the buffer boundary and the most significant bit of the address pointed to by a bitstream pointer; logically right-shifting the contents of the register by the difference of the buffer bit length and M; and subjecting the contents of the buffer and the registers to a logical sum; storing the results of the logical sum in the buffer; logically right-shifting the buffer by the bit capacity of the buffer minus the number of bits to get; and shifting the bitstream pointer past the address holding the number of bits to get.

Another aspect of the present invention provides that the manipulating of the bitstream data stores the bitstream data into a register prior to putting the bitstream data into the buffer. Preferably, when a number of invalid bits in the buffer is greater than the number of bits to be put into the buffer, the manipulating of the bitstream data includes placing the number of bits to be put into the buffer into a register; logically left-shifting the data stored in the register by the number of invalid bits in the buffer minus the number of bits to be put in the buffer; and subjecting the buffer to a logical sum operation with the register; and storing the result of the logical sum operation in the buffer.

In addition, when a number of invalid bits in the buffer is less than or equal to the number of bits to be put into the buffer, the manipulating of the bitstream data includes: storing a first part of bits to be put into the buffer into a first register; logically right shifting the data stored in the first register by the number of bits to be placed in the buffer minus the number of invalid bits in the buffer; logically summing the contents of the first register with the buffer and putting the results into memory; storing a second part of bits to be put into the buffer into a second register; logically left shifting the data stored in the second register by the bit length of the buffer minus the number of bits to put into the buffer plus the number of invalid bits in the buffer; and storing the contents of the second register into the buffer.

In another aspect of the present invention, the manipulating of the bitstream data deletes bits from the buffer. Preferably, when the number of valid bits in the bitstream is greater than the bit length of a register address plus the number of bits to be deleted, the manipulating of the bitstream data includes logically left shifting the data stored in the buffer by the number of bits to be deleted. Further preferred is when the number of valid bits in the bitstream is less than or equal to the bit length of a register address plus the number of bits to be deleted, the manipulating of the bitstream data includes: loading the contents of memory including the bits to be deleted into a first and a second register, the first and the second register having a bit length greater than the memory address bit length; logically left-shifting the first register by M bits, M being the number of bits between the buffer boundary and the most significant bit of the address pointed to by the bitstream pointer; logically right-shifting the second register by the difference of the buffer bit capacity and M; subjecting the contents of the first and second registers to a logical sum; and storing the result of the logical sum in the buffer.

In another aspect of the present invention, a processor is provided for performing bit manipulation on data in a bitstream that is stored in a memory having an address boundary length, wherein the processor being programmed for: transferring data in the bitstream from the memory into a buffer, the buffer having a bit length greater than the address boundary length of the memory; and manipulating the bitstream data while it is stored in the buffer.

Preferably, the manipulating of the bitstream data aligns the bits of interest to be shown in a register in a predetermined alignment. The processor may also manipulate of the bitstream data locates a number of valid bits to get in a predetermined alignment in the buffer. Further, the processor may store the bitstream data into a register prior to putting the bitstream data into the buffer. The processor may also delete bits from the buffer.

Other aspects of the present invention provide for a storage medium operable to store instructions for causing a processor to perform bit manipulation on data in a bitstream that is stored in a memory having an address boundary length, the instructions causing the processor to: transfer data in the bitstream from the memory into a buffer, the buffer having a bit length greater than the address boundary length of the memory; and manipulate the bitstream data while it is stored in the buffer.

Still another aspect of the present invention provides a system for performing bit manipulation on data in a bitstream, comprising: a memory storing data in a bitstream and having an address boundary length; and a processor comprising a buffer having a bit length greater than the address boundary length of the memory, said processor being programmed for transferring data in the bitstream from the memory into a buffer, the buffer having a bit length greater than the address boundary length of the memory, and manipulating the bitstream data while it is stored in the buffer. The memory and processor may be integrated on a single chip or separately provided.

Another aspect of the present invention provides a computer processing system for performing bit manipulation on data in a bitstream, comprising: a user input device; a display interface for attachment of a display device; a memory storing data in a bitstream and having an address boundary length; and a processor comprising one or more processing elements, at least one of the processor elements comprising a buffer having a bit length greater than the address boundary length of the memory, said processor being programmed for transferring data in the bitstream from the memory into a buffer, the buffer having a bit length greater than the address boundary length of the memory; and manipulating the bitstream data while it is stored in the buffer.

Yet another aspect of the present invention provides a computer network for performing bit manipulation on data in a bitstream, comprising: a plurality of computer processing systems connected to one another via a communications network, each of the computers comprising a user input device; a display interface for attachment of a display device; a memory storing data in a bitstream and having an address boundary length; and a processor comprising one or more processing elements, at least one of the processor elements comprising a buffer having a bit length greater than the address boundary length of the memory, said processor being programmed for transferring data in the bitstream from the memory into a buffer, the buffer having a bit length greater than the address boundary length of the memory; and manipulating the bitstream data while it is stored in the buffer.

In accordance with another aspect of the present invention, the bit manipulation steps can be performed on a wide range of processing systems. By way of example, a multi-processing system can be used.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a conventional bit manipulation function;

FIG. 2 illustrates a conventional bit manipulation function where the N bits of bitstream data cross a 32-bit boundary in memory and/or is greater than 32 bits;

FIG. 3 illustrates a conventional bit manipulation function for deleting N data bits from the bitstream;

FIG. 4 illustrates a conventional bit manipulation function;

FIG. 5 illustrates a conventional bit manipulation function to place or store N bits in memory;

FIG. 6 illustrates another conventional bit manipulation function;

FIG. 7 illustrates a bit manipulation function in accordance with one aspect of the present invention;

FIG. 8 illustrates a bit manipulation function in accordance with one aspect of the present invention for the case where the number of valid bits in the bitstream is greater than 32+N;

FIG. 9 illustrates a bit manipulation function in accordance with one aspect of the present invention for the case where the number of valid bits in the bitstream is less than 32−N;

FIG. 10 illustrates a bit manipulation function in accordance with one aspect of the present invention for the case when the number of invalid bits in the buffer is greater than N;

FIG. 11 illustrates a bit manipulation function in accordance with one aspect of the present invention for the case when the number of invalid bits is less than N;

FIG. 12 illustrates a bit manipulation function in accordance with one aspect of the present invention for the case when the number of valid bits in the bitstream is greater than 32+N;

FIG. 13 illustrates a bit manipulation function in accordance with one aspect of the present invention for the case where “RestBits” is less than 32+N;

FIGS. 14 and 15 illustrate a block diagram of one processing system that can be used to perform bit manipulation in accordance with the present invention; and

FIG. 16 is a schematic diagram of a computer network depicting various computing devices that can be used in accordance with the present invention.
DETAILED DESCRIPTION

Bit manipulation in accordance with the invention provides enhanced bitstream processing for variable length encoding and decoding. In order to reduce the number of operations performed during data processing, a fast bit manipulation scheme has been developed. For instance, the Show_Bits(N) function described above can be performed, according to the invention to be described, in two operations whether or not the data of interest exceeds a memory boundary.

In the present invention, an additional register is employed as the buffer for the bitstream. Upon initialization, the bitstream of interest is loaded into the buffer register and the number of valid bits in the bitstream (referred to herein as “RestBits”) is recorded for later use. Preferably, the buffer register is at least 33 bits, although there is no maximum length. The bitstream may be processed using the buffer by itself or in combination with the standard register, depending upon the particular function required. The RestBits value is used and updated when performing, e.g., logical shifts. The architecture and methodology of the present invention is also applicable to other bit manipulation functions, such as the described Delete_Bits(N) function, the Get_Bits(N) function and the Put_Bits(N) function, and substantial improvements in speed are obtained when performing these functions with the present invention.

It should of course be understood that the reference herein to specifically-named functions such as Get_Bits, Put_Bits, Delete_Bits, etc. are only for ease of understanding of the present invention and are not necessarily well-known or industry terms. Their use herein should not be construed as limiting the present invention such as by limiting the present invention for use only with functions having these exemplary names.

FIG. 7 is a diagram illustrating a Show_Bits(N) method according to the invention. Initially, the bitstream of interest is loaded from memory into a register, which acts as a buffer to hold the relevant bitstream, with the leftmost bit being occupied by the leftmost bit of the memory location to which the bitstream pointer points. This register can be designated as a buffer since it holds data reflective of the bitstream. Preferably, the buffer holds greater than 32 bits of data, and the diagram in FIG. 7 shows this buffer to be 64 bits. According to the Show_Bits(N) method of the invention, loading the 64 bits into the 64-bit buffer requires one register load operation. The term RestBits as used herein describes the number of valid bits in the buffer. For instance, loading a 64 bit buffer will result in RestBits being 64. Alternatively, loading a 33 bit buffer will result in RestBits being 33.

After loading the buffer with data, in order to show the N bits of data, the buffer is logically right shifted by the number of bits in the buffer minus the number of bits to be shown, or rather N. Showing N bits from a 64-bit buffer requires that this register be logically right shifted by 64−N bits. Consequently, Show_Bits(N) according to the invention only requires 2 operations: 1 arithmetic and 1 shift. Note that the result of the logical right shift is shown in a 64-bit register not specifically designated as the buffer. This designation was dropped from the register since after register operations have taken place, it technically is no longer reflective of the bitstream.

FIG. 8 illustrates a diagram showing a Get_Bits(N) method according to the invention for the case where the number of valid bits in the bitstream, RestBits, is greater than 32+N. The example illustrated in FIG. 8 was a 64-bit buffer. After the contents of the bitstream portion of interest are loaded into the buffer, this register is right shifted by the bit length of the register minus N bits. Consequently, for a 64-bit buffer, the buffer contents will be logically right-shifted by 64−N bits as is shown in FIG. 8. Note that the result of the logical right-shift is shown in a 64-bit register not specifically designated as the buffer. This designation was dropped from the register since after register operations have taken place, it technically is no longer reflective of the Bitstream. The Bitstream pointer is then advanced past the N bits by logically left shifting it to another address past that including the N bits. Since the bitstream pointer has been forwarded past the N bits, the 64-bit register is now reflective again of the bitstream and it is designated as the buffer in FIG. 8. The RestBits value is updated to reflect that the buffer no longer points to the N bits. Consequently RestBits is updated by RestBits−N. This method requires a minimum of 7 operations: 3 arithmetic including (for the example illustrated) 32+N, 64−N and RestBits-N; 1 compare, 2 shift including the buffer shift and the bitstream pointer shift; and 1 branch to the appropriate Get_Bits(N) routine after verifying that RestBits is greater than 32+N.

FIG. 9 illustrates a diagram showing a Get_Bits(N) method according to the invention for the case where RestBits is less than 32−N. Contents of the relevant portion of memory are loaded into two registers. For example, FIG. 9 illustrates an example using two 64-bit registers. The least significant half of the register holding the most significant bit information is logically left-shifted by M bits, M being the number of bits from the 64-bit boundary. The other 64-bit register is logically right-shifted by the bit capacity of the register minus M bits or rather 64−M bits. The contents of the two registers are then logically summed (e.g., logically OR'ed) with the result being stored in the buffer. The buffer is logically right-shifted by the bit capacity of the register minus N, or 64−N for the example shown in FIG. 9. Next, the bitstream pointer is logically left shifted by N bits so that the N bits are no longer being pointed to. The RestBits value is updated to reflect the number of bits in the register minus N, or 64−N for the example shown in FIG. 9.

FIG. 10 illustrates a diagram showing a Put_Bits(N) method according to the invention when the number of invalid bits in the buffer is greater than N. The number of invalid bits in the buffer shall be referred to as I-Restbits. Starting with an empty buffer of say 64 bits, the N bits to be placed in the buffer are stored in a 64-bit register. This register is logically left shifted by I-Restbits minus N and the result is logically summed (e.g., logically OR'ed) with the buffer so as to place the N bits in the buffer. I-RestBits becomes I-RestBits-N. This Put_Bits(N) method requires 5 operations: 1 arithmetic, 1 logical, 1 compare, 1 shift and 1 branch to the appropriate Put_Bits(N) routine based on the result of I-RestBits being greater than N.

FIG. 11 illustrates a diagram showing a Put_Bits (N) method when the number of invalid bits, I-Restbits, is less than N. The buffer is initially empty. N bits in a register, of a size greater than 32 bits, e.g., 64 bits is logically right-shifted by (64−N+I-RestBits) . The shifted out data is placed in a separate 64 bit register which is logically left-shifted by 64−I+RestBits. The register in which right-shift occurred is logically summed (e.g., logically OR'ed) with the contents of the buffer. In this case, the buffer has (64-RestBits) of valid bits. Since N is larger than RestBits, N bits is separated into two parts and the following steps are followed. First, the left portion of N bits is stored into a register in order to merge it with the contents of the buffer. Second, the right portion of N bits is stored temporarily into a second register. After putting the first register's value into the buffer, the contents of the buffer is placed into memory since the buffer is full. After this operation, the second register's content is stored into the buffer and RestBits are re-initialized.

FIG. 12 illustrates a diagram showing a Delete_Bits(N) method for the condition where RestBits is greater than 32+N, and this assumes that RestBits is always greater than 32. The buffer is logically left shifted by N bits to reflect the deletion of the N bits from the bitstream. This requires 5 operations: 2 arithmetic, 1 shift, 1 condition and 1 branch to the appropriate delete bits routine.

FIG. 13 illustrates a Delete_Bits(N) method with the buffer register for the case where RestBits is less than 32+N. The example shown in FIG. 13 illustrates Delete_Bits (N) using 64-bit registers. The bitstream pointer points to an address in memory wherein the last bit of the memory contents is M bits away from a 32-bit boundary. The contents of memory which includes the N bits to be deleted from the buffer is loaded into two 64-bit registers. The register containing the bits included in the memory location being addressed by the bitstream pointer is logically left-shifted by M bits. The other 64-bit register is right-shifted by 64−M bits. The two 64-bit registers are logically summed (e.g., logically OR'ed) in the buffer. The bitstream pointer is advanced to an address which does not include the N bits to be deleted. This Delete_Bits(N) method requires 12 operations: 4 arithmetic, 1 logical OR, 1 compare, 3 shift, 2 loads and 1 branch.

The bit manipulation steps in accordance with the various aspects of the present invention can be performed on a wide range of processing systems. For example, the bit manipulation steps can be performed on a stand-alone processing system. They can also be performed on a multi-processor system. An example of a multi-processor system that can be used to perform the bit manipulation steps of the present invention is illustrated in FIG. 14.

FIG. 14 illustrates a processor element. The processor element includes an I/O interface 202, a processor unit 204, a direct memory access controller 206, a plurality of sub-processing units 208, and a memory interface 210. The processor element communicates with a DRAM 214. The processor element is more fully described in U.S. patent application Ser. Nos. 09/816,004 and 09/816,020, both filed on Mar. 22, 2001, which are hereby incorporated by reference.

FIG. 15 illustrates an exemplary sub-processing unit 208. Each sub-processing unit includes local memory 250, registers 252, floating point units 254, integer units 256, and a bus interface 258. The bit manipulation processing in accordance with the various aspects of the present invention can be performed in a number of different places in the processor element of FIG. 14. For instance, it can be performed in the processor unit 204. The bit manipulation of the present invention can also be performed in any of the sub-processing units. Further, processor systems having multiple processors are contemplated by the present invention, and the bit manipulation of the present invention can be performed in selected processor elements in a system having multiple processor elements.

FIG. 16 is a schematic diagram of a computer network depicting various computing devices that can be used alone or in a networked configuration in accordance with the present invention. The computing devices may comprise computer-type devices employing various types of user inputs, displays, memories and processors such as found in typical PCs, laptops, servers, gaming consoles, PDAs, etc. For example, FIG. 16 illustrates a computer network 300 that has a plurality of computer processing systems 310, 320, 330, 340, 350 and 360, connected via a communications network 370 such as a LAN, WAN, the Internet, etc. and which can be wired, wireless, a combination, etc.

Each computer processing system can include, for example, one or more computing devices having user inputs such as a keyboard 311 and mouse 312 (and various other types of known input devices such as pen-inputs, joysticks, buttons, touch screens, etc.), a display interface 313 (such as connector, port, card, etc.) for connection to a display 314, which could include, for instance, a CRT, LCD, or plasma screen monitor, TV, projector, etc. Each computer also preferably includes the normal processing components found in such devices such as one or more memories and one or more processors located within the computer processing system. The memories and processors within such computing device are adapted to perform the bit manipulations on data in a bitstream in accordance with the various aspects of the present invention as described herein. The memories can include memories for storing bitstream data, buffer memories for receiving data transfers from the bitstream data and memories for storing instructions for causing a processor to perform the storage, transfers and bitstream manipulations in accordance with the present invention.

The present invention is substantially more efficient than conventional processing of variable bitstreams in most cases. The larger the registers, the more efficient the process becomes. The registers and bitstream buffers should preferably be at least 64 bits, and more preferably, the registers and buffers are 128 bits or more.

Although the invention herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present invention. The foregoing described invention has particular application to audio/video coder-decoders (CODECs) and video games and the like which required fast and repetitive manipulation of data. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present invention as defined by the appended claims.

INVENTORS:

Iwata, Eiji

THIS PATENT IS REFERENCED BY THESE PATENTS:
Patent Priority Assignee Title
7421566, Aug 12 2005 International Business Machines Corporation Implementing instruction set architectures with non-contiguous register file specifiers
7793081, Jun 02 2006 International Business Machines Corporation Implementing instruction set architectures with non-contiguous register file specifiers
8604946, Apr 08 2011 Panasonic Corporation Data processing device and data processing method
8898439, Jul 17 2009 Macronix International Co., Ltd. Serial flash memory and address transmission method thereof
9223704, Jan 21 2011 Sony Semiconductor Solutions Corporation Memory access control circuit, prefetch circuit, memory device and information processing system
THIS PATENT REFERENCES THESE PATENTS:
Patent Priority Assignee Title
3793631,
4095265, Jun 07 1976 International Business Machines Corporation Memory control structure for a pipelined mini-processor system
4408275, Dec 26 1979 Hitachi, Ltd. Data processing system with data cross-block-detection feature
4449184, Nov 18 1981 Intel Corporation Extended address, single and multiple bit microprocessor
4970642, Sep 14 1987 Hudson Soft Co. Ltd. An apparatus for accessing a memory
5265204, Oct 05 1984 Hitachi, Ltd. Method and apparatus for bit operational process
5550972, Jun 30 1993 Microsoft Technology Licensing, LLC Method and apparatus for efficient transfer of data to memory
5608887, Jan 12 1993 International Business Machines Corporation Method of processing data strings
5696946, Jun 30 1993 Microsoft Technology Licensing, LLC Method and apparatus for efficient transfer of data to memory
5696959, Nov 30 1993 Texas Instruments Incorporated Memory store from a selected one of a register pair conditional upon the state of a selected status bit
5812147, Sep 20 1996 Hewlett Packard Enterprise Development LP Instruction methods for performing data formatting while moving data between memory and a vector register file
5821886, Oct 18 1996 SAMSUNG ELECTRONICS CO , LTD Variable length code detection in a signal processing system
5826074, Nov 22 1996 SAMSUNG ELECTRONICS CO , LTD Extenstion of 32-bit architecture for 64-bit addressing with shared super-page register
5835793, May 02 1997 Texas Instruments Incorporated Device and method for extracting a bit field from a stream of data
5835973, Apr 25 1991 Kabushiki Kaisha Toshiba Instruction processing unit capable of efficiently accessing the entire address space of an external memory
5865914, Jun 09 1995 Alcoa Inc Method for making an aerospace structural member
6122724, Jun 24 1991 Acacia Research Group LLC; SOTA SEMICONDUCTOR LLC Central processing unit having instruction queue of 32-bit length fetching two instructions of 16-bit fixed length in one instruction fetch operation
6195741, Dec 25 1997 Fujitsu Limited Data processing device having a variable length code processing mechanism
6216218, Nov 03 1997 PMC-SIERRA, INC Processor having a datapath and control logic constituted with basis execution blocks
6247112, Dec 30 1998 Sony Corporation; Sony Electronics, Inc. Bit manipulation instructions
6272620, Jun 24 1991 Acacia Research Group LLC; SOTA SEMICONDUCTOR LLC Central processing unit having instruction queue of 32-bit length fetching two instructions of 16-bit fixed length in one instruction fetch operation
6332188, Nov 06 1998 Analog Devices, Inc Digital signal processor with bit FIFO
6437790, Oct 05 1984 Hitachi, Ltd. Apparatus for bit operational process
6539059, Mar 02 2000 Oracle America, Inc Apparatus and method for efficiently scalable digital video decoding
6546053, May 14 1997 NEC Corporation System and method for decoding signal and method of generating lookup table for using in signal decoding process
6552730, Oct 05 1984 Hitachi, Ltd. Method and apparatus for bit operational process
6560694, Jan 14 2000 Advanced Micro Devices, Inc. Double prefix overrides to provide 16-bit operand size in a 32/64 operating mode
6571330, Jan 14 2000 Advanced Micro Devices, Inc. Address size and operand size prefix overrides for default sizes defined by an operating mode of a processor
6587058, Jun 25 1998 American Patents LLC Processing circuit and method for variable-length coding and decoding
6658578, Oct 06 1998 Texas Instruments Incorporated Microprocessors
6671428, Dec 01 2000 BAYSPEC, INC Wavelength selective optical cross switch and optical add/drop multiplexer using volume phase grating and array of micro electro mechanical mirrors
6671791, Aug 09 2000 Advanced Micro Devices, Inc. Processor including a translation unit for selectively translating virtual addresses of different sizes using a plurality of paging tables and mapping mechanisms
20010047456,
20010050682,
20020025003,
20020050992,
20020066007,
20030043156,
20030210163,
WO198892,
ASSIGNMENT RECORDS    Assignment records on the USPTO
////
Executed onAssignorAssigneeConveyanceFrameReelDoc
Oct 04 2004IWATA, EIJISony Computer Entertainment IncASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS 0152780634 pdf
Oct 06 2004Sony Computer Entertainment Inc.(assignment on the face of the patent)
Apr 01 2010Sony Computer Entertainment IncSONY NETWORK ENTERTAINMENT PLATFORM INC CHANGE OF NAME SEE DOCUMENT FOR DETAILS 0274450239 pdf
Apr 01 2010SONY NETWORK ENTERTAINMENT PLATFORM INC Sony Computer Entertainment IncASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS 0275510154 pdf
MAINTENANCE FEES AND DATES:    Maintenance records on the USPTO
Date Maintenance Fee Events
Aug 07 2008ASPN: Payor Number Assigned.
Jul 21 2011M1551: Payment of Maintenance Fee, 4th Year, Large Entity.
Aug 05 2015M1552: Payment of Maintenance Fee, 8th Year, Large Entity.
Aug 08 2019M1553: Payment of Maintenance Fee, 12th Year, Large Entity.


Date Maintenance Schedule
Feb 19 20114 years fee payment window open
Aug 19 20116 months grace period start (w surcharge)
Feb 19 2012patent expiry (for year 4)
Feb 19 20142 years to revive unintentionally abandoned end. (for year 4)
Feb 19 20158 years fee payment window open
Aug 19 20156 months grace period start (w surcharge)
Feb 19 2016patent expiry (for year 8)
Feb 19 20182 years to revive unintentionally abandoned end. (for year 8)
Feb 19 201912 years fee payment window open
Aug 19 20196 months grace period start (w surcharge)
Feb 19 2020patent expiry (for year 12)
Feb 19 20222 years to revive unintentionally abandoned end. (for year 12)