A method and apparatus for mapping a stream of bits output from an encoder to a stream of bits for 2m-ary modulation. The method and apparatus divides the stream of bits from the encoder into a first period and a second period. The first period includes bits with higher priority in the stream of the bits output from the encoder, and the second period includes bits with lower priority. The method and apparatus maps the bits existing in the first period to bit positions with higher reliability in a stream of m bits representing each of the bits for 2m-ary modulation, and maps the bits existing in the second period to bit positions with lower reliability in the stream of m bits.
|
4. A transmission apparatus in a communication system, comprising:
an encoder;
a sequence mapper for dividing a stream of bits from the encoder into a first period and a second period, the first period including bits with higher priority and the second period including bits with lower priority, and for mapping the stream of bits from the encoder to 3 bit positions representing each of the bits for 8PSK modulation, determined by
s0(i)=x(2·N+i) s1(i)=x(2·i) s2(i)=x(2·i+1) where x(i) indicates an i-th bit before mapping, s(i) indicates an i-th bit after mapping, s0(i) indicates a first bit among the 3 bits representing each of the bits for 8PSK modulation, s1(i) indicates a second bit among the 3 bits representing each of the bits for 8PSK modulation, s2(i) indicates a third bit among the 3 bits representing each of the bits for 8PSK modulation, and i indicates positions of the bits from 0 to (N−1);and
a modulator for 8PSK modulating the mapped bits.
10. A transmission apparatus in a communication system, comprising:
an encoder;
a sequence mapper for dividing a stream of bits output from the encoder into a first period and a second period, the first period including bits with higher priority and the second period including bits with lower priority, and for mapping the stream of bits from the encoder to 3 bit positions representing each of the bits for 8PSK modulation, determined by
s0(N−1−i)=x(2·N+i) s1(N−1−i)=x(2·i+1) s2(N−1−i)=x(2·i) where x(i) indicates an i-th before mapping, s(i) indicates an i-th bit after mapping, s0 indicates a first bit among the 3 bits representing each of the bits for 8-ary PSK modulation, s1 indicates a second bit among the 3 bits representing each of the bits for 8-ary PSK modulation, s2 indicates a third bit among the 3 bits representing each of the bits for 8-ary PSK modulation, and i indicates positions of the bits from 0 to (N−1);and
a modulator for 8PSK modulating the mapped bits.
7. A method for mapping a stream of bits output from an encoder to a stream of bits for 8PSK (8-ary Phase Shift Keying) modulation, comprising the steps of:
dividing the stream of bits from the encoder into a first period and a second period, wherein the first period includes bits with higher priority and the second period includes bits with lower priority; and
mapping the stream of bits from the encoder to 3 bit positions representing each of the bits for 8PSK modulation, determined by
s0(N−1−i)=x(2·N+i) s1(N−1−i)=x(2·i+1) s2(N−1−i)=x(2·i) where x(i) indicates an i-th bit before mapping, s(i) indicates an i-th bit after mapping, s0 indicates a first bit among the 3 bits representing each of the bits for 8-ary PSK modulation, s1 indicates a second bit among the 3 bits representing each of the bits for 8-ary PSK modulation, s2 indicates a third bit among the 3 bits representing each of the bits for 8-ary PSK modulation, and i indicates positions of the bits from 0 to (N−1).
1. A method for mapping a stream of bits output from an encoder to a stream of bits for 8PSK (8-ary Phase Shift Keying) modulation, comprising the steps of:
dividing the stream of bits from the encoder into a first period and a second period, wherein the first period includes bits with higher priority and the second period includes bits with lower priority; and
mapping the stream of bits from the encoder to 3 bit positions representing each of the bits for 8PSK modulation, determined by
s0(i)=x(2·N+i) s1(i)=x(2·i) s2(i)=x(2·i+1) where x(i) indicates an i-th bit before mapping, s(i) indicates an i-th bit after mapping, s0(i), indicates a first bit among the i-th 3 bits representing each of the bits for 8-ary PSK modulation, s1(i) indicates a second bit among the i-th 3 bits representing each of the bits for 8-ary PSK modulation, s2(i) indicates a third bit among the i-th 3 bits representing each of the bits for 8-ary PSK modulation, and i indicates positions of the bits from 0 to (N−1).
5. A transmission apparatus in a communication system, comprising:
an encoder;
a sequence mapper for dividing the stream of bits from the encoder into a first period and a second period, the first period including bits with higher priority and the second period including bits with lower priority, and for mapping the stream of bits from the encoder are mapped to 4 bit positions representing each of the bits for 16QAM modulation, determined by
s0(i)=x(2·N+i) s1(i)=x(2·i) s2(i)=x(2·i+1) s3(i)=x(2·i+1) where x(i) indicates an i-th before mapping, s(i) indicates an i-th bit after mapping, s0(i) indicates a first bit among the 4 bits representing each of the bits for 16QAM modulation, s1(i) indicates a second bit among the 4 bits representing each of the bits for 16QAM modulation, s2(i) indicates a third bit among the 4 bits representing each of the bits for 16QAM modulation, s3(i) indicates a fourth bit among the 4 bits representing each of the bits for 16QAM modulation, and i indicates positions of the bits from 0 to (N−1); and
a modulator for 16QAM modulating the mapped bits.
2. A method for mapping a stream of bits output from an encoder to a stream of bits for 16QAM (16-ary Quadrature Amplitude Modulation) modulation, comprising the steps of:
dividing the stream of bits from the encoder into a first period and a second period, wherein the first period includes bits with higher priority and the second period includes bits with lower priority; and
mapping the stream of bits from the encoder to 4 bit positions representing each of the bits for 16QAM modulation, determined by
s0(i)=x(2·N+2×i) s1(i)=x(2·i) s2(i)=x(2·N+2×i+1) s3(i)=x(2·i+1) where x(i) indicates an i-th bit before mapping, s(i) indicates an i-th bit after mapping, s0 indicates a first bit among the 4 bits representing each of the bits for 16QAM modulation, s1(i) indicates a second bit among the 4 bits representing each of the bits for 16QAM modulation, s2(i) indicates a third bit among the 4 bits representing each of the bits for 16QAM modulation; s3(i) indicates a fourth bit among the 4 bits representing each of the bits for 16QAM modulation, and i indicates positions of the bits from 0 to (N−1).
8. A method for mapping a stream of bits output from an encoder to a stream of bits for 16QAM (16-ary Quadrature Amplitude Modulation) modulation, comprising the steps of:
dividing the stream of bits from the encoder into a first period and a second period, wherein the first period includes bits with higher priority and the second period includes bits with lower priority; and
mapping the stream of bits from the encoder to 4 bit positions representing each of the bits for 16QAM modulation, determined by
s0(N−1−i)=x(2·N+2·i+1) s1(N−1−i)=x(2·i+1) s2(N−1−i)=x(2·N+2·i) s3(N−1−i)=x(2·i) where x(i) indicates an i-th bit before mapping, s(i) indicates an i-th bit after mapping, s0(i) indicates a first bit among the 4 bits representing each of the bits for 16QAM modulation, s1 indicates a second bit among the 4 bits representing each of the bits for 16QAM modulation, s2 indicates a third bit among the 4 bits representing each of the bits for 16QAM modulation, s3 indicates a fourth bit among the 4 bits representing each of the bits for 16QAM modulation, and i indicates positions of the bits from 0 to (N−1).
11. A transmission apparatus in a communication system, comprising:
an encoder;
a sequence mapper for dividing the stream of bits output from the encoder into a first period and a second period, the first period including bits with higher priority and the second period including bits with lower priority, and for mapping the stream of bits output from the encoder are mapped to 4 bit positions representing each of the bits for 16QAM modulation, determined by
s0(N−1−i)=x(2·N+2·i+1) s1(N−1−i)=x(2·i+1) s2(N−1−i)=x(2·N+2·i) s3(N−1−i)=x(2·i) where x(i) indicates an i-th before mapping, s(i) indicates an i-th bit after mapping, s0 indicates a first bit among the 4 bits representing each of the bits for 16QAM modulation, s1 indicates a second bit among the 4 bits representing each of the bits for 16QAM modulation, s2 indicates a third bit among the 4 bits representing each of the bits for 16QAM modulation, s3 indicates a fourth bit among the 4 bits representing each of the bits for 16QAM modulation, and i indicates positions of the bits from 0 to (N−1);and
a modulator for 16QAM modulating the mapped bits.
3. A method for mapping a stream of bits output from an encoder to a stream of bits for 64QAM (64-ary Quadrature Amplitude Modulation) modulation, comprising the steps of:
dividing the stream of bits from the encoder into a first period, a second period and a third period, wherein the first period includes bits with higher priority, the second period includes bits with lower priority and the third period includes bits having lower priority than the bits in the first period and having higher priority than the bits in the second period; and
mapping the stream of bits from the encoder to 6 bit positions representing each of the bits for 64QAM modulation, determined by
s0(i)=x(4·N+2·i) s1(i)=x(2·N+2·i) s2(i)=x(2·i) s3(i)=x(4·N+2·i+1) s4(i)=x(2·N+2·i+1) s5(i)=x(2·i+1) where x(i) indicates an i-th bit before mapping, s(i) indicates an i-th bit after mapping, s0(i) indicates a first bit among the 6 bits representing each of the bits for 64QAM modulation, s1(i) indicates a second bit among the 6 bits representing each of the bits for 64QAM modulation, s2(i) indicates a third bit among the 6 bits representing each of the bits for 64QAM modulation, s3(i) indicates a fourth bit among the 6 bits representing each of the bits for 64QAM modulation, s4(i) indicates a fifth bit among the 6 bits representing each of the bits for 64QAM modulation, s5(i) indicates a sixth bit among the 6 bits representing each of the bits for 64QAM modulation, and i indicates positions of the bits from 0 to (N−1).
9. A method for mapping a stream of bits output from an encoder to a stream of bits for 64QAM (64-ary Quadrature Amplitude Modulation) modulation, comprising the steps of:
dividing the stream of bits output from the encoder into a first period, a second period and a third period, wherein the first period includes bits with higher priority, the second period includes bits with lower priority and the third period includes bits having lower priority than the bits in the first period and having higher priority than the bits in the second period; and
mapping the stream of bits from output the encoder to 6 bit positions representing each of the bits for 64QAM modulation, determined by
s0(N−1−i)=x(4·N+2·i+1) s1(N−1−i)=x(2·N+2·i+1) s2(N−1−i)=x(2·i+1) s3(N−1−i)=x(4·N+2·i) s4(N−1−i)=x(2·N+2·i) s5(N−1−i)=x(2·i) where x(i) indicates an i-th bit before mapping, s(i) indicates an i-th bit after mapping, s0 indicates a first bit among the 6 bits representing each of the bits for 64QAM modulation, s1 indicates a second bit among the 6 bits representing each of the bits for 64QAM modulation, s2 indicates a third bit among the 6 bits representing each of the bits for 64QAM modulation, s3 indicates a fourth bit among the 6 bits representing each of the bits for 64QAM modulation, s4 indicates a fifth bit among the 6 bits representing each of the bits for 64QAM modulation, s5 indicates a sixth bit among the 6 bits representing each of the bits for 64QAM modulation, and i indicates positions of the bits from 0 to (N−1).
12. A transmission apparatus in a communication system, comprising:
an encoder;
a sequence mapper for dividing the stream of bits from the encoder into a first period, a second period, and a third period, the first period including bits with higher priority, the second period including bits with lower priority and the third period including bits having lower priority than the bits in the first period and having higher priority than the bits in the second period, for mapping the bits in the first period to bit positions with higher reliability in a stream of 6 bits representing each of the modulated bits, for mapping the stream of bits from the encoder to 6 bit positions representing each of the bits for 64QAM modulation, determined by
s0(N−1−i)=x(4·N+2·i+1) s1(N−1−i)=x(2·N+2·i+1) s2(N−1−i)=x(2·i+1) s3(N−1−i)=x(4·N+2·i) s4(N−1−i)=x(2·N+2·i) s5(N−1−i)=x(2·i) where x(i) indicates an i-th before mapping, s(i) indicates an i-th bit after mapping, s0 indicates a first bit among the 6 bits representing each of the bits for 64QAM modulation, s1 indicates a second bit among the 6 bits representing each of the bits for 64QAM modulation, s2 indicates a third bit among the 6 bits representing each of the bits for 64QAM modulation, s3 indicates a fourth bit among the 6 bits representing each of the bits for 64QAM modulation, s4 indicates a fifth bit among the 6 bits representing each of the bits for 64QAM modulation, s5 indicates a sixth bit among the 6 bits representing each of the bits for 64QAM modulation, and i indicates positions of the bits from 0 to (N−1); and
a modulator for 64QAM (64-ary Quadrature Amplitude Modulation) modulating the mapped bits.
6. A transmission apparatus in a communication system, comprising:
an encoder;
a sequence mapper for dividing the stream of bits from the encoder into a first period, a second period and a third period, the first period including bits with higher priority, the second period including bits with lower priority and the third period including bits having lower priority than the bits in the first period and having higher priority than the bits in the second period, for mapping the bits existing in the first period to bit positions with higher reliability in a stream of 6 bits representing each of the modulated bits, for mapping the stream of bits output from the encoder to 6 bit positions representing each of the bits for 64QAM modulation, determined by
s0(i)=x(4·N+2·i) s1(i)=x(2·N+2·i) s2(i)=x(2·i) s3(i)=x(4·N+2·i+1) s4(i)=x(2·N+2·i+1) s5(i)=x(2·i+1) where x(i) indicates an i-th bit before mapping, s(i) indicates an i-th bit after mapping, s0(i) indicates a first bit among the 6 bits representing each of the bits for 64QAM modulation, s1(i) indicates a second bit among the 6 bits representing each of the bits for 64QAM modulation, s2(i) indicates a third bit among the 6 bits representing each of the bits for 64QAM modulation, s3(i) indicates a fourth bit among the 6 bits representing each of the bits for 64QAM modulation, s4(i) indicates a fifth bit among the 6 bits representing each of the bits for 64QAM modulation, s5(i) indicates a sixth bit among the 6 bits representing each of the bits for 64QAM modulation, and i indicates positions of the bits from 0 to (N−1); and
a modulator for 64QAM (64-ary Quadrature Amplitude Modulation) modulating the mapped bits.
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
This application is a Continuation Application of U.S. patent application Ser. No. 10/166,480, filed on Jun. 10, 2002 now U.S. Pat. No. 7,130,358 which claims priority to an application entitled “Method and Apparatus for Rearranging Codeword Sequence in a Communication System” filed in the Korean Industrial Property Office on Jun. 9, 2001 and assigned Ser. No. 2001-32355, the contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates generally to a communication system using multi-level modulation/demodulation, and in particular, to a method and apparatus for rearranging a bit stream of a codeword sequence before modulation, and arranging an output of a demodulator in the form of an original codeword sequence.
2. Description of the Related Art
An IMT-2000 (International Mobile Telecommunication-2000) system or a UMTS (Universal Mobile Telecommunication System) system, a typical CDMA (Code Division Multiple Access) mobile communication system, uses multi-level modulation/demodulation in order to increase spectral efficiency. Here, the “multi-level modulation” refers to 8PSK (8-ary Phase Shift Keying), 16QAM (16-ary Quadrature Amplitude Modulation) and 64QAM modulations as 2m-ary modulation having a higher modulation level than QPSK (Quadrature Phase Shift Keying) modulation. When generating modulated bits using the multi-level modulation, there occurs a difference in reliability between a plurality of bits constituting each modulated bit. Due to the reliability difference, the respective bits have different average bit error rates.
Meanwhile, when an encoder comprised of a plurality of system encoders, such as a turbo encoder, is used as a channel encoder, codeword bits from the system encoders are divided into a systematic part, a stream of bits with higher priority (importance), and a parity part, a stream of bits with lower priority. In the case where one information sequence is input to a plurality of constituent encoders, a decrease in a bit error rate of bits belonging to the systematic part of the codeword bits may result in a decrease in an average bit error rate and an average packet error rate of an information sequence output from a channel decoder. That is, when the codeword bits belonging to the systematic part with higher priority assuredly have higher reliability than the codeword bits belonging to the parity part with lower priority, it is possible to expect a performance improvement in terms of an error rate of an information sequence generated after decoding.
It is, therefore, an object of the present invention to provide a method and apparatus for rearranging bits of a codeword sequence output from a channel encoder before modulation, such that bits belonging to a systematic part with higher priority are arranged in bit positions with higher reliability of a modulated bit, in a communication system using multi-level modulation.
It is another object of the present invention to provide a method and apparatus for rearranging bits of a codeword sequence output from a channel encoder before modulation, such that bits belonging to a systematic part with higher priority are arranged in bit positions with higher reliability of a modulated bit, and arranging a demodulated bit in the order of an original codeword sequence, in a communication system using multi-level modulation.
It is further another object of the present invention to provide a method and apparatus for improving an average bit error rate and an average packet error rate of an information sequence generated after decoding, in a communication system.
To achieve the above and other objects, there is provided a method and apparatus for mapping a stream of bits output from an encoder to a stream of bits for 2m-ary modulation. The method and apparatus divides the stream of bits from the encoder into a first period and a second period. The first period includes bits with higher priority in the stream of the bits output from the encoder, and the second period includes bits with lower priority. The method and apparatus maps the bits existing in the first period to bit positions with higher reliability in a stream of m bits representing each of the bits for 2m-ary modulation, and maps the bits existing in the second period to bit positions with lower reliability in the stream of m bits.
The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings in which:
A preferred embodiment of the present invention will be described herein below with reference to the accompanying drawings. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail.
The present invention provides (1) a method for rearranging bits of a codeword sequence output from a channel encoder before modulation such that the bits with higher reliability, such as the bits belonging to a systematic part, are arranged in positions with higher reliability among the bits constituting a modulated bit, in a communication system using multi-level modulation/demodulation such as 8PSK, 16QAM and 64QAM having a higher modulation level than QPSK, (2) a method for arranging output values of a demodulator in original positions of the codeword sequence, and (3) an apparatus for performing the methods. If a channel interleaver is not used in the following stage of the channel encoder or if, though a channel interleaver is used, an interleaved sequence can be divided into a systematic part with higher priority and a parity part with lower priority, then the present invention can improve system performance by utilizing a method for rearranging output bits of the channel encoder or the channel interleaver before modulation by taking into consideration a reliability difference between bits in the multi-level modulation/demodulation, and by arranging output values of a demodulator in the original positions before channel decoding or channel deinterleaving. Herein, first, a description will be made of a transmission apparatus for rearranging a codeword sequence according to an embodiment of the present invention, and a reception apparatus corresponding to the transmission apparatus. Next, an operation of rearranging a codeword sequence according to different embodiments of the present invention will be described. The description of the codeword sequence rearranging operation will be made from two different perspectives. Embodiments A-1, A-2, A-3, B-1, B-2 and B-3 based on a first perspective demonstrate how the codeword sequence rearranging operation is performed from the perspective of the codeword sequences. Embodiments C-1, C-2, C-3, D-1, D-2 and D-3 based on a second perspective demonstrate how the codeword sequence rearranging operation is performed from the perspective of the modulated bits. The embodiments based on the first perspective will be described on the assumption that the codeword sequence has N bits, and the embodiments based on the second perspective will be described on the assumption that the number of modulated bits is N. Although the codeword sequence rearranging operation according to the present invention will be described from two different perspectives, it should be noted that both operations are substantially identical to each other. Finally, performance of the codeword sequence rearranging operation according to the present invention will be analyzed.
Referring to
Before a detailed description of the present invention, reference will be made to how the sequence mapper 130 according to the present invention maps (or constellates) the input codeword sequence according to the modulation techniques. The codeword sequence may be either a codeword sequence directly output from the channel encoder 110 of
During modulation, the codeword sequence output from the channel encoder 110 is divided by m bits, and then constellated to a specific signal point among M=2m signal points according to, for example, Gray coding rule. This can be expressed by
In Equation (1), si (i=0, 1, . . . , m−1) represents an (i+1)th bit of the codeword sequence output from the channel encoder, constellated to one modulated bit. Further, I and Q represent an in-phase component and a quadrature-phase component of the corresponding modulated bit, respectively. In the case of 8PSK modulation, m=3. In the case of 16QAM and 64QAM modulations, m=4 and 6, respectively.
In the multi-level modulation, reliabilities between bits constituting one modulated bit are different from one another. This is because error probabilities due to a distance difference up to a region where each bit value of the modulated bit constellated to a specific position on the I-Q plane can be inverted by noises that are different from one another. Due to this phenomenon, LLRs (Log Likelihood Ratios) of the respective bits have different values, causing a reduction in performance of the channel decoder that expects soft values for the bits having the same error rate.
In the case of 8PSK, 2 of 3 bits constituting one modulated bit have the same reliability, whereas the remaining one bit has lower reliability than the other bits. For example, when a signal constellation diagram for 8PSK of
First, a description will be made of an operation of rearranging bits of a codeword sequence output from a channel encoder or a channel interleaver before modulation.
A fundamental principle of rearrangement according to the present invention is to rearrange the codeword sequence output from the channel encoder or the channel interleaver such that as many bits with higher priority as possible, such as the codeword bits belonging to a systematic part, are arranged in the bit positions with higher reliability of the bits representing a modulated bit. Bit rearrangement on the codeword sequence to be performed before generation of the modulated bit can be differently applied depending on the form of power to be allocated to the codeword sequence, observing the above principle.
A description of the bit rearrangement operation according to embodiments of the present invention will be separately made for one case where power is uniformly allocated to the codeword sequence and another case where different power levels are allocated to the front part and the rear part of the codeword sequence. Further, a description of each case will be separately made for 8PSK, 16QAM and 64QAM. In the following description of the bit rearrangement operation, it will be assumed that one codeword sequence is comprised of N bits, and N is a multiple of 3 for 8PSK modulation, a multiple of 4 for 16QAM modulation, and a multiple of 6 for 64QAM modulation. In addition, the codeword sequence before rearrangement is represented by {d0,d1, . . . , dk, . . . , dN−2,dN−1}, and the codeword sequence after rearrangement is represented by {d0,b1, . . . ,bk, . . . ,bN−2,bN−1}. Moreover, it will be assumed that the codeword sequence before rearrangement, i.e., the output codeword sequence of the channel encoder or the channel interleaver is arranged in the order of the systematic part and the parity part. If the codeword sequence is not arranged in the order of the systematic part and the parity part, a separate straightforward pre-processing to achieve this ordering is performed first.
When the power is uniformly allocated to the codeword sequence, it is possible to achieve performance improvement in terms of an average packet error rate by utilizing the intact rearrangement principle.
As mentioned before, 2 of 3 bits constituting one 8PSK-modulated bit have higher reliability than the remaining 1 bit. If it is assumed that the signal constellation diagram of
1. For the bits in a first period, the sequence mapper 130 sequentially maps first to {(2/3)×N}th bits to positions of a second bit s1 and a third bit s2 in each of (N/3) modulated bits.
2. For the bits in a second period, the sequence mapper 130 sequentially maps the remaining {(2/3)×N+1}th to Nth bits to a position of a first bit s0 in each of (N/3) modulated bits.
These processes are summarized into Equations (2) and (3). The bits of the codeword sequence before rearrangement are rearranged as shown in FIG. 9.
b3×└k/2┘+(k mod 2)+1=dk, for k<(2/3)×N (2)
b(3×k)−(2×N)=dk, for k≧(2/3)×N (3)
In the Equations (2) and (3), ‘A mod B’ indicates a remainder obtained by dividing A by B, and └X┘ indicates a maximum integer less than X.
A first bit d0 in the first period of the codeword sequence is mapped to a second bit position m0,s1 (i.e. b1) of a first modulated bit, and a second bit d1 in the first period of the codeword sequence is mapped to a third bit position m0,s2 (i.e. b2) of the first modulated bit. A third bit d2 in the first period is mapped to a second bit position m1,s1 (i.e. b4) of a second modulated bit, and a fourth bit d3 in the first period is mapped to a third bit position m1,s2 (i.e. b5) of the second modulated bit. A {(2/3)×N−1}th bit d2N/3−2 in the first period is mapped to a second bit position mN/3−1,s1 (i.e. bN−2) of an (N/3)th modulated bit, the last modulated bit, and a {(2/3)×N}th bit d2N/3−1, the last bit in the first period is mapped to a third bit position mN/3−1,s2 (i.e. bN−1) of the last modulated bit.
A {(2/3)×N+1}th bit d2N/3, a first bit in the second period is mapped to a first bit position m0,s0 (i.e. b0) of the first modulated bit, and a {(2/3)×N+2}th bit d2N/3+1, a second bit in the second period is mapped to a first bit position m1,s0 of the second modulated bit. An (N−1)th bit dN−2 in the second period is mapped to a first bit position mN/3−2,s0 (i.e. bN−6) of an {N/3−1}th modulated bit, and an Nth bit dN−1, the last bit in the second period is mapped to a first bit position mN/3−1,s0 (i.e. bN−3) of an (N/3)th modulated bit, the last modulated bit.
Referring to
As mentioned before, 2 of 4 bits constituting one 16QAM-modulated bit have higher reliability than the remaining 2 bits. If it is assumed that the signal constellation diagram of
1. For the bits in a first period, the sequence mapper 130 sequentially maps first to {(1/2)×N}th bits to positions of a second bit s1 and a fourth bit s3 in each of (N/4) modulated bits.
2. For the bits in a second period, the sequence mapper 130 sequentially maps the remaining {(1/2)×N+1}th to Nth bits to positions of a first bit s0 and a third bit s2 in each of (N/4) modulated bits.
These processes are summarized into Equations (4) and (5). The bits of the codeword sequence before rearrangement are rearranged as shown in FIG. 11.
b(2×k)−(0×N)+1=dk, for k<(1/2)×N (4)
b(2×k)−(1×N)+0=dk, for k≧(1/2)×N (5)
A first bit d0 in the first period of the codeword sequence is mapped to a second bit position m0,s1 (i.e. b1) of a first modulated bit, and a second bit d1 in the first period is mapped to a fourth bit position m0,s3 (i.e. b3) of the first modulated bit. A third bit d2 in the first period is mapped to a second bit position m1,s1 (i.e. b5) of a second modulated bit, and a fourth bit d3 in the first period is mapped to a fourth bit position m1,s3 (i.e. b7) of the second modulated bit. A {(1/2)×N−1}th bit dN/2−2 in the first period is mapped to a second bit position mN/4−1,s1 i.e. bN−3) of an (N/4)th modulated bit, the last modulated bit, and a {(1/2)×N}th bit dN/2−1, the last bit in the first period is mapped to a fourth bit position mN/4−1,s3 (i.e. bN−1) of the last modulated bit.
A {(1/2)×N+1}th bit dN/2, a first bit in the second period of the codeword sequence is mapped to a first bit position m0,s0 (i.e. b0) of the first modulated bit, a {(1/2)×N+2}th bit dN/2+1, a second bit in the second period is mapped to a third bit position m0,s2 (i.e. b2) of the first modulated bit. An (N−1)th bit dN−2 in the second period is mapped to a first bit position mN/4−1,s0 (i.e. bN−4) of an {N/4}th modulated bit, the last modulated bit, and an Nth bit dN−1, the last bit in the second period is mapped to a third bit position mN/4−1,s2 (i.e. bN−2) of an (N/4)th modulated bit.
Referring to
As mentioned before, 2 of 6 bits constituting one 64QAM-modulated bit have higher reliability than the remaining 2 pairs of the bits. If it is assumed that the signal constellation diagram of
1. For the bits in a first period, the sequence mapper 130 sequentially maps first to {(1/3)×N}th bits to positions of a third bit s2 and a sixth bit s5 in each of (N/6) modulated bits.
2. For the bits in a second period, the sequence mapper 130 sequentially maps {(1/3)×N+1}th to {(2/3)×N}th bits to positions of a second bit s1 and a fifth bit s4 in each of (N/6) modulated bits.
3. For the bits in a third period, the sequence mapper 130 sequentially maps the remaining {(2/3)×N+1}th to Nth bits to positions of a first bit s0 and a fourth bit s3 in each of (N/6) modulated bits.
These processes are summarized into Equations (6) to (8). The bits of the codeword sequence before rearrangement are rearranged as shown in FIG. 13.
b(3×k)−(0×N)+2=dk, for k<(1/3)×N (6)
b(3×k)−(1×N)+1=dk, for (1/3)×N≦k<(2/3)×N (7)
b(3×k)−(2×N)+0=dk, for k≧(2/3)×N (8)
A first bit d0 in the first period of the codeword sequence is mapped to a third bit position m0,s2 (i.e. b2) of a first modulated bit, and a second bit d1 in the first period is mapped to a sixth bit position m0,s5 (i.e. b5) of the first modulated bit. A third bit d2 in the first period is mapped to a third bit position m1,s2 (i.e. b8) of a second modulated bit, and a fourth bit d3 in the first period is mapped to a sixth bit position m1,s5 (i.e. b11) of the second modulated bit. A {(1/3)×N−1}th bit dN/3−2 in the first period is mapped to a third bit position mN/6−1,s2 (i.e. bN−4) of an (N/6)th modulated bit, the last modulated bit, and a {(1/3)×N}th bit dN/3−1, the last bit in the first period is mapped to a sixth bit position mN/6−1,s5 (i.e. bN−1) of the last modulated bit.
A {(1/3)×N+1}th bit dN/3, a first bit in the second period of the codeword sequence is mapped to a second bit position m0,s1 (i.e. b1) of the first modulated bit, and a {(1/3)×N+2}th bit dN/3+1, a second bit in the second period is mapped to a fifth bit position m0,s4 (i.e. b4) of the first modulated bit. A {(2/3)×N−1}th bit d2N/3−2 in the second period of the codeword sequence is mapped to a second bit position mN/6−1,s1 (i.e. bN−5) of the (N/6)th modulated bit, the last modulated bit, and a {(2/3)×N}th bit d2N/3−1, the last bit in the second period is mapped to a fifth bit position mN/6−1,s4 (i.e. bN−2) of the last modulated bit.
A {(2/3)×N+1}th bit d2N/3, a first bit in the third period of the codeword sequence is mapped to a first bit position m0,s0 (i.e. b0) of the first modulated bit, and a {(2/3)×N+2}th bit d2N/3+1, a second bit in the third period is mapped to a fourth bit position b0,s3 of the first modulated bit. An (N−1)th bit dN−2 in the third period of the codeword sequence is mapped to a first bit position mN/6−1,s0 (i.e. bN−6) of the (N/6)th modulated bit, the last modulated bit, and an Nth bit dN−1, the last bit in the fourth period is mapped to a third bit position mN/6−1,s3 (i.e. bN−3) of the last modulated bit.
Referring to
A description of an operation for the case where the power is non-uniformly allocated to the codeword sequence can be separately made for the following two cases.
In a first case, a higher power level is applied to the front part of the codeword sequence, while a lower power level is applied to the rear part of the codeword sequence. Such power allocation is illustrated in
In a second case, to the contrary, a lower power level is applied to the front part of the codeword sequence, while a higher power level is applied to the rear part of the codeword sequence. Such power allocation is illustrated in
1. For the bits in a first period, the sequence mapper 130 maps, in reverse order, first to {(2/3)×N}th bits to positions of a third bit s2 and a second bit s1 in each of (N/3) modulated bits.
2. For the bits in a second period, the sequence mapper 130 maps, in reverse order, the remaining {(2/3)×N+1}th to Nth bits to a position of a first bit s0 in each of (N/3) modulated bits.
These processes are summarized into Equations (9) and (10). The bits of the codeword sequence before rearrangement are rearranged as shown in FIG. 15.
b1×(N−1)−(3×└k/2┘+(k mod 2))=dk, for k<(2/3)×N (9)
b3×(N−1)−3×k=dk, for k≧(2/3)×N (10)
A first bit d0 in the first period of the codeword sequence is mapped to a third bit position mN/3−1,s2 (i.e. bN−1) of an (N/3)th modulated bit, the last modulated bit, and a second bit d1 in the first period of the codeword sequence is mapped to a second bit position mN/3−1,s1 (i.e. bN−2) of the last modulated bit. A third bit d2 in the first period is mapped to a third bit position mN/3−2,s2 (i.e. bN−4) of an {(N/3)−1}th modulated bit, and a fourth bit d3 in the first period is mapped to a second bit position mN/3−2,s1 (i.e. bN−5) of the {(N/3)−1}th modulated bit. A {(2/3)×N−1}th bit d2N/3−2 in the first period is mapped to a third bit position m0,s2 (i.e. b2) of a first modulated bit, and a {(2/3)×N}th bit d2N/3−1, the last bit in the first period is mapped to a second bit position m0,s1 (i.e. b1) of the first modulated bit.
A {(2/3)×N+1}th bit d2N/3, a first bit in the second period of the codeword sequence is mapped to a first bit position mN/3−1,s0 (i.e. bN−3) of an (N/3)th modulated bit, the last modulated bit, and a {(2/3)×N+2}th bit d2N/3+1, a second bit in the second period is mapped to a first bit position mN/3−2,s0 (i.e. bN−6) of an {(N/3)−1}th modulated bit. An (N−1)th bit dN−2 in the second period is mapped to a first bit position m1,s0 (i.e. b3) of a second modulated bit, and an Nth bit dN−1, the last bit in the second period is mapped to a first bit position m0,s0 (i.e. b0) of a first modulated bit.
Referring to
1. The sequence mapper 130 arranges the output codeword sequence of the channel encoder or the channel interleaver in the order of the systematic part and the parity part.
2. For the bits in a first period, the sequence mapper 130 maps, in reverse order, first to {(1/2)×N}th bits to positions of a fourth bit s3 and a second bit s1 in each of (N/4) modulated bits.
3. For the bits in a second period, the sequence mapper 130 maps, in reverse order, the remaining {(1/2)×N+1}th to Nth bits to positions of a third bit s2 and a first bit s0 in each of (N/4) modulated bits.
These processes are summarized into Equations (11) and (12). The bits of the codeword sequence before rearrangement are rearranged as shown in FIG. 17.
b1×(N−1)−2×k=dk, for k<(1/2)×N (11)
b2×(N−1)−2×k=dk, for k≧(1/2)×N (12)
A first bit d0 in the first period of the codeword sequence is mapped to a fourth bit position mN/4−1,s3 (i.e. bN−1) of an (N/4)th modulated bit, the last modulated bit, and a second bit d1 in the first period of the codeword sequence is mapped to a second bit position mN/4−1,s1 (i.e. bN−3) of the last modulated bit. A third bit d2 in the first period is mapped to a fourth bit position mN/4−2,s3 (i.e. bN−5) of an {(N/4)−1}th modulated bit, and a fourth bit d3 in the first period is mapped to a second bit position mN/4−2,s1 (i.e. bN−7) of the {(N/4)−1}th modulated bit. A {(1/2)×N−1}th bit dN/2−2 in the first period is mapped to a fourth bit position m0,s3 (i.e. b3) of a first modulated bit, and a {(1/2)×N}th bit dN/2−1, the last bit in the first period is mapped to a second bit position m0,s1 (i.e. b1) of the first modulated bit.
A {(1/2)×N+1}th bit dN/2, a first bit in the second period of the codeword sequence is mapped to a third bit position mN/4−1,s2 (i.e. bN−2) of an (N/4)th modulated bit, the last modulated bit, and a {(1/2)×N+2}th bit dN/2+1, a second bit in the second period is mapped to a first bit position mN/4−1,s0 (i.e. bN−4) of the last modulated bit. An (N−1)th bit dN−2 in the second period is mapped to a third bit position m0,s2 (i.e. b2) of a first modulated bit, and an Nth bit dN−1, the last bit in the second period is mapped to a first bit position m0,s0 (i.e. b0) of the first modulated bit.
Referring to
1. For the bits in a first period, the sequence mapper 130 maps, in reverse order, first to {(1/3)×N}th bits to positions of a sixth bit s5 and a third bit s2 in each of (N/6) modulated bits.
2. For the bits in a second period, the sequence mapper 130 maps, in reverse order, {(1/3)×N+1}th to {(2/3)×N}th bits to positions of a fifth bit s4 and a second bit s1 in each of (N/6) modulated bits.
3. For the bits in a third period, the sequence mapper 130 maps, in reverse order, the remaining {(2/3)×N+1}th to Nth bits to positions of a fourth bit s3 and a first bit s0 in each of (N/6) modulated bits.
These processes are summarized into Equations (13) to (15). The bits of the codeword sequence before rearrangement are rearranged as shown in FIG. 19.
b1×(N−1)−3×k=dk, for k<(1/3)×N (13)
b2×(N−1)−3×k=dk, for (1/3)×N≦k<(2/3)×N (14)
b3×(N−1)−3×k=dk, for k≧(2/3)×N (15)
A first bit d0 in the first period of the codeword sequence is mapped to a sixth bit position mN/6−1,s5 (i.e. bN−1) of an (N/6)th modulated bit, the last modulated bit, and a second bit d1 in the first period is mapped to a third bit position mN/6−1,s2 (i.e. bN−4) of the last modulated bit. A third bit d2 in the first period is mapped to a sixth bit position mN/6−2,s5 (i.e. bN−7) of an {(N/6)−1}th modulated bit, and a fourth bit d3 in the first period is mapped to a third bit position mN/6−2,s2 (i.e. bN−10) of the {(N/6)−1}th modulated bit. A {(1/3)×N−1}th bit dN/3−2 in the first period is mapped to a sixth bit position m0,s5 (i.e. b5) of a first modulated bit, and a {(1/3)×N}th bit dN/3−1, the last bit in the first period is mapped to a third bit position m0,s2 (i.e. b2) of the first modulated bit.
A {(1/3)×N+1}th bit dN/3, a first bit in the second period of the codeword sequence is mapped to a fifth bit position mN/6−1,s4 (i.e. bN−2) of an (N/6)th modulated bit, the last modulated bit, and a {(1/3)×N+2}th bit dN/3+1, a second bit in the second period is mapped to a second bit position mN/6−1,s1 (i.e. bN−5) of the last modulated bit. A {(2/3)×N−1}th bit d2N/3−2 in the second period of the codeword sequence is mapped to a fifth bit position m0,s4 (i.e. b4) of a first modulated bit, and a {(2/3)×N}th bit d2N/3−1, the last bit in the second period is mapped to a second bit position m0,s1 (i.e. b1) of the first modulated bit.
A {(2/3)×N+1}th bit d2N/3, a first bit in the third period of the codeword sequence is mapped to a fourth bit position mN/6−1,s3 (i.e. bN−3) of an (N/6)th modulated bit, the last modulated bit, and a {(2/3)×N+2}th bit d2N/3+1, a second bit in the third period is mapped to a first bit position mN/6−1,s0 (i.e. bN−6) of the last modulated bit. An (N−1)th bit dN−2 in the third period of the codeword sequence is mapped to a fourth bit position m0,s3 (i.e. b3) of a first modulated bit, and an Nth bit dN−1, the last bit in the third period is mapped to a first bit position m0,s0 (i.e. b0) of the first modulated bit.
Referring to
Heretofore, the description has been made of the operation of rearranging the output codeword sequence bits of the channel encoder or the channel interleaver before modulation according to the embodiments of the present invention. Next, a description will be made of an operation of arranging output values of a demodulator in the order of the original codeword sequence before channel decoding or channel deinterleaving.
The operation of arranging the output values of the demodulator in the order of the original codeword sequence is achieved by performing the above-described rearranging operation in reverse. If an output sequence of the demodulator is represented by {q0,q1, . . . ,qk, . . . ,qN−2,qN−1}, the sequence arranged in the original order before channel decoding or channel deinterleaving is represented by {p0,p1, . . . ,pk, . . . ,pN−2,pN−1}, a subscript of the left term b in Equation (2) to (15) is represented by m, and a subscript of the right term d is represented by n, then a process of arranging output sequence values of the demodulator in the original order before channel decoding or channel deinterleaving can be expressed by
qmpn, for all m and n (however, m and n ε{0,1, . . . ,N−1}) (16)
A description of the bit rearrangement operation according to embodiments of the present invention will be separately made for one case where power is uniformly allocated to the codeword sequence and another case where different power levels are allocated to the front part and the rear part of the codeword sequence. Further, a description of each case will be separately made for 8PSK, 16QAM and 64QAM. In the following description of the bit rearrangement operation, it will be assumed that the number of modulated bits constituting one modulated bit sequence is N, and a codeword sequence before rearrangement, i.e., an output sequence of the channel encoder or a channel interleaver is represented by {X(0), . . . ,X(k), . . . ,X(N×m−1)}, and a codeword sequence after rearrangement is represented by s0(i), . . . ,sm−1(i), where i□{0, . . . ,N−1}. Moreover, it will be assumed that the codeword sequence before rearrangement is arranged in the order of the systematic part and the parity part. If the codeword sequence is not arranged in the order of the systematic part and the parity part, straightforward pre-processing is included to arrange the sequence in this order.
When the power is uniformly allocated to the codeword sequence, it is possible to achieve performance improvement in terms of an average packet error rate by utilizing the intact rearrangement principle.
As mentioned before, 2 of 3 bits constituting one 8PSK-modulated bit have higher reliability than the remaining 1 bit. If it is assumed that the signal constellation diagram of
1. For the bits in a first period, the sequence mapper 130 sequentially maps first to {2×N}th bits to positions of a second bit s1 and a third bit s2 in each of N modulated bits.
2. For the bits in a second period, the sequence mapper 130 sequentially maps the remaining {2×N+1}th to {3×N}th bits to a position of a first bit s0 in each of N modulated bits.
These processes are summarized into Equations (17) to (19). The bits of the codeword sequence before rearrangement are rearranged as shown in FIG. 21.
s0(i)=x(2×N+i) (17)
s1(i)=x(2×i) (18)
s2(i)=x(2×i+1) (19)
Referring to
A first bit x(2N) in the second period of the codeword sequence is mapped to a first bit position s0(0) of a first modulated bit, a first bit x(0) in the first period of the codeword sequence is mapped to a second bit position s1(0) of the first modulated bit, and a second bit x(1) in the first period of the codeword sequence is mapped to a third bit position s2(0) of the first modulated bit.
A second bit x(2N+1) in the second period of the codeword sequence is mapped to a first bit position s0(1) of a second modulated bit, a third bit x(2) in the first period of the codeword sequence is mapped to a second bit position s1(1) of the second modulated bit, and a fourth bit x(3) in the first period of the codeword sequence is mapped to a third bit position s2(1) of the second modulated bit.
A third bit x(2N+2) in the second period of the codeword sequence is mapped to a first bit position s0(2) of a third modulated bit, a fifth bit x(4) in the first period of the codeword sequence is mapped to a second bit position s1(2) of the third modulated bit, and a sixth bit x(5) in the first period of the codeword sequence is mapped to a third bit position s2(2) of the third modulated bit.
A {3N−1}th bit x(3N−2) in the second period of the codeword sequence is mapped to a first bit position s0(N−2) of an (N−1)th modulated bit, a {2N−3}th bit x(2N−4) in the first period of the codeword sequence is mapped to a second bit position s1(N−2) of the (N−1)th modulated bit, and a {2N−2}th bit x(2N−3) in the first period of the codeword sequence is mapped to a third bit position s2(N−2) of the (N−1)th modulated bit.
A {3×N}th bit x(3N−1) in the second period of the codeword sequence is mapped to a first bit position s0(N−1) of an Nth modulated bit, a {2N−1}th bit x(2N−2) in the first period of the codeword sequence is mapped to a second bit position s1(N−1) of the Nth modulated bit, and a {2×N}th bit x(2N−1) in the first period of the codeword sequence is mapped to a third bit position s2(N−1) of the Nth modulated bit.
Referring to
As mentioned before, 2 of 4 bits constituting one 16QAM-modulated bit have higher reliability than the remaining 2 bits. If it is assumed that the signal constellation diagram of
1. For the bits in a first period, the sequence mapper 130 sequentially maps first to {2×N}th bits to positions of a second bit s1 and a fourth bit s3 in each of N modulated bits.
2. For the bits in a second period, the sequence mapper 130 sequentially maps the remaining {2×N+1}th to {4×N}th bits to positions of a first bit s0 and a third bit s2 in each of N modulated bits.
These processes are summarized into Equations (20) to (23). The bits of the codeword sequence before rearrangement are rearranged as shown in FIG. 23.
s0(i)=x(2×N+2×i) (20)
s1(i)=x(2×i) (21)
s2(i)=x(2×N+2×i+1) (22)
s3(i)=x(2×i+1) (23)
Referring to
A first bit x(2N) in the second period of the codeword sequence is mapped to a first bit position s0(0) of a first modulated bit, a first bit x(0) in the first period of the codeword sequence is mapped to a second bit position s1(0) of the first modulated bit, a second bit x(2N+1) n the second period of the codeword sequence is mapped to a third bit position s2(0) of the first modulated bit, and a second bit x(1) in the first period of the codeword sequence is mapped to a fourth bit position s3(0) of the first modulated bit.
A third bit x(2N+2) in the second period of the codeword sequence is mapped to a first bit position s0(1) of a second modulated bit, a third bit x(2) in the first period of the codeword sequence is mapped to a second bit position s1(1) of the second modulated bit, a fourth bit x(2N+3) in the second period of the codeword sequence is mapped to a third bit position s2(1) of the second modulated bit, and a fourth bit x(3) in the first period of the codeword sequence is mapped to a fourth bit position s3(1) of the second modulated bit.
A {4N−3}th bit x(4N−4) in the second period of the codeword sequence is mapped to a first bit position s0(N−2) of an (N−1)th modulated bit, a {2N−3}th bit x(2N−4) in the first period of the codeword sequence is mapped to a second bit position s1(N−2) of the (N−1)th modulated bit, a {4N−2}th bit x(4N−3) in the second period of the codeword sequence is mapped to a third bit position s2(N−2) of the (N−1)th modulated bit, and a {2N−2}th bit x(2N−3) in the first period of the codeword sequence is mapped to a fourth bit position s3(N−2) of the (N−1)th modulated bit.
A {4N−1}th bit x(4N−2) in the second period of the codeword sequence is mapped to a first bit position s0(N−1) of an Nth modulated bit, a {2N−1}th bit x(2N−2) in the first period of the codeword sequence is mapped to a second bit position s1(N−1) of the Nth modulated bit, a {4×N}th bit x(4N−1) in the second period of the codeword sequence is mapped to a third bit position s2(N−1) of the Nth modulated bit, and a {2×N}th bit x(2N−1) in the first period of the codeword sequence is mapped to a fourth bit position s3(N−1) of the Nth modulated bit.
Referring to
As mentioned before, 2 of 6 bits constituting one 64QAM-modulated bit have higher reliability than the remaining 2 pairs of the bits. If it is assumed that the signal constellation diagram of
1. For the bits in a first period, the sequence mapper 130 sequentially maps first to {2×N}th bits to positions of a third bit s2 and a sixth bit s5 in each of N modulated bits.
2. For the bits in a second period, the sequence mapper 130 sequentially maps {2×N+1}th to {4×N}th bits to positions of a second bit s1 and a fifth bit s4 in each of N modulated bits.
3. For the bits in a third period, the sequence mapper 130 sequentially maps the remaining {4×N+1}th to {6×N}th bits to positions of a first bit s0 and a fourth bit s3 in each of N modulated bits.
These processes are summarized into Equations (24) to (29). The bits of the codeword sequence before rearrangement are rearranged as shown in FIG. 25.
s0(i)=x(4×N+2×i) (24)
s1(i)=x(2×N+2×i) (25)
s2(i)=x(2×i) (26)
s3(i)=x(4×N+2×i+1) (27)
s4(i)=x(2×N+2×i+1) (28)
s5(i)=x(2×i+1) (29)
Referring to
A first bit x4N in the third period of the codeword sequence is mapped to a first bit position s0(0) of a first modulated bit, a first bit x(2N) in the second period of the codeword sequence is mapped to a second bit position s1(0) of the first modulated bit, a first bit x(0) in the first period of the codeword sequence is mapped to a third bit position s2(0) of the first modulated bit, a second bit x(4N+1) in the third period of the codeword sequence is mapped to a fourth bit position s3(0) of the first modulated bit, a second bit x(2N+1) in the second period of the codeword sequence is mapped to a fifth bit position s4(0) of the first modulated bit, and a second bit x(1) in the first period of the codeword sequence is mapped to a sixth bit position s5(0) of the first modulated bit.
A {6N−1}th bit x(6N−2) in the third period of the codeword sequence is mapped to a first bit position s0(N−1) of an Nth modulated bit, a {4N−1)}th bit x(4N−2) in the second period of the codeword sequence is mapped to a second bit position s1(N−1) of the Nth modulated bit, a {2N−1}th bit x(2N−2) in the first period of the codeword sequence is mapped to a third bit position s2(N−1) of the Nth modulated bit, a {6×N}th bit x(6N−1) in the third period of the codeword sequence is mapped to a fourth bit position s3(N−1) of the Nth modulated bit, a {4×N}th bit x(4N−1) in the second period of the codeword sequence is mapped to a fifth bit position s4(N−1) of the Nth modulated bit, and a {2×N}th bit x(2N−1) in the first period of the codeword sequence is mapped to a sixth bit position s5(N−1) of the Nth modulated bit.
Referring to
A description of an operation for the case where the power is non-uniformly allocated to the codeword sequence can be separately made for the following two cases.
In a first case, a higher power level is applied to the front part of the codeword sequence, while a lower power level is applied to the rear part of the codeword sequence. Such power allocation is illustrated in
In a second case, to the contrary, a lower power level is applied to the front part of the codeword sequence, while a higher power level is applied to the rear part of the codeword sequence. Such power allocation is illustrated in
1. For the bits in a first period, the sequence mapper 130 maps, in reverse order, first to {2×N}th bits to positions of a third bit s2 and a second bit s1 in each of N modulated bits.
2. For the bits in a second period, the sequence mapper 130 maps, in reverse order, the remaining {2×N+1}th to {3×N}th bits to a first bit position s0 in each of N modulated bits.
These processes are summarized into Equations (30) and (32). The bits of the codeword sequence before rearrangement are rearranged as shown in FIG. 27.
s0(N−1−i)=x(2×N+i) (30)
s1(N−1−i)=x(2×i+1) (31)
s2(N−1−i)=x(2×i) (32)
Referring to
A {3×N}th bit x(3N−1) in the second period of the codeword sequence is mapped to a first bit position s0(0) of a first modulated bit, a {2×N}th bit x(2N−1) in the first period of the codeword sequence is mapped to a second bit position s1(0) of the first modulated bit, and a {2×N−1}th bit x(2N−2) in the first period of the codeword sequence is mapped to a third bit position s2(0) of the first modulated bit.
A {3×N−1}th bit x(3N−2) in the second period of the codeword sequence is mapped to a first bit position s0(1) of a second modulated bit, a {2×N−2}th bit x(2N−3) in the first period of the codeword sequence is mapped to a second bit position s1(1) of the second modulated bit, and a {2×N−3}th bit x(2N−4) in the first period of the codeword sequence is mapped to a third bit position s2(1) of the second modulated bit.
A {3×N−2}th bit x(3N−3) in the second period of the codeword sequence is mapped to a first bit position s0(2) of a third modulated bit, a {2×N−4}th bit x(2N−5) in the first period of the codeword sequence is mapped to a second bit position s1(2) of the third modulated bit, and a {2×N−5}th bit x(2N−6) in the first period of the codeword sequence is mapped to a third bit position s2(2) of the third modulated bit.
A second bit x(2N+1) in the second period of the codeword sequence is mapped to a first bit position s0(N−2) of an {N−1}th modulated bit, a fourth bit x(3) in the first period of the codeword sequence is mapped to a second bit position s1(N−2) of the {N−1}th modulated bit, and a third bit x(2) in the first period of the codeword sequence is mapped to a third bit position s2(N−2) of the {N−1}th modulated bit.
A first bit x(2N) in the second period of the codeword sequence is mapped to a first bit position s0(N−1) of an Nth modulated bit, a second bit x(1) in the first period of the codeword sequence is mapped to a second bit position s1(N−1) of the Nth modulated bit, and a first bit x(0) in the first period of the codeword sequence is mapped to a third bit position s2(N−1) of the Nth modulated bit.
Referring to
1. For the bits in a first period, the sequence mapper 130 maps, in reverse order, first to {2×N}th bits to positions of a fourth bit s3 and a second bit s1 in each of N modulated bits.
2. For the bits in a second period, the sequence mapper 130 maps, in reverse order, the remaining {2×N+1}th to {4×N}th bits to positions of a third bit s2 and a first bit s0 in each of N modulated bits.
These processes are summarized into Equations (33) and (36). The bits of the codeword sequence before rearrangement are rearranged as shown in FIG. 17.
s0(N−1−i)=x(2×N+2×i+1) (33)
s1(N−1−i)=x(2×i+1) (34)
s2(N−1−i)=x(2×N+2×i) (35)
s3(N−1−i)=x(2×i) (36)
Referring to
A {4×N}th bit x(4N−1) in the second period of the codeword sequence is mapped to a first bit position s0(0) of a first modulated bit, a {2×N}th bit x(2N−1) in the first period of the codeword sequence is mapped to a second bit position s1(0) of the first modulated bit, a {4×N−1}th bit x(4N−2) in the second period of the codeword sequence is mapped to a third bit position s2(0) of the first modulated bit, and a {2×N−1}th bit x(2N−2) in the first period of the codeword sequence is mapped to a fourth bit position s3(0) of the first modulated bit.
A {4×N−2}th bit x(4N−3) in the second period of the codeword sequence is mapped to a first bit position s0(1) of a second modulated bit, a {2×N−2}th bit x(2N−3) in the first period of the codeword sequence is mapped to a second bit position s1(1) of the second modulated bit, a {4×N−3}th bit x(4N−4) in the second period of the codeword sequence is mapped to a third bit position s2(1) of the second modulated bit, and a {2×N−3}th bit x(2N−4) in the first period of the codeword sequence is mapped to a fourth bit position s3(1) of the second modulated bit.
A fourth bit x(2N+3) in the second period of the codeword sequence is mapped to a first bit position s0(N−2) of an {N−1}th modulated bit, a fourth bit x(3) in the first period of the codeword sequence is mapped to a second bit position s1(N−2) of the {N−1}th modulated bit, a third bit x(2N+2) in the second period of the codeword sequence is mapped to a third bit position s2(N−2) of the {N−1}th modulated bit, and a third bit x(2) in the first period of the codeword sequence is mapped to a fourth bit position s3(N−2) of the {N−1}th modulated bit.
A second bit x(2N+1) in the second period of the codeword sequence is mapped to a first bit position s0(N−1) of an Nth modulated bit, a second bit x(1) in the first period of the codeword sequence is mapped to a second bit position s1(N−1) of the Nth modulated bit, a first bit x(2N) in the second period of the codeword sequence is mapped to a third bit position s2(N−1) of the Nth modulated bit, and a first bit x(0) in the first period of the codeword sequence is mapped to a fourth bit position s3(N−1) of the Nth modulated bit.
Referring to
1. For the bits in a first period, the sequence mapper 130 maps, in reverse order, first to {2×N}th bits to positions of a sixth bit s5 and a third bit s2 in each of N modulated bits.
2. For the bits in a second period, the sequence mapper 130 maps, in reverse order, {2×N+1}th to {4×N}th bits to positions of a fifth bit s4 and a second bit s1 in each of N modulated bits.
3. For the bits in a third period, the sequence mapper 130 maps, in reverse order, the remaining {4×N+1}th to {6×N}th bits to positions of a fourth bit s3 and a first bit s0 in each of N modulated bits.
These processes are summarized into Equations (37) to (42). The bits of the codeword sequence before rearrangement are rearranged as shown in FIG. 31.
s0(N−1−i)=x(4×N+2×i+1) (37)
s1(N−1−i)=x(2×N+2×i+1) (38)
s2(N−1−i)=x(2×i+1) (39)
s3(N−1−i)=x(4×N+2×i) (40)
s4(N−1−i)=x(2×N+2×i) (41)
s5(N−1−i)=x(2×i) (42)
Referring to
A {6×N}th bit x(6N−1) in the third period of the codeword sequence is mapped to a first bit position s0(0) of a first modulated bit, a {4×N}th bit x(4N−1) in the second period of the codeword sequence is mapped to a second bit position s1(0) of the first modulated bit, a {2×N}th bit x(2N−1) in the first period of the codeword sequence is mapped to a third bit position s2(0) of the first modulated bit, a {6×N−1}th bit x(6N−2) in the third period of the codeword sequence is mapped to a fourth bit position s3(0) of the first modulated bit, a {4N−1}th bit x(4N−2) in the second period of the codeword sequence is mapped to a fifth bit position s4(0) of the first modulated bit, and a {2×N−1}th bit x(2N−2) in the first period of the codeword sequence is mapped to a sixth bit position s5(0) of the first modulated bit.
A second bit x(4N+1) in the third period of the codeword sequence is mapped to a first bit position s0(N−1) of an Nth modulated bit, a second bit x(2N+1) in the second period of the codeword sequence is mapped to a second bit position s1(N−1) of the Nth modulated bit, a second bit x(1) in the first period of the codeword sequence is mapped to a third bit position s2(N−1) of the Nth modulated bit, a first bit x(4N) in the third period of the codeword sequence is mapped to a fourth bit position s3(N−1) of the Nth modulated bit, a first bit x(2N) in the second period of the codeword sequence is mapped to a fifth bit position s4(N−1) of the Nth modulated bit, and a first bit x(0) in the first period of the codeword sequence is mapped to a sixth bit position s5(N−1) of the Nth modulated bit.
Referring to
Heretofore, the description has been made of the operation of rearranging the output codeword sequence bits of the channel encoder or the channel interleaver before modulation according to the embodiments of the present invention. Next, a description will be made of an operation of arranging output values of a demodulator in the order of the original codeword sequence before channel decoding or channel deinterleaving.
The operation of arranging the output values of the demodulator in the order of the original codeword sequence is achieved by performing the above-described rearranging operation in reverse. If an output sequence of the demodulator is represented by {t0(i), . . . ,tm−1(i)} (where iε{0, . . . ,N−1}) and the sequence arranged in the original order before channel decoding or channel deinterleaving is represented by {y0, . . . ,yk, . . . ,yN×m−1}, then a method of arranging output values of the demodulator in the original order before channel decoding or channel deinterleaving can be expressed by shifting the right terms of Equations (17) to (42) to the left terms while substituting ‘y’ for ‘x’, and shifting the left terms to the right terms while substituting ‘t’ for ‘s’. For example, Equation (42) can be changed to y(2×i)=t5(N−1−i), and used in arranging the output values of the demodulator in the original order.
It is noted from
As described above, the communication system using multi-level modulation having a higher modulation level than QPSK modulation according to the present invention rearranges output codeword sequence bits of the channel encoder or the channel interleaver before modulation, such that the bits belonging to a systematic part are arranged in bit positions with higher reliability of the bits constituting a multi-level modulated bit, and arranging output values of the demodulator in the original order before channel decoding or channel deinterleaving, thus contributing to an improvement in the average bit error rate and the average packet error rate. In addition, the sequence rearrangement method according to the present invention can be implemented without an increase in system complexity and time delay.
While the invention has been shown and described with reference to a certain preferred embodiment thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. For example, although the invention has been described with reference to the 8PSK, 16QAM and 64QAM modulations, the sequence rearrangement method according to the present invention can also be applied to other modulations.
Ahn, Seong-Woo, Kim, Min-goo, Ha, Sang-Hyuck
| Patent | Priority | Assignee | Title |
| 10148309, | Aug 05 2005 | Panasonic Corporation | Radio communication apparatus, and radio communication method |
| 10298286, | Aug 05 2005 | Panasonic Corporation | Integrated circuit |
| 10374854, | Dec 06 2005 | Microsoft Technology Licensing, LLC | Apparatus and method for transmitting data using a plurality of carriers |
| 10511343, | Aug 05 2005 | Panasonic Corporation | Integrated circuit |
| 10673483, | Aug 05 2005 | Panasonic Corporation | Communication system and communication method |
| 11469786, | Aug 04 2006 | PANASONIC HOLDINGS CORPORATION | Communication system and communication method |
| 11901929, | Aug 05 2005 | PANASONIC HOLDINGS CORPORATION | Communication system and communication method |
| 8340006, | Apr 12 2006 | Panasonic Corporation | Transmission of multicast/broadcast services in a wireless communication network |
| 9544008, | Aug 05 2005 | PANASONIC HOLDINGS CORPORATION | Integrated circuit |
| 9755689, | Aug 05 2005 | Panasonic Corporation | Integrated circuit |
| 9935673, | Aug 05 2005 | Panasonic Corporation | Radio communication apparatus, and radio communication method |
| Patent | Priority | Assignee | Title |
| 5291289, | Nov 16 1990 | North American Philips Corporation | Method and apparatus for transmission and reception of a digital television signal using multicarrier modulation |
| 5565926, | Aug 31 1993 | Philips Electronics North America Corporation | Method and apparatus for communicating digital television signals using a signal constellation formed by four signal constellations placed in the quadrants |
| 6115427, | Apr 26 1996 | AT&T Corp | Method and apparatus for data transmission using multiple transmit antennas |
| 6473878, | May 28 1999 | WSOU Investments, LLC | Serial-concatenated turbo codes |
| 6889355, | Apr 26 1996 | Ortho-McNeil Pharmaceutical, Inc | Method and apparatus for data transmission using multiple transmit antennas |
| 7016296, | Oct 16 2000 | AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LIMITED | Adaptive modulation for fixed wireless link in cable transmission system |
| 7151805, | Dec 23 1999 | ROHDE & SCHWARZ GMBH & CO KG | System for generating an analogue I/Q signal from two or more data streams |
| 20040049725, | |||
| EP485105, | |||
| EP1043858, | |||
| EP1189380, | |||
| EP1204256, | |||
| EP1235404, | |||
| JP66399, | |||
| WO74296, |
| Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
| Dec 22 2003 | Samsung Electronics Co., Ltd | (assignment on the face of the patent) | / |
| Date | Maintenance Fee Events |
| Nov 14 2008 | ASPN: Payor Number Assigned. |
| Aug 18 2011 | M1551: Payment of Maintenance Fee, 4th Year, Large Entity. |
| Aug 25 2011 | RMPN: Payer Number De-assigned. |
| Aug 26 2011 | ASPN: Payor Number Assigned. |
| Aug 19 2015 | M1552: Payment of Maintenance Fee, 8th Year, Large Entity. |
| Aug 15 2019 | M1553: Payment of Maintenance Fee, 12th Year, Large Entity. |
| Date | Maintenance Schedule |
| Mar 04 2011 | 4 years fee payment window open |
| Sep 04 2011 | 6 months grace period start (w surcharge) |
| Mar 04 2012 | patent expiry (for year 4) |
| Mar 04 2014 | 2 years to revive unintentionally abandoned end. (for year 4) |
| Mar 04 2015 | 8 years fee payment window open |
| Sep 04 2015 | 6 months grace period start (w surcharge) |
| Mar 04 2016 | patent expiry (for year 8) |
| Mar 04 2018 | 2 years to revive unintentionally abandoned end. (for year 8) |
| Mar 04 2019 | 12 years fee payment window open |
| Sep 04 2019 | 6 months grace period start (w surcharge) |
| Mar 04 2020 | patent expiry (for year 12) |
| Mar 04 2022 | 2 years to revive unintentionally abandoned end. (for year 12) |