A CMOS image sensor and fabricating method thereof enable enhanced photo-response characteristics and protect a microlens in packaging by embedding the microlens in a passivation layer pattern. The image sensor may include a semiconductor substrate, a photodiode, a metal line, an insulating layer, a passivation layer pattern, and a microlens formed to be embedded in the passivation layer pattern.
|
1. A method of fabricating a CMOS image sensor, comprising the steps of:
forming a photodiode in a semiconductor substrate;
forming a first insulating layer on the semiconductor substrate;
forming a metal line on the first insulating layer for electrically connecting to the photodiode;
forming a second insulating layer on an entire surface of the first insulating layer including the metal line;
forming a passivation layer pattern and a microlens material layer pattern on the second insulating layer
such that the microlens material layer pattern is embedded between the passivation layer pattern;
forming a photoresist pattern on the passivation layer pattern and the microlens material layer pattern;
forming an opening by selectively performing an etching using the photoresist pattern as a mask until an upper surface of a metal pad is exposed and removing the photoresist pattern; and
forming a microlens by performing reflowing on the microlens material layer pattern.
6. A method of fabricating a CMOS image sensor, comprising the steps of:
forming a photodiode in a semiconductor substrate defined by a pixel area and a peripheral area;
forming a first insulating layer on the semiconductor substrate;
forming a metal line on the first insulating layer of the pixel area and forming a metal pad on the first insulating layer of the peripheral area;
forming a second insulating layer on an entire surface of the first insulating layer including the metal line and the metal pad;
forming passivation layer patterns on the second insulating layer;
forming a microlens material layer on the second insulating layer including the passivation layer patterns;
forming microlens material layer patterns embedded between the passivation layer patterns by planarizing the microlens material layer until an upper surface of the passivation layer patterns are exposed;
forming a photoresist pattern on the passivation layer patterns including the microlens material layer patterns in order to expose the metal pad;
selectively etching, in the peripheral area, the microlens material layer pattern and the second insulating layer using the photoresist pattern as a mask until an upper surface of the metal pad is exposed and removing the photoresist pattern; and
forming at least one microlens by performing reflowing on the microlens material layer patterns of the pixel area.
2. The method of
forming a passivation layer on the second insulating layer;
forming the passivation layer pattern on the second insulating layer by selectively etching a portion of the passivation layer corresponding to an area for forming the microlens;
forming a microlens material layer on the second insulating layer including the passivation layer pattern;
forming the microlens material layer pattern embedded between the passivation layer pattern by planarizing the microlens material layer until an upper surface of the passivation layer pattern is exposed.
3. The method of
4. The method of
|
This application claims the benefit of Korean Patent Application No. 10-2004-0116428, filed on Dec. 30, 2004, which is hereby incorporated by reference for all purposes as if fully set forth herein.
1. Field of the Invention
The present invention relates to a CMOS image sensor and fabricating method thereof. Although the present invention is suitable for a wide scope of applications, it is particularly suitable for enhancing photo-response characteristics and protecting a microlens in packaging by embedding the microlens in a passivation layer pattern.
2. Discussion of the Related Art
An image sensor is a semiconductor device that converts an optical image to an electric signal. Image sensors can be classified into charge coupled devices (CCD) and CMOS (complementary metal oxide silicon) image sensors. In a CCD image sensor, a plurality of MOS (metal-oxide-metal) capacitors are arranged close to one another to transfer and store electric charge carriers. In a CMOS (complementary MOS) image sensor, a plurality of MOS transistors corresponding to the number of pixels are fabricated by CMOS technology using a control circuit and a signal processing circuit as peripheral circuits. A switching system of sequentially detecting outputs using the MOS transistors is also adopted.
Microlenses of the related art CMOS image sensor are formed on a passivation layer; thus, the microlenses are vulnerable to packaging. Hence, photo-response characteristics of the CMOS image sensor are degraded and overall process throughput is lowered.
A CMOS image sensor and fabricating method thereof according to a related art are explained with reference to the attached drawing as follows.
Referring to
A passivation insulating layer 19 may be formed of nitride. The passivation insulating layer 19 is planarized by CMP (chemical mechanical polishing) and is then selectively etched to form an opening 21 on the pad 17. A microlens material layer (not shown) is formed on the passivation insulating layer 19. A photoresist layer (not shown) is coated on the microlens material layer. The photoresist layer is patterned to form a photoresist pattern (not shown). The microlens material layer is selectively etched to form a microlens material layer pattern (not shown) using the photoresist pattern as a mask. Reflowing is carried out on the microlens material layer pattern by baking to form a spherical microlens 20.
However, the related art CMOS image sensor and fabricating method thereof have disadvantages. Since the microlens is formed on the passivation layer, the microlens can be damaged in subsequent packaging. Hence, a photo-response characteristic of a device is degraded and process throughput is lowered.
Accordingly, the present invention is directed to a CMOS image sensor and fabricating method thereof that substantially obviate one or more problems due to limitations and disadvantages of the related art.
An advantage of the present invention is to provide a CMOS image sensor and fabricating method thereof, in which a microlens is formed between patterns of a passivation layer.
Another advantage of the present invention is to provide a CMOS image sensor and fabricating method thereof, by which damaging of the microlens in a subsequent packaging can be prevented.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure and method particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described, a CMOS image sensor includes a semiconductor substrate, a photodiode in the semiconductor substrate, a metal line over the semiconductor substrate that electrically connects to the photodiode, an insulating layer on the semiconductor substrate that insulates the metal line, a passivation layer pattern on the insulating layer, and a microlens on the insulating layer that is embedded in the passivation layer pattern.
In another aspect of the present invention, a method of fabricating a CMOS image sensor includes the steps of forming a photodiode in a semiconductor substrate, forming a first insulating layer on the semiconductor substrate, forming a metal line on the first insulating layer for electrically connecting to the photodiode, forming a second insulating layer on an entire surface of the first insulating layer including the metal line, forming a passivation layer pattern on the second insulating layer, and forming a microlens on the second insulating layer such that the microlens is embedded in the passivation layer pattern.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate exemplary embodiment(s) of the invention and together with the description serve to explain the principles of the invention. In the drawings:
Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or similar parts.
Referring to
A first photoresist layer (not shown) is coated on the passivation layer 39. Exposure and development are performed on the first photoresist layer to form a first photoresist pattern 40 to expose portions of the passivation layer 39 corresponding to a microlens forming area and the pad 37, respectively.
Referring to
Referring to
Referring to
In an exemplary embodiment, the second opening 41b is formed by etching the portion of the passivation layer 39 corresponding to the pad area and the microlens material layer pattern is formed in the second opening 41b. The second opening 41b may be omitted. Since the portion of the passivation layer 39 corresponding to the pad area remains intact, the targets of the selective etch are the passivation layer 39 and the second insulating layer 38. Selective etching of these layers exposes the pad 37 using the second photoresist pattern 43 as a mask.
Referring to
By forming the self-aligned microlens 44 to be embedded in the passivation layer 39, a space margin between the microlenses 44 can be accurately secured to raise photo-efficiency.
The present invention provides the following effects. The self-aligned microlenses may be accurately arranged in a photo-shield layer to raise photo-efficiency. Also, the microlens is embedded in the passivation layer such that it is prevented from being damaged in packaging. Hence, photo-response characteristics of the device can be enhanced and the process throughput can be raised.
It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.
Patent | Priority | Assignee | Title |
Patent | Priority | Assignee | Title |
5324623, | Jun 04 1991 | Sony Corporation | Microlens forming method |
6577342, | Sep 25 1998 | Intel Corporation | Image sensor with microlens material structure |
6737626, | Aug 06 2001 | Pixim, Inc. | Image sensors with underlying and lateral insulator structures |
20040038443, | |||
20060141660, | |||
KR1020030001066, |
Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
Dec 28 2005 | LEE, SANG GI | DONGBUANAM SEMICONDUCTOR INC | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 017387 | /0814 | |
Dec 29 2005 | Dongbu Electronics Co., Ltd | (assignment on the face of the patent) | / | |||
Mar 24 2006 | DONGBUANAM SEMICONDUCTOR INC | DONGBU ELECTRONICS CO , LTD | CHANGE OF NAME SEE DOCUMENT FOR DETAILS | 018176 | /0351 | |
Jan 29 2015 | DONGBU ELECTRONICS CO , LTD | III Holdings 4, LLC | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 035383 | /0560 |
Date | Maintenance Fee Events |
Aug 21 2008 | ASPN: Payor Number Assigned. |
Sep 17 2009 | ASPN: Payor Number Assigned. |
Sep 17 2009 | RMPN: Payer Number De-assigned. |
Sep 20 2011 | M1551: Payment of Maintenance Fee, 4th Year, Large Entity. |
Apr 27 2015 | ASPN: Payor Number Assigned. |
Apr 27 2015 | RMPN: Payer Number De-assigned. |
Oct 27 2015 | M1552: Payment of Maintenance Fee, 8th Year, Large Entity. |
Oct 22 2019 | M1553: Payment of Maintenance Fee, 12th Year, Large Entity. |
Date | Maintenance Schedule |
May 27 2011 | 4 years fee payment window open |
Nov 27 2011 | 6 months grace period start (w surcharge) |
May 27 2012 | patent expiry (for year 4) |
May 27 2014 | 2 years to revive unintentionally abandoned end. (for year 4) |
May 27 2015 | 8 years fee payment window open |
Nov 27 2015 | 6 months grace period start (w surcharge) |
May 27 2016 | patent expiry (for year 8) |
May 27 2018 | 2 years to revive unintentionally abandoned end. (for year 8) |
May 27 2019 | 12 years fee payment window open |
Nov 27 2019 | 6 months grace period start (w surcharge) |
May 27 2020 | patent expiry (for year 12) |
May 27 2022 | 2 years to revive unintentionally abandoned end. (for year 12) |