Low cost apparatus and methods of detecting arc faults for better discriminating electrical events. The arc fault detection apparatus includes a current sensor, a di/dt input sense circuit, a dv/dt input sense circuit, and a processing unit. The current sensor monitors a power line current, and provides high frequency components of the power line current to the di/dt input sense circuit. The dv/dt input sense circuit monitors a power line voltage. The di/dt and dv/dt input sense circuits generate signals carrying information relating to changes in the power line current and the power line voltage, respectively. The processing unit analyzes these changes in the power line current and the power line voltage to discriminate detected electrical arcing events from nuisance loads with increased accuracy.
|
1. arc fault detection apparatus, comprising:
a power input;
a processor integrated circuit (IC) including a first input, a second input, and at least two input protection diodes, the two input protection diodes being coupled to one another at a common node and connected in series between a supply voltage and ground, the first input being connected to the common node of the two input protection diodes;
a differential voltage input sense circuit operative to sense at least one differential voltage (dv/dt) signal associated with the power input, and to provide the dv/dt signal to the first input of the processor IC; and
a differential current input sense circuit operative to sense at least one differential current (di/dt) signal associated with the power input, and to provide the di/dt signal to the second input of the processor IC;
wherein the two input protection diodes of the processor IC form a zero-crossing detector operative to detect zero crossings of the dv/dt signal, and
wherein the processor IC is operative to measure the di/dt signal at times based on the detected zero crossings of the dv/dt signal, and to analyze the dv/dt signal and the di/dt signal based on at least one characteristic of the respective dv/dt and di/dt signals for determining whether the dv/dt and di/dt signal characteristics are indicative of an arc fault.
14. A method of detecting an arc fault, comprising the steps of:
sensing, by a differential voltage input sense circuit, at least one differential voltage (dv/dt) signal associated with a power input;
providing, by the differential voltage input sense circuit, the dv/dt signal to a first input of a processor integrated circuit (IC), the processor IC including the first input, a second input, and at least two input protection diodes, the two input protection diodes being coupled to one another at a common node and connected in series between a supply voltage and ground, the first input being connected to the common node of the two input protection diodes;
detecting, by a zero-crossing detector formed by the two input protection diodes of the processor IC, zero crossings of the dv/dt signal;
sensing, by a differential current input sense circuit, at least one differential current (di/dt) signal associated with the power input;
providing, by the differential current input sense circuit, the di/dt signal directly to the second input of the processor IC;
measuring, by the processor IC, the di/dt signal at times based on the detected zero crossings of the dv/dt signal; and
analyzing, by the processor IC, the dv/dt signal and the di/dt signal based on at least one characteristic of the respective dv/dt and di/dt signals for determining whether the dv/dt and di/dt signal characteristics are indicative of an arc fault.
2. The arc fault detection apparatus of
3. The arc fault detection apparatus of
4. The arc fault detection apparatus of
5. The arc fault detection apparatus of
6. The arc fault detection apparatus of
7. The arc fault detection apparatus of
8. The arc fault detection apparatus of
9. The arc fault detection apparatus of
10. The arc fault detection apparatus of
11. The arc fault detection apparatus of
12. The arc fault detection apparatus of
13. The arc fault detection apparatus of
15. The method of
16. The method of
17. The method of
18. The method of
19. The method of
20. The method of
21. The method of
22. The method of
23. The method of
24. The method of
|
N/A
N/A
The present invention relates generally to apparatus and methods for detecting arc faults, and more specifically to low cost arc fault detection apparatus and methods.
U.S. patent application Ser. No. 11/225,585 filed Sep. 13, 2005 entitled ARC FAULT DETECTION TECHNIQUE and assigned to the same assignee of the present invention (the '585 application) discloses an arc fault detection apparatus that has a reduced susceptibility to nuisance tripping. As disclosed in the '585 application, the arc fault detection apparatus comprises an analog front end including a current sensor, an input sense circuit, and an arcing sense circuit; a power supply; a tripping (firing) circuit; a processing unit; and, an electromechanical interface. The current sensor monitors an AC power line current input, and provides high frequency components of the AC current to the input sense circuit. Next, the input sense circuit filters and rectifies the AC signal at its input, and provides the rectified signal to the arcing sense circuit. The arcing sense circuit then provides a voltage level accumulated over a predetermined sampling period, and one or more digital signals indicative of possible electrical arcing events (i.e., di/dt events) occurring during the sampling period, to the processing unit. Next, the processing unit measures the voltage level, stores information relating to the measured voltages and the digital signals provided thereto, and processes the stored information using one or more algorithms to determine whether the signals resulted from an arc fault or a nuisance load. In the event the signals resulted from an arc fault, the processing unit activates the firing circuit to trip the electromechanical interface, thereby interrupting a power output to the load.
Although the arc fault detection apparatus disclosed in the '585 application can be successfully employed to detect and distinguish between electrical arcing and nuisance loads under a broad range of operating conditions, there is an increasing need for arc fault detection devices suitable for use in low cost applications. For example, such low cost arc fault detection devices might be employed in conjunction with cord sets for lamps or any other suitable household or industrial appliances. As described above, conventional arc fault detection apparatus typically include an analog front end configured to sense a differential input current (di/dt). However, such an analog front end is typically implemented using numerous discrete electrical and electronic components, which can significantly increase the total number of device components, the total cost of the components, and the cost of manufacturing the arc fault detection device. The increased number of discrete components included in the conventional arc fault detection apparatus can also lead to a reduction in the overall reliability of the device.
It would therefore be desirable to have low cost apparatus and methods of detecting arc faults. Such arc fault detection apparatus would include a reduced number of discrete electrical and electronic components. It would also be desirable to have low cost arc fault detection apparatus and methods that can better discriminate electrical arc faults from nuisance loads.
In accordance with the present invention, low cost apparatus and methods of detecting arc faults are provided for better discriminating electrical arc faults from nuisance loads. The presently disclosed arc fault detection apparatus has a lower cost because it includes a front end that can be implemented using a reduced number of discrete electrical and electronic components. In addition, the disclosed arc fault detection apparatus can better discriminate electrical arc faults from nuisance loads because, in response to the detection of a possible electrical arcing condition, it analyzes not only changes in the power line current (di/dt), but also changes in the power line voltage (dv/dt). It is noted that some electrical arcing events are characterized by high dv/dt conditions that can occur simultaneously with frequent levels of high di/dt. By analyzing changes in both the power line current (di/dt) and the power line voltage (dv/dt), the arc fault detection apparatus can discriminate such electrical events with increased accuracy.
In one embodiment, the low cost arc fault detection apparatus comprises a front end including a current sensor and a di/dt input sense circuit, and a processing unit. The current sensor includes a transformer, which monitors an AC power line current input and magnetically couples the high frequency components of the AC current from its primary coil to its secondary coil. The di/dt input sense circuit includes a rectifier circuit, which receives the high frequency AC current components from the current sensor, performs full wave or half wave rectification of the AC signal, and provides the rectified signal (the “di/dt signal”) to a first analog input of the processing unit for subsequent analysis. The low cost arc fault detection apparatus further comprises a dv/dt input sense circuit including a charging capacitor and a current limiting resistor, which are employed to derive a signal carrying information relating to changes in the power line voltage (the “dv/dt signal”). In this embodiment, the dv/dt signal is derived from the full wave rectified power line voltage. The dv/dt input sense circuit provides the dv/dt signal to a second analog input of the processing unit.
During a specified measurement period, the processing unit polls the voltage states of the di/dt and dv/dt signals provided by the di/dt and dv/dt input sense circuits, respectively, and generates a plurality of data streams from the information obtained therefrom. In the presently disclosed embodiment, the specified measurement period is equal to slightly less than one half of a cycle of the AC power mains. Next, the processing unit generates three data streams, specifically, a first data stream including information relating to the number of times the di/dt signal level exceeded a first specified voltage threshold, a second data stream including information relating to the number of times the dv/dt signal level exceeded a second specified voltage threshold, and a third data stream including information relating to the length of time the di/dt signal level exceeded the first specified threshold, during the specified measurement period. For example, the processing unit can generate the first and second data streams by counting the number of state transitions occurring at the first and second analog inputs, respectively. Further, the processing unit can generate the third data stream by accumulating the length of time that the di/dt signal remains in a particular state at the first analog input. After the measurement period expires, the processing unit stores the information relating to the first, second, and third data streams in memory.
Next, the processing unit analyzes the information included in the first, second, and third data streams generated during the most recent measurement period, and optionally analyzes the information included in data streams generated during one or more previous measurement periods. In the presently disclosed embodiment, the processing unit analyzes the first data stream(s) by determining the number of times the di/dt signal level exceeded the first specified threshold during the respective measurement periods. Specifically, the processing unit maintains a first running count of the number of times the di/dt signal level exceeded the first threshold during one or more successive measurement periods. In the event the first running count exceeds a first predetermined value, thereby indicating an electrical arcing condition, the processing unit activates a firing circuit to trip an electromechanical interface for interrupting a power output to a load. Similarly, the processing unit analyzes the second data stream(s) by determining the number of times the dv/dt signal level exceeded the second specified threshold during the respective measurement periods. Specifically, the processing unit maintains a second running count of the number of times the dv/dt signal level exceeded the second threshold during one or more successive measurement periods. In the event the second running count exceeds a second predetermined value, thereby indicating a possible electrical arcing condition, the processing unit adds a specified quantity to the first running count, thereby increasing the speed and likelihood of tripping the electromechanical interface to interrupt power output to the load.
The processing unit analyzes the third data stream by accumulating the length of time during one or more measurement periods that the di/dt signal remained in a particular state, and by evaluating the accumulated time relative to the first running count of the number of times the di/dt signal level exceeded the first threshold. In the event the accumulated time that the di/dt signal remained in a particular state is high relative to the number of times the di/dt signal level exceeded the first threshold, the processing unit inhibits the tripping of the electromechanical interface since such a condition may be indicative of a nuisance load.
Other features, functions, and aspects of the invention will be evident from the Detailed Description of the Invention that follows.
The invention will be more fully understood with reference to the following Detailed Description of the Invention in conjunction with the drawings of which:
Low cost apparatus and methods of detecting arc faults are disclosed that can better discriminate electrical arc faults from nuisance loads. The low cost arc fault detection apparatus includes a front end that can be implemented using a reduced number of discrete electrical and electronic components. In addition, in response to the detection of a possible electrical arcing condition, the low cost arc fault detection apparatus analyzes not only changes in the power line current (di/dt), but also changes in the power line voltage (dv/dt) to discriminate electrical events with increased accuracy.
The di/dt input sense circuit 102 includes resistors R1-R2, capacitors C0-C1, and diodes D1-D6. The secondary coil of the transformer TR1 is connected across the resistors R1-R2, which share a common node connection to ground. The resistors R1-R2 provide a ground reference for the secondary coil of the transformer TR1. The capacitor C1 and the diode D1 are connected in parallel with the resistor R1, and the capacitor C1 and the diode D2 are connected in parallel with the resistor R2. In addition, the cathode of the diode D1 is connected to the anodes of the diodes D3-D4, and the cathode of the diode D2 is connected to the anodes of the diodes D5-D6. The cathodes of the diodes D4-D5 are connected to ground, and the cathodes of the diodes D3 and D6 are connected to a node 114 providing the output of the di/dt input sense circuit 102. The diodes D1-D2 and D4-D5 are configured to form a full wave rectified bridge, and therefore the output provided at the node 114 is a full wave rectified signal. Further, the diodes D3-D6 and a capacitor C2 included in the arcing sense circuit 104 form a logging circuit, thereby causing the level of the output provided at the node 114 to be proportional to the log of the input of the di/dt input sense circuit 102.
The arcing sense circuit 104 includes the capacitor C2, an integrating capacitor C3, a bypass capacitor C4, resistors R4-R8, an operational amplifier (op amp) 116, and a diode D7. As shown in
The arcing sense circuit 104 receives the full wave rectified signal from the di/dt input sense circuit 102, and provides voltage levels accumulated over predetermined measurement periods to the analog input PA0 of the processing unit 112, which subsequently measures the voltage levels, stores information relating to the measured voltage levels, and processes the stored information using one or more algorithms to determine whether the high frequency components of the AC current provided by the current sensor 101 resulted from an electrical arc fault or a nuisance load. In the event the high frequency AC current components resulted from an arc fault, the processing unit activates a firing circuit (not shown) to trip an electromechanical interface, thereby interrupting the power output to the load. Because the conventional front end circuitry 100 of
As shown in
It should be noted that, in an alternative embodiment, the di/dt input sense circuit 202 may be configured to perform half wave rectification of the AC signal provided at the secondary coil of the transformer TR1. In addition, in further alternative embodiments, one or both of the rectifier circuit (including the diodes D8-D11) and the resistor R9 may be omitted from the front end circuitry 200, and the di/dt signal may be provided directly to the analog input PA1 of the processing unit 212.
In the presently disclosed embodiment, the transformer TR1 is configured to provide a low magnetizing inductance on its primary coil, and a high turns ratio on its secondary coil. In addition, the rectifying diodes D8-D11 are included in the front end circuitry 200 to format the information carried by the di/dt signal, and the resistor R9 is included in the circuitry 200 to limit peaking of the di/dt signal due to resonance, thereby facilitating the analysis of this information by the processing unit 212.
As a result, like the conventional front end circuitry 100 of
As described above, the dv/dt input sense circuit 204 receives the full wave rectified power line voltage VFW from the electromechanical interface 217. The charging capacitor C18 and the current limiting resistor R18 are configured to derive an AC signal z(t) (the “dv/dt signal”, see
in which “R” is the value of the resistor R19, “C” is the value of the capacitor C18, “x(t)” is the input of the R-C differentiator circuit, and “y(t)” is the output of the R-C differentiator circuit (see also
In one embodiment, the processing unit 212 measures the voltage of the di/dt signal provided to the analog input PA1 (see
Accordingly, whenever the voltage of the dv/dt signal z(t) exceeds VCC plus one voltage drop Vdiode of the diode D18 or D19, the diode D18 will be forward biased (“turned on”), thereby sinking current through the resistor R18 into VCC. The processing unit 212 reads the resulting voltage of the dv/dt signal z(t) as a logical high or “1”. In addition, whenever the voltage of the dv/dt signal z(t) is below VCC plus one diode voltage drop Vdiode, the diode D18 will not be turned on. In this case, the processing unit 212 reads the resulting voltage of the dv/dt signal z(t) as a logical low or “0”. It is noted that when the full wave rectified power line voltage VFW is provided as the input x(t) (see
The R-C differentiator circuit formed by the capacitor C18 and the resistor R19, and the zero-crossing detector formed by the resistor R18 and the diodes D18-D19, therefore cause the dv/dt signal z(t) at the analog input PA2 to respond as follows. If
then the processing unit 212 reads the voltage of the dv/dt signal z(t) as a logical high. Alternatively, if
then the processing unit 212 reads the voltage of the dv/dt signal z(t) as a logical low.
As shown in
It is noted that, in the presently disclosed embodiment, the dv/dt input sense circuit 204 derives the dv/dt signal from the full wave rectified power line voltage VFW to decrease the stress on the charging capacitor C18, thereby allowing the capacitor C18 to be implemented using a low cost electrical component. It should be understood, however, that the dv/dt signal may alternatively be derived from the half wave rectified power line voltage, or from the power line voltage directly. In addition,
In the presently disclosed embodiment, the arc fault detection apparatus analyzes changes in the power line current (di/dt) and the power line voltage (dv/dt) as follows. During a specified measurement period, the processing unit 212 polls the voltage states of the di/dt signal and the dv/dt signal at the analog inputs PA1 and PA2 (see
Next, the processing unit 212 (see
Similarly, the processing unit 212 analyzes the second data stream(s) by determining the number of times the dv/dt signal level exceeded the second specified threshold during the respective measurement periods. Specifically, the processing unit 212 maintains a second running count of the number of times the dv/dt signal level exceeded the second threshold during one or more successive measurement periods. In the event the second running count exceeds a second predetermined value, thereby indicating a possible electrical arcing condition, the processing unit 212 adds a specified quantity to the first running count, thereby increasing the speed and likelihood of tripping the electromechanical interface 217 to interrupt the power output to the load. For example, the second predetermined value may be equal to 4 state transitions of the dv/dt signal or any other suitable number of state transitions, and the specified quantity added to the first running count of the state transitions of the di/dt signal may be equal to 40 or any other suitable quantity. Such a specified quantity is not added to the first running count unless the second running count exceeds the second predetermined value to account for the dv/dt characteristics of the load.
In addition, the processing unit 212 analyzes the third data stream by accumulating the length of time during one or more measurement periods that the di/dt signal remained in a particular state, and by evaluating the accumulated time relative to the first running count of the number of times the di/dt signal level exceeded the first threshold. In the event the accumulated time that the di/dt signal remained in a particular state is high relative to the number of times the di/dt signal level exceeded the first threshold, the processing unit 212 inhibits the tripping of the electromechanical interface since such a condition may be indicative of a nuisance load. For example, the minimum length of the accumulated time during which the di/dt signal remained in a particular state may be equal to 2 msec or any other suitable length of time. In addition, the tripping of the electromechanical interface may be inhibited by increasing the trip threshold for activating the firing circuit or by any other suitable technique.
A method of analyzing the di/dt signal and the dv/dt signal generated by the di/dt input sense circuit 202 and the dv/dt input sense circuit 204 (see
Next, the processing unit counts the state transitions of the di/dt signal, as depicted in step 506 (see
Next, as depicted in step 508 (see
T=Tend−Tbeg,
Tacc=Tacc+T. (4)
A determination is then made as to whether the measurement period has expired, as depicted in step 510 (see
In the event the measurement period has expired, calculations are performed to discriminate electrical events and to determine whether to trip the electromechanical interface of the arc fault detection apparatus, as depicted in step 512 (see
It is appreciated that the functions necessary to implement the presently disclosed arc fault detection apparatus, including the di/dt input sense circuit 202 (see
It will further be appreciated by those of ordinary skill in the art that further modifications to and variations of the above-described low cost arc fault detection technique may be made without departing from the inventive concepts disclosed herein. Accordingly, the invention should not be viewed as limited except as by the scope and spirit of the appended claims.
Parker, Michael T., Pellon, Christian V., Nicolls, Christopher A.
Patent | Priority | Assignee | Title |
10509067, | Jul 06 2017 | MERSEN USA EP CORP | Method for AC arc fault detection using multidimensional energy points |
10680427, | Aug 25 2017 | Ford Global Technologies, LLC | Hurst exponent based adaptive detection of DC arc faults in a vehicle high voltage system |
8132459, | Sep 13 2008 | Texas Instruments Incorporated | System and method to determine mechanical resonance of an accelerometer |
8228103, | Feb 23 2009 | Moeller Gebaeudeautomation GmbH | Circuit breaker |
8346207, | May 25 2011 | Ian Alexander, Stewart | Fault location and control system for distribution lines |
9366713, | May 23 2013 | nVent Services GmbH | Arc fault detection system and method |
9366716, | May 23 2013 | nVent Services GmbH | Sub-harmonic arc fault detection system and method |
9551751, | Jun 15 2011 | UL LLC | High speed controllable load |
9581626, | Nov 14 2012 | Diehl AKO Stiftung & Co. KG | Circuit and method for detecting zero-crossings and brownout conditions on a single phase or multi-phase system |
9869719, | Jun 15 2011 | UL LLC | High speed controllable load |
Patent | Priority | Assignee | Title |
6504692, | Apr 06 2000 | Pass & Seymour, Inc | AFCI device which detects upstream and downstream series and parallel ARC faults |
6987389, | Nov 14 2000 | Pass & Seymour, Inc | Upstream/downstream arc fault discriminator |
7227729, | Sep 13 2005 | SENSATA TECHNOLOGIES MASSACHUSETTS, INC | Arc fault detection technique |
20040042137, | |||
20040066593, | |||
20070058304, |
Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
Dec 23 2005 | PELLON, CHRISTIAN V | Texas Instruments Incorporated | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 017425 | /0943 | |
Dec 28 2005 | PARKER, MICHAEL T | Texas Instruments Incorporated | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 017425 | /0943 | |
Dec 28 2005 | NICOLLS, CHRISTOPHER A | Texas Instruments Incorporated | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 017425 | /0943 | |
Dec 29 2005 | Sensata Technologies, Inc. | (assignment on the face of the patent) | / | |||
Apr 19 2007 | Texas Instruments Incorporated | SENSATA TECHNOLOGIES, INC | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 019220 | /0902 | |
Apr 30 2008 | SENSATA TECHNOLOGIES MASSACHUSETTS, INC | MORGAN STANLEY & CO INCORPORATED | SECURITY AGREEMENT | 021450 | /0563 | |
Apr 30 2008 | SENSATA TECHNOLOGIES, INC | SENSATA TECHNOLOGIES MASSACHUSETTS, INC | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 021018 | /0690 | |
May 12 2011 | MORGAN STANLEY & CO INCORPORATED | SENSATA TECHNOLOGIES FINANCE COMPANY, LLC | RELEASE BY SECURED PARTY SEE DOCUMENT FOR DETAILS | 026293 | /0352 | |
May 12 2011 | MORGAN STANLEY & CO INCORPORATED | SENSATA TECHNOLOGIES MASSACHUSETTS, INC | RELEASE BY SECURED PARTY SEE DOCUMENT FOR DETAILS | 026293 | /0352 | |
May 12 2011 | MORGAN STANLEY & CO INCORPORATED | SENSATA TECHNOLOGIES, INC | RELEASE BY SECURED PARTY SEE DOCUMENT FOR DETAILS | 026293 | /0352 |
Date | Maintenance Fee Events |
Feb 27 2012 | REM: Maintenance Fee Reminder Mailed. |
Jul 15 2012 | EXP: Patent Expired for Failure to Pay Maintenance Fees. |
Date | Maintenance Schedule |
Jul 15 2011 | 4 years fee payment window open |
Jan 15 2012 | 6 months grace period start (w surcharge) |
Jul 15 2012 | patent expiry (for year 4) |
Jul 15 2014 | 2 years to revive unintentionally abandoned end. (for year 4) |
Jul 15 2015 | 8 years fee payment window open |
Jan 15 2016 | 6 months grace period start (w surcharge) |
Jul 15 2016 | patent expiry (for year 8) |
Jul 15 2018 | 2 years to revive unintentionally abandoned end. (for year 8) |
Jul 15 2019 | 12 years fee payment window open |
Jan 15 2020 | 6 months grace period start (w surcharge) |
Jul 15 2020 | patent expiry (for year 12) |
Jul 15 2022 | 2 years to revive unintentionally abandoned end. (for year 12) |