systems and methods for adaptively compressing test data are disclosed. One such method comprises the steps of examining a test data file that includes a first plurality of data units corresponding to a first plurality of DUT pins and a second plurality of data units corresponding to a second plurality of DUT pins, compressing the first plurality of data units using a first compression technique, and compressing the second plurality of data units using a second compression technique.
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1. A method for adaptively compressing test data to be provided to a device under test (DUT), the method comprising the steps of:
examining a test data file that includes test data configured to enable testing the DUT, the test data file including a first plurality of data units and a second plurality of data units, the first plurality of data units corresponding to a first plurality of DUT pins, and the second plurality of data units corresponding to a second plurality of DUT pins, wherein the first plurality of DUT pins are clock-pins and the second plurality of DUT pins are non-clock-pins;
determining that the first plurality of data units have a first compressibility characteristic; and
determining that the second plurality of data units have a second compressibility characteristic.
5. A system for adaptively compressing test data to be provided to a device under test (DUT), the system comprising:
memory configured to store a test data file that includes test data configured to enable testing the DUT, the test data file including a first plurality of data units and a second plurality of data units, the first plurality of data units corresponding to a first plurality of DUT pins, and the second plurality of data units corresponding to a second plurality of DUT pins, wherein the first plurality of DUT pins are clock-pins and the second plurality of DUT pins are non-clock-pins; and
a processor that is operative to:
determine that the first plurality of data units have a first compressibility characteristic;
determine that the second plurality of data units have a second compressibility characteristic.
2. The method of
3. The method of
4. The method of
6. The system of
compress the first plurality of data units independently from the second plurality of data units.
7. The system of
8. The system of
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This application is a continuation-in-part of co-pending U.S. utility application titled “Systems and Methods for Testing a Device Under Test” having Ser. No. 10/620,191, filed on Jul. 15, 2003, and of U.S. utility application titled “Systems and Methods for Testing Performance of an Electronic Device” having Ser. No. 10/461,252, filed on Jun. 12, 2003 now U.S. Pat. No. 7,100,098, which are entirely incorporated herein by reference.
Testing the structure of an electronic device-under-test (DUT), such as, for example, a microprocessor, typically requires providing the device with input and then checking the device's output to determine if there are any defects. The input that is provided to the DUT is typically compressed prior to being provided to a testing device since the testing device has limited memory capacity. However, in some circumstances, there may not be enough computing resources available to adequately compress the data that is to be provided to the testing device. Therefore, there exists a need for systems and methods for addressing these and/or other problems associated with testing a DUT.
Systems and methods for adaptively compressing test data are disclosed. An embodiment of a method for adaptively compressing test data comprises the steps of: examining a test data file that includes a first plurality of data units corresponding to a first plurality of DUT pins and a second plurality of data units corresponding to a second plurality of DUT pins; compressing the first plurality of data units using a first compression technique; and compressing the second plurality of data units using a second compression technique.
Another embodiment of a method for adaptively compressing test data comprises the steps of examining a test data file that includes test data configured to enable testing the DUT, the test data file including a first plurality of data units and a second plurality of data units, the first plurality of data units corresponding to a first plurality of DUT pins, and the second plurality of data units corresponding to a second plurality of DUT pins; determining that the first plurality of data units have a first compressibility characteristic; and determining that the second plurality of data units have a second compressibility characteristic.
An embodiment of a system for adaptively compressing test data comprises memory configured to store a test data file that includes a first plurality of data units corresponding to a first plurality of DUT pins and a second plurality of data units corresponding to a second plurality of DUT pins, and a processor that is programmed to compress the first plurality of data units using a first compression technique, and to compress the second plurality of data units using a second compression technique.
Another embodiment of a system for adaptively compressing test data includes memory configured to store a test data file that includes test data configured to enable testing the DUT, the test data file including a first plurality of data units and a second plurality of data units, the first plurality of data units corresponding to a first plurality of DUT pins, and the second plurality of data units corresponding to a second plurality of DUT pins; and a processor that is programmed to determine that the first plurality of data units have a first compressibility characteristic, and that the second plurality of data units have a second compressibility characteristic.
Other systems, methods, features and/or advantages will be or may become apparent to one with skill in the art upon examination of the following figures and detailed description. It is intended that all such additional systems, methods, features, and/or advantages be included within this description and be protected by the accompanying claims.
In the drawings, like reference numerals designate corresponding parts throughout the several views. Furthermore, the components in the drawings are not drawn to scale.
Disclosed are systems and methods for adaptive compression of test data for testing an electronic device-under-test (DUT). As will be described in more detail, test data within a test data file may be separated based on one or more properties of the test data. For example, a first set of data corresponding to a first set of DUT pins is separated from a second set of data corresponding to a second set of DUT pins. In this manner, the first and second sets of data may be compressed using different compression techniques and may be provided to respective testing resources operating in different timing domains. The testing resources may then use the respective sets of data to test the structure, functionality and/or performance of the DUT via respective sets of DUT pins.
The scan converter 106 formats the test data 104 independently from the test data 105 to produce formatted test data 107 and 108, respectively, that are subsequently provided to a compression module 120. The formatted test data 108 has different properties than the formatted test data 107, including, for example, different timing complexity, vector data volume, and repetitiveness, among others. The compression module 120 compresses the formatted test data 107 and 108 to produce compressed test data 121 corresponding to a first set of DUT pins and compressed test data 122 corresponding to a second set of DUT pins, respectively. The compressed test data 121 and the compressed test data 122 are then provided to a DUT tester 109.
The compression module 120 also provides feedback 123 to the pin-grouping module 102-1 regarding the compressibility characteristics of data 107 and 108 received by the compression module 120. This feedback 123 enables the pin-grouping module to better separate test data 104 and 105 based on their compressibility characteristics.
The DUT tester 109 includes resources 112 coupled to the first set of pins of a DUT, and resources 111 coupled to a second set of pins of the DUT. The resources 112 may operate in a different timing domain than the resources 111. For example, the resources 112 may include processors running at a first clock speed, and the resources 111 may include processors running at a second clock speed. The resources 112 receive the compressed test data 121 and provide or receive corresponding test signals to/from the first set of DUT pins. On the other hand, the resources 111 receive the compressed test data 122 and provide or receive corresponding test signals to/from the second set of DUT pins.
The processor 202 is a hardware device for executing software, particularly that stored in memory 204. When the computer 200 is in operation, the processor 202 is configured to execute software stored within the memory 204, to communicate data to and from the memory 204, and to generally control operations of the computer 200 pursuant to the software.
The I/O interfaces 206 may be used to communicate with one or more peripheral devices including, for example, a printer, a copier, a keyboard, a mouse, and/or a monitor, etc. The I/O interfaces 206 may include, for example, a serial port, a parallel port, an IR interface, an RF interface, and/or a universal serial bus (USB) interface.
The memory 204 can include any one or combination of volatile and/or non-volatile memory elements now known or later developed. For example, the memory 204 may comprise random access memory (RAM), read only memory (ROM), a hard disk, a tape, and/or a compact disk ROM (CD-ROM), among others. Note that the memory 204 can have a distributed architecture, where various components are situated remote from one another, but can be accessed by the processor 202.
The software applications in memory 204 include an operating system (OS) 210, a compression module 120, a scan converter 106, and a pin-grouping module 102. The OS 210 essentially controls the execution of the other applications, and provides scheduling, input-output control, file and data management, memory management, and/or communication control, among other functionality. The pin-grouping module 102 may be used to identify test data corresponding to the first set of DUT pins and/or to separate test-data for clock pins from test-data for the second set of DUT pins. The scan converter 106 may be used to format the test data, whereas the compression module 120 may be used to compress the test data using multiple compression techniques, as will be discussed in more detail below. The scan converter 106, the compression module 120, and pin-grouping module 102 may each be a source program, an executable program (e.g., object code), a script, or any other entity comprising a set of instructions to be executed.
Furthermore, the scan converter 106, the compression module 120, and pin-grouping module 102 may each be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system or a processor-containing system. In the context of this disclosure, a “computer-readable medium” can be any means that can store, communicate, propagate, or transport a program for use by or in connection with the instruction execution system, apparatus, or device. The computer-readable medium can be, for example, among others, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, device, or propagation medium now known or later developed.
As a non-limiting example, assume that the following string of characters corresponds to input that is to be provided to a DUT pin 110:
TABLE 1
String Of Characters
11101000000000011110000110110101000000000000000000000000000001
The string of characters in Table 1 may be converted to the following three-character vectors:
TABLE 8
Three-Character Vectors
111, 010, 000, 000, 000, 111, 100, 001, 101, 101, 010, 000, 000,
000, 000, 000, 000, 000, 000, 000, 01X
A waveform entry may then be created for each distinct vector configuration encountered among the vectors in Table 8. The distinct vector configurations are as follows:
TABLE 9
Distinct Vector Configurations
111, 101, 100, 000, 001, 010, 01X
In the above example, waveform entries would not be created for the possible vectors 110 and 011, since such vectors were not encountered among the examined vectors. In cases where the input to a DUT pin 110 is more complex, the method 200-7 may be used to create a limited number of waveform entries representing a very small fraction of the number of possible waveform entries.
If the number of waveform entries corresponding to a waveform table 708 exceeds a predetermined limit, or if the waveforms entries would otherwise overwhelm resources of the DUT tester 109, then waveform entries corresponding to the least encountered type of vectors may be eliminated accordingly (e.g., until the number of waveform entries is equal to the predetermined limit). Alternatively, or additionally, the size of the waveform entries may be reduced to correspond to smaller vectors (i.e., vectors having fewer state characters). For example, if using three-character vectors results in a number of waveform entries that exceeds the pre-determined limit, then two-character vectors may be used instead.
The sequencer 1206 sequentially retrieves vectors (e.g., character sequences) from the vector memory 1202, causes the waveform table 708 to output respective waveform data, and causes the edge generator 1208 to output respective timing information.
If a vector retrieved from the vector memory 1202 represents data that is to be provided to the DUT pin 110, then the drive data formatter 1210 formats a waveform using the waveform data and timing information (provided by the waveform table 708 and the edge generator 1208, respectively). The drive data formatter 1210 then provides the formatted waveform to the driver 1212 which outputs the formatted waveform to the DUT pin 110.
If a vector retrieved from the vector memory 1202 corresponds to data that is to be received from the DUT pin 110, then the compare-data formatter 1216 formats a waveform using the waveform data and timing information (provided by the waveform table 708 and the edge generator 1208, respectively). The compare-data formatter 1216 then provides the formatted waveform to the error detector 1218. The error detector 1218 compares the formatted waveform to a corresponding waveform received from the DUT pin 110. Differences between the formatted waveform and the corresponding waveform received form the DUT pin 110 represent errors in the performance of the DUT 106. Information about such errors is stored in the error map 1220.
It should be emphasized that the above-described embodiments are merely possible examples, among others, of the implementations. Many variations and modifications may be made to the above-described embodiments. All such modifications and variations are intended to be included herein within the scope of the disclosure and protected by the following claims.
Hildebrant, Andrew S., Chindamo, Domenico
Patent | Priority | Assignee | Title |
8539278, | Oct 29 2010 | Infineon Technologies AG | Methods and systems for measuring I/O signals |
8654838, | Aug 31 2009 | MORGAN STANLEY SENIOR FUNDING, INC | System and method for video and graphic compression using multiple different compression techniques and compression error feedback |
8799703, | Oct 29 2010 | Infineon Technologies AG | Methods and systems for measuring I/O signals |
Patent | Priority | Assignee | Title |
5467087, | Dec 18 1992 | Apple Inc | High speed lossless data compression system |
5499248, | Feb 23 1993 | ADVANTEST SINGAPORE PTE LTD | Test vector generator comprising a decompression control unit and a conditional vector processing unit and method for generating a test vector |
5737512, | May 22 1996 | Teradyne, Inc. | Fast vector loading for automatic test equipment |
5883906, | Aug 15 1997 | Advantest Corp. | Pattern data compression and decompression for semiconductor test system |
6067651, | Feb 20 1998 | AVAGO TECHNOLOGIES GENERAL IP SINGAPORE PTE LTD ; AVAGO TECHNOLOGIES GENERAL IP PTE LTD | Test pattern generator having improved test sequence compaction |
6205407, | Feb 26 1998 | Credence Systems Corporation | System and method for generating test program code simultaneously with data produced by ATPG or simulation pattern capture program |
6327687, | Nov 23 1999 | Siemens Industry Software Inc | Test pattern compression for an integrated circuit test environment |
6546512, | Jun 15 1993 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Semiconductor integrated circuit having compression circuitry for compressing test data, and the test system and method for utilizing the semiconductor integrated circuit |
6560756, | Jul 02 2001 | LTX Corporation | Method and apparatus for distributed test pattern decompression |
6661839, | Mar 24 1998 | Advantest Corporation | Method and device for compressing and expanding data pattern |
6732312, | Mar 09 2001 | Advantest Corporation | Test vector compression method |
6751767, | Sep 29 1999 | NEC Electronics Corporation | Test pattern compression method, apparatus, system and storage medium |
6795944, | May 10 2001 | International Business Machines Corporation | Testing regularly structured logic circuits in integrated circuit devices |
6950974, | Sep 07 2001 | SYNOPSYS INC | Efficient compression and application of deterministic patterns in a logic BIST architecture |
20030217343, | |||
20040237014, | |||
20050097419, | |||
20060242502, |
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